Support All Industrial Ethernet Standards on Your Next "Drive" Design White Paper

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1 FPGA WP Coal Fossil Fuels Conversion Losses Petroleum 0.40 Natural Gas 7.29 Other Gases 0.09 Nuclear Electric Power 8.35 Renewable Energy 4.28 Other 0.16 Energy Consumed to Generate Electricity Gross Electricity Generation Unaccounted for 0.16 Net Electricity Imports 0.12 Net Electricity Generation Plant Use 0.79 T & D Losses 1.00 Residential 4.65 Commercial 4.51 Industrial 3.01 Transportation 0.03 Direct Use Innovation Drive San Jose, CA Altera ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS STRATIX Altera Altera Altera Altera Altera Altera Altera. ISO 9001:2008 Registered Altera

2 2 Power Generators T & D Utilities Substations Substations PMU Substations Control Center Substations PMU PMU Customers AMI AMI EV Electricity Communication f Altera FPGA

3 3 T&D AMI IEC FPGA Altera

4 Altera FPGA

5 5 Operating Room Switchyard Fiber Optic Cable Copper Wire Sensors and Actuators Sensors and Actuators Conventional Substation Power Lines Fiber Optic Cable (Station Bus) IEC Implementation Fiber Optic Cable (Process Bus) S/A S/A S/A S/A S/A S/A FPGA Altera

6 6 Goose Sampled Values Client/Server Goose Sampled Values Mapping Layer Mapping Layer 7 Application 7 Application 6 Presentation 6 Presentation ISO Stack Layer Session Transport (TCP) Network (IP) ISO Stack Layer Session Transport (TCP) Network (IP) 2 Data Link 2 Data Link 1 PHY (Ethernet) 1 PHY (Ethernet) ( ) ( ) 800 ms 400 ms 12 ms 4 ms 12 ms 4 ms 8 ms 4 ms <1 ms < Altera FPGA

7 7 IEC PRP Device LAN A LAN B PRP Device LAN A LAN B LAN A LAN B LAN A LAN B LAN A LAN B LAN A LAN B LAN A LAN B LAN A LAN B LAN LAN PRP Device PRP Device PRP Device PRP Device PRP Device LAN Device LAN Device FPGA Altera

8 8 Sending Node HSR Device Port A Port B HSR Device Port A Port B Port A Port B HSR Device Port A Port B Port A Port B Port A Port B HSR Device HSR Device HSR Device IEC f Altera FPGA

9 FPGA SoC 9 IEEE Master Clock Slave Clock t 1 SYNC (t 1 ) t 2 t 4 Delay_Request Delay_Response (t 4 ) t 3 (t 2 - t 1 ) + (t 4 - t 3 ) Avg Path Delay t d = Offset From Master t 0 = (t 2 - t 1 ) - t d 2 UDP/IP Repeat Each Second FPGA SoC FPGA Altera

10 10 FPGA SoC DC/DC DC/AC Line Filter Switch EMI Filter To Meter/ Grid V/I Gate Drivers V/I Gate Drivers/Opto Isolators V/I V PV/I PV V DC/I DC VAC/I AC PWM PWMs FPGA V PV/I PV MPPT V DC V AC V REF V Control PLL I r I REF I AC I Control DSP/FPGA Analog Interface Memory Comms MCU Keypad LCD Memory Altera FPGA

11 FPGA SoC 11 T&D Secure Gateway Router Control Center GPS Receiver Internet Other Secure Substations Controller (PLC) IEC (Substation Bus) IEC (Process Bus) RedBox = Redundancy Box Controller (PLC) IEC Ethernet Switches Industrial Computer RedBox Remote Operator Legacy Bus (e.g., CAN, etc.) Intelligent IED IED IED Electronic Devices I/O Relays, Switches & Reclosers HV Wiring MU Merging Unit HV Wiring Switchyard FPGA Altera

12 12 FPGA SoC Port A Port B FPGA (Fault Detection Algorithms) Fieldbus 10/100/1000 (IEEE 1588) DSP (Fault Detection Algorithms) CPU (Housekeeping, MMI Communication) Keypad/ Display Memory Modbus Time Sync Analog Interface (V-I Sense) 16 bit Relays HV Wiring Altera FPGA

13 FPGA SoC 13 Programming Software RTOS Synchronization Processor PRP/HSR Fieldbus Digital I/O Modules Analog I/O Modules Backplane T&D Fieldbus (Optional) Port A PHY MII/GMII MAC Registers CAN UART Port B PHY MII/GMII MDIO I 2 C MAC MMD MII/GMII STA MAC CPU Aux PHY MII/GMII MAC IEEE 1588 FPGA Altera

14 14 FPGA SoC T&D GPS Receiver Modem Port A PHY Port B PHY Microprocessor DSP 16 bit Altera FPGA

15 15 Port A PHY Port B PHY Display Keyboard Graphics Controller Microprocessor Communications 16 bit DSP CAN UART Equipment Operator Terminals Service Life (Years) 6-10 Communications Secondary Equipment, IEDs Switchgear/Transformers FPGA Altera

16 16 Altera FPGA SoC Altera FPGA

17 Altera FPGA SoC 17 Altera FPGA SoC Performance 4,000 DMIPS at < 1.8 W ARM Cortex-A9 (800 MHz) L1 Cache NAND Flash L1 Cache QSPI Flash Control ARM Cortex-A9 (800 MHz) L1 Cache 64 KB RAM Ethernet (x2) CAN, SPI, UART (x2) Communications Fieldbus, IEC Compatible PRP/HSR Reliability Highest Level of ECC Coverage USB (x2) DMA (x11) Timers (x11) JTAG FPGA Configuration HPS to FPGA FPGA to HPS GPIO Power and Footprint FPGA and MCU Have Up to 30% Lower Power Consumption and Up to 50% Footprint Reduction Performance Two Hard-Coded Memory Controllers Hard Multi-Port DDR SDRAM Controller (x2) FPGA Fabric PCIe Transceivers Flexibility, Reliability, and Upgrades RISC Cores, Variable Precision DSP, Soft-Coded Peripherals & Hardware Accelerators FPGA Altera

18 18 Altera FPGA SoC Altera FPGA

19 FPGA Altera

solutions guide

solutions guide Tridium 01 Table of Contents Tridium... 1 Frameworks... 4 Niagara AX Framework... 5 Sedona Framework... 6.... 7 NPM... 8 Sedona Chip... 9 AX Supervisor... 10 AX SoftJACE...11...12. JACE