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1 TERM PROJECT R

2 Sigma-Delta Modulation (1), (A/D,D/A) (Quantization Error), Sigma-Delta Modulation, ADC, DAC Fractional N Frequency Synthesizer,,,, (2) Ó-Ä ADC cascaded integrator-comb filter( ), Ó-Ä modulation, reference[9], Ó-Ä modulation,, SECTION 1. : Sigma-Delta Modulation b-bit ADC( Ft Hz); Rfs, (voltage step)äv=rfs / (2^b - 1) Rfs / (2^b), error -ÄV/2 ÄV/2, error voltage RMS quantization noise power e =ÄV /12;, 0 ~ Ft/2 [4] ( 2^b 2 b )

3 Low sampling rate Ft /2 Noise density Frequency Fm : signal band (0 ~ Fm) High sampling rate Ft/2 noise power per unit bandwidth(noise density) Pe,n =(ÄV /12) / (Ft/2) in-band noise power Ptotal = Pe,n Fm = { (ÄV /12) / (Ft/2) } Fm ----( * ) = { ( (Rfs / (2^b)) /12) / (Ft/2) } Fm = (ÄV /12)(1/OSR) oversampling ratio (OSR) M= Ft / (2 Fm) Ft = (2 Fm) M=1 b Ptotal = (Rfs / (2^ )) /12 =b M OSR double ( M ) ={ ( (Rfs / (2^b)) /12) / (Ft/2) } Fm =( (Rfs / (2^b)) /12) (1/M) (resolution) 0.5 (bit) & Ptotal 3dB ( b) b ADC [4], (2^b)(ÄV/2) signal power Ps={[(2^b)(ÄV/2)]/ 2}

SNR=10 [ Ps/ Ptotal ] =6.02 b +1.76 + 10 (OSR) 6.02dB 1 Example 1 [7] 1 ADC 6dB SNR, Fm=25KHz, 96dB SNR( 16 ),?

4 SNR=10 [ Ps/ Ptotal ] =6.02 b (OSR) 6.02dB 1 Example 1 [7] 1 ADC 6dB SNR, Fm=25KHz, 96dB SNR( 16 ),? 96-6=90 db SNR double OSR Ptotal 3dB SNR 3dB OSR=2^30 Ft=2^30 (2 Fm)=54000 GHz Oversampling SNR! Oversampling with Noise-Shaping( ÓÄM ), : (a) ÓÄ Modulator (b) modulator ( Ft >> Fm ) (transfer function) STF (Z) Y(Z)/U(Z) = H(Z) / (1+H(Z)) (quantization error) N TF (Z) Y(Z)/E(Z) =1 / (1+H(Z)) (superposition) Y(Z)= STF (Z) U(Z) +N TF (Z) E(Z) (0,Fm), N TF (Z) E(Z) N TF (Z) ---> 0 N TF (Z) Zeros H(Z) Poles, H(Z), 0 Fm magnitude! Low Pass! N TF (Z) Zeros H(Z) Poles baseband

Modulator modulation noise power spectral density Py(f) = N TF (Z) Pe,n [2(ð f / Ft) ] (ÄV /12) / (Ft/2) = 2/3 ð ÄV ² ³, f << Ft sigma-delta ADC in-band noise power P total,sd =

5 (c) First-Order Noise Shaping (discrete-time integrator) H(Z)= 1/ (Z-1) H(Z) Pole Z=1 N TF (Z) Zero Z=1 dc( Z=exp( jùt ) ) (transfer function) STF (Z) Y(Z)/U(Z) = H(Z) / (1+H(Z))=1/Z 1 ; ùt (quantization error) N TF (Z) Y(Z)/E(Z) =1 / (1+H(Z))=1-1/Z High Pass N TF (Z) = 2sin(ð f / Ft) Z=exp( jùt )=exp( j 2 ð f T) f << Ft N TF (Z) 2(ð f / Ft) ÓÄ Modulator modulation noise power spectral density Py(f) = N TF (Z) Pe,n [2(ð f / Ft) ] (ÄV /12) / (Ft/2) = 2/3 ð ÄV ² ³, f << Ft sigma-delta ADC in-band noise power P total,sd = Py(f) df =2/9ð ÄV ³ ³, ( * ), Oversampling in-band noise power Ptotal, os= Pe,n Fm = { (ÄV /12) / (Ft/2) } Fm, noise performance 10 log 10 ( Ptotal, os / P total,sd ) = log 10 M db, (OSR M)

6 OSR 2 6dB 1 (sigma-delta ADC Oversampling ADC OSR ), (2^b)(ÄV/2) signal power Ps={[(2^b)(ÄV/2)]/ 2} SNR=10 [ Ps/ Ptotal,sd] =6.02 b (M) 6.02dB 1 (OSR M) OSR (sigma-delta ADC Oversampling ADC ), modulator, ( dc) (idle tone),,,, audio signal, sigma-delta modulator [3][7][8] sigma-delta modulator (transfer function) STF (Z) 1/Z (quantization error) N TF (Z) (1 1/Z) SNR=10 [ Ps/ Ptotal,sd] =6.02 b (M) OSR 2 SNR 15dB 2.5 Example1 sigma-delta modulator Ft = 2^((90+5)/9) 2 Fm = 75MHz sigma-delta modulator Ft = 2^((90+13)/15) 2 Fm = 5.8MHz CD Fm 24KHz 44.1KHz 2.586MHz N TF (f) sigma-delta modulator Noise Power SNR ; Noise Power,, sigma-delta modulator, error-feedback

7 ERROR-FEEDBACK ARCHITECTURE (transfer function) STF (Z) 1 (quantization error) N TF (Z) G(Z) G(Z)=1 1/Z, N TF (Z)=1 0.99/Z zero dc H(Z) ;,, error feedback! (! )

Three-Stage MASH Operation[5][6] ADC, triple-integration noise shaping, 3 270 oscillation triple-integration noise shaping, first-order Ó-Ä quantizers three-stage MASH,

8 Three-Stage MASH Operation[5][6] ADC, triple-integration noise shaping, oscillation triple-integration noise shaping, first-order Ó-Ä quantizers three-stage MASH, (MASH 1-1-1) Single-bit Ó-Ä modulation Multi-bit Ó-Ä modulation [10] SECTION 2. DIGITAL Sigma-Delta Modulator : digital sigma-delta modulator digital phase accumulator(dpa) first

order sigma delta modulator first order digital phase accumulatore [9] difference equation digital phase accumulatore(dpa) Rn=Rn-1+Kn-1-M carry[rn-1+kn-1] carry(x)=1 carry(x)=0 when X>=M otherwise

9 order sigma delta modulator first order digital phase accumulatore [9] difference equation digital phase accumulatore(dpa) Rn=Rn-1+Kn-1-M carry[rn-1+kn-1] carry(x)=1 carry(x)=0 when X>=M otherwise carry(x)=(1+sign(x-m))/2 (Rn+Kn-M)=(Rn-1+Kn-1-M)+Kn-M/2-M/2 sign(rn-1+kn-1-m) Let Xn Rn+Kn-M Xn=Xn-1+Un-M/2 sign(xn-1) modulator[9] Un Kn-M/2, first order sigma delta DPA sigma delta DAC Fractional-N frequency synthesizer (bit-width) digital phase accumulator(dpa),, pipeline carry save adder( ), chip area, speed trade off, one bit pipeline, [10]

10 SECTION 3 First order modulator (frequency domain) First order modulator (time domain)

: : x(0)=0.1, two-level quantizer +/ 1 u(n)= y(n) x(n) n x(n) x(n+1) y(n) e(n) 0 0.1-0.5667 1 0.9 1-0.5667 0.7667-1 -0.

11 : : x(0)=0.1, two-level quantizer +/ 1 u(n)= y(n) x(n) n x(n) x(n+1) y(n) e(n) y(n)= [1+( 1)+1]/3 = 1/3 y(n) Low Pass Filter LPF, frequency domain [4] H(f)=[ zeros(1,n-5) 0.5 1] Matlab Code[4] clear; wo=2*pi*0.01; N=input('Type in the length of input sequence='); n=1:1:n;

12 m=(n-1); A=input('Type in the input amplitude='); x=a*cos(wo*m); axis([0 N ]); plot(m,x); xlabel('time');ylabel('amplitude'); title('input analog signal'); pause y=zeros(1,n+1); v0=0; for k=2:1:n+1; vl=x(k-1)-y(k-1)+v0; if vl >= 0; y(k)=1; y(k)=-1; end nxx(k)=vl; v0=vl; end pause yn=y(2:n+1); axis([0 N ]); stairs(m,yn); xlabel('time');ylabel('amplitude'); title('output of sigma-delta quantizer'); Y=fft(yn); pause H=[ zeros(1,n-5) 0.5 1]; YF = Y.* H; out=ifft(yf); axis([0 N ]); plot(m,out); xlabel('time');ylabel('amplitude'); title('lowpass filtered output'); pause plot(20*log(abs(y)/100))

13 :

14 Verilog HDL Implementation A. 2 bits first order digital sigma delta modulator `timescale 1 ns/ 10 ps module one_bit_acc(sum,c_out,x,c_in,clk,reset); output sum,c_out; input x,clk,reset,c_in; reg q; wire d; assign d=sum; assign sum=x^q^c_in;

15 assign c_out=(x & q) ((x q) & c_in); clk or negedge reset) if(!reset) q=1'b0; q=d; endmodule module sdm; reg[1:0] A; reg reset,mhz50; wire sum0,c_out0,sum1,c_out1; initial begin // $timeformat (-9,1,"ns",15); $dumpfile ("sdm.vcd"); $dumpvars (2,sdm); reset = 0; mhz50 = 0; A = 2'b 11; #100; reset = 1; #1000 $dumpoff; end $finish; always begin #10 mhz50 = ~mhz50; end

16 one_bit_acc oba0(sum0,c_out0,a[0],1'b0,mhz50,reset); one_bit_acc oba1(sum1,c_out1,a[1],c_out0,mhz50,reset); endmodule mhz50 system clock A = 3 2 bits DPA c_out = ( )/4=3/4 B. 2 bits MASH 1-1 `timescale 1 ns/ 10 ps module one_bit_acc(sum,c_out,x,c_in,clk,reset); output sum,c_out; input x,clk,reset,c_in; reg q; wire d; assign d=sum;

17 assign sum=x^q^c_in; assign c_out=(x & q) ((x q) & c_in); clk or negedge reset) if(!reset) q=1'b0; q=d; endmodule module sdm; reg[1:0] A; wire[2:0] com; reg reset,mhz50,q_c_out1b; wire sum0,c_out0,sum1,c_out1,sum0b,c_out0b,sum1b,c_out1b; initial begin // $timeformat (-9,1,"ns",15); $dumpfile ("sdm.vcd"); $dumpvars (2,sdm); reset = 0; mhz50 = 0; A = 2'b 11; #100; reset = 1; #1000 $dumpoff; end $finish; always begin #10 mhz50 = ~mhz50; end one_bit_acc oba0(sum0,c_out0,a[0],1'b0,mhz50,reset);

one_bit_acc oba1(sum1,c_out1,a[1],c_out0,mhz50,reset); one_bit_acc oba0b(sum0b,c_out0b,sum0,1'b0,mhz50,reset); one_bit_acc oba1b(sum1b,c_out1b,sum1,c_out0b,mhz50,reset); always @(posedge mhz50 or

18 one_bit_acc oba1(sum1,c_out1,a[1],c_out0,mhz50,reset); one_bit_acc oba0b(sum0b,c_out0b,sum0,1'b0,mhz50,reset); one_bit_acc oba1b(sum1b,c_out1b,sum1,c_out0b,mhz50,reset); mhz50 or negedge reset) if(!reset) q_c_out1b=1'b0; q_c_out1b=c_out1b; assign com={((~c_out1) & (~c_out1b) & q_c_out1b),(c_out1 & c_out1b & (~q_c_out1b)),(c_out1^c_out1b^q_c_out1b)}; endmodule mhz50 system clock A = 3 2bits DPA c_out = ( )/8=3/4 C. 9 bits PIPELINE first order sigma-delta modulator `timescale 1 ns/ 10 ps module pipeline_sdm1(sum_t,c_out,a,mhz50,reset); output[8:0] sum_t; output c_out; input[8:0] A; input mhz50,reset; reg q_c_out0,q_c_out1; reg[2:0] q,buftmp,buf1tmp,buf2tmp;

19 reg[5:0] out; wire[8:0] sum; wire c_out0,c_out1,c_out1; three_bit_acc tda0(sum[2:0],c_out0,a[2:0],1'b0,mhz50,reset); mhz50 or negedge reset) if(!reset) q_c_out0=1'b0; q_c_out0=c_out0; mhz50 or negedge reset) if(!reset) q[2:0]=3'b000; q[2:0]=sum[2:0]; mhz50 or negedge reset) if(!reset) out[2:0]=3'b000; out[2:0]=q[2:0]; mhz50 or negedge reset) if(!reset) buftmp[2:0]=3'b000; buftmp[2:0]=a[5:3]; three_bit_acc tda1(sum[5:3],c_out1,buftmp[2:0],q_c_out0,mhz50,reset); mhz50 or negedge reset) if(!reset) q_c_out1=1'b0; q_c_out1=c_out1; mhz50 or negedge reset) if(!reset) out[5:3]=3'b000; out[5:3]=sum[5:3];

20 mhz50 or negedge reset) if(!reset) buf1tmp[2:0]=3'b000; buf1tmp[2:0]=a[8:6]; mhz50 or negedge reset) if(!reset) buf2tmp[2:0]=3'b000; buf2tmp[2:0]=buf1tmp[2:0]; three_bit_acc tda2(sum[8:6],c_out2,buf2tmp[2:0],q_c_out1,mhz50,reset); assign sum_t={sum[8:6],out[5:3],out[2:0]}; assign c_out=c_out2; endmodule module three_bit_acc(sum,c_out,a,c_in,mhz50,reset); input[2:0] A; output[2:0] sum; input reset,mhz50,c_in; wire sum0,c_out0,sum1,c_out1,sum2,c_out2; output c_out; assign sum={sum2,sum1,sum0}; assign c_out=c_out2; one_bit_acc oba0(sum0,c_out0,a[0],c_in,mhz50,reset); one_bit_acc oba1(sum1,c_out1,a[1],c_out0,mhz50,reset); one_bit_acc oba2(sum2,c_out2,a[2],c_out1,mhz50,reset); endmodule

21 module one_bit_acc(sum,c_out,x,c_in,clk,reset); output sum,c_out; input x,clk,reset,c_in; reg q; wire d; assign d=sum; assign sum=x^q^c_in; assign c_out=(x & q) ((x q) & c_in); clk or negedge reset) if(!reset) q=1'b0; q=d; endmodule module sdm; reg[8:0] A; reg reset,mhz50; wire[8:0] sum; wire c_out; initial begin // $timeformat (-9,1,"ns",15); $dumpfile ("sdm.vcd"); $dumpvars (2,sdm); reset = 0; mhz50 = 0; A = 9'b ; #100; reset = 1;

clock A = 256(100H) 9bits DPA c_out = (1+0+1+0+1+0+.

22 #10000 $dumpoff; end $finish; always begin #10 mhz50 = ~mhz50; end pipeline_sdm1 sdm1(sum,c_out,a,mhz50,reset); endmodule mhz50 system clock A = 256(100H) 9bits DPA c_out = ( )/(2^9) = 256/512 = 1/2 (Contribution) 1. sigma delta modulation 2. sigma delta modulation

23 3. Matlab,Simulink,System View 4. Verilog HDL Digital Sigma Delta Modulator (Conclusions) sigma-delta modulation,, sigma-delta ADC, Verilog HDL 2-bit MASH 9-bit first order pipeline DPA,, Simulink,System View tools, sigma-delta modulation,,, ;,! bye bye! (Reference) [1] 1962 IRE Transactions on Space Electronics and Telemetry A Telemetering System by code Modulation----Ä-Ó Modulation [2] 1983 IEEE Trans. Commun Design Methodology for ÓÄM [3] Communication Systems Haykin [4] Digital Signal Processing Mitra [5] Delta-Sigma Data Converter IEEE press [6] Oversampling Delta-Sigma Data Converters IEEE press [7] Analog Integrated Circuit Design David A. Johns & Ken Martin [8] ---- [9] 1999 IEEE Transactions on vehicular technology Design and Realization of a Digital Delta Sigma modularor for Fractional-n Frequency Synthesis [10]Katy Falakshahi, High-speed,High-Resolution D/A Conversion in CMOS,PhD defense slides,august [11] IEEE Trans. on circuits and systems-ii: Analog and Digital signal processing, VOL.47,NO. 11 November 2000 Efficient Modified-Sinc Filters for Sigma-Delta A/D Converters [12]Te chniques for High Data Rate Modulation and Low Power operation of Fractional-N Frequency Synthesizer by Michael Henderson Perrott [13]

24 Cascaded Integrator-Comb Filter sigma delta ADC, Quantization Noise, Desired Signal Oversampling, decimated output [13]:

25 Quantization Noise, Cascaded Integrator-Comb Filter, (multirate signal processing), [11] Decimation filter,, Stopband ( stopband, Decimation Aliasing effect)

幻灯片 1

幻灯片 1 Digital Signal Processing(DSP) : 203 : 0531-88364509 Email: jiangmingyan@sdu.edu.cn : ---- ---- JMY Copyright Reserved, SDU, 1 / 69 : (,, 2007 64 48 16 1 8 1. 2 2. 6 3. 6 4. 8 5., FFT 8 6. 6 7. 8 8. 4

穨R _report.PDF

穨R _report.PDF