浮点运算单元的设计与实现

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誓璎悠康
6 years ago
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2 32 IEEE (A+B C) 4 SRT Verilog HDL 0.18µm CMOS - i -

3 Abstract Floating point representation is the science notification in computer, and floating point operations are the major part of multimedia calculations, so floating point unit is an important part in the design of all kinds of processors and it determines the performance. This article describes design and implementation of a 32-bit floating point unit and related research results, which is archived as my undergraduate thesis. The unit is fully compliant with the IEEE 754 floating point standard, and supports 32-bit single precision floating point operations including addition, multiplication, division, square root operation, and conversion between integers and floating point numbers. Multiply-add fused scheme is adapted in front end arithmetic design, to calculate addition and multiplication (A+B C). The processing of denormalized numbers is merged into the dataflow. In order to narrow the width of the main adder, normalization shift is performed before addition. Along with the significant bits wide main adder, rounding is performed on-fly. The synthesis result proves that the delay of MAF unit decreased a lot, compared with previous designs. The MAF unit is divided into 3 pipeline stages, so that the throughput increased a lot. Radix-4 SRT algorithm is implemented for calculating division and square root literally. Different rounding schemes are chose for different representation of intermediate results. As a result, the iteration cycles are limited and the arithmetic is efficient. The whole design is described in Verilog HDL and simulated. The design is mapped on SMIC 0.18µm CMOS technology as an automatic standard cell implementation. The post-simulation result proves that it achieved the goal. Key Words: FPU (floating point unit), MAF (multiply-add fused), denormalized number processing, rounding - ii -

4 ... I ABSTRACT...II...III (ROUNDING) EXCEPTION SRT iii -

5 iv -

6 1.1 0 (Float Point Unit) FPU 3D FPU FPU ALU CPU 486 Intel i80486dx CPU MMX 3DNow! CPU DSP FPU FPU FLOPS Floating Point Operations Per Second SONY IBM TOSHIBA ISSCC05 90nm SOI Cell SPE (Synergistic Processing Element) 4GHz SPE 32GFLOPS SONY Play Station 3-1 -

7 2 Intel P AMD Athlon 16 4 P4 Athlon Intel Pentium SMIC 0.18µm CMOS MAF(Multiply-add fused) A+B C A B C MAF IBM z990 [1] MAF MAF Z990 (millicode) [2] [3] MAF - 2 -

8 [3] MAF MAF A/B [1] 4 SRT AMD Athon SQRT(A) z990 FPU 2 SRT 1 20 P4 23 [4] 4 SRT 2 14 IEEE 754 [4] MAF Verilog HDL RTL Synopsys VCS Synopsys Design Complier Synopsys Astro IBM z990 FPU 0.13µm CMOS 1.2GHz 156MHz IEEE 754 FPU FPU - 3 -

9 IEEE 754 [4] IEEE ±S B E s e f s(sign) 0 1 S(significand) 1 1 (mantissa) (fraction) E(exponent) ~255 1~ ~ B(base) IEEE

10 /1 0/1 0/ <e< f f NaN ±2 e f ± f 2.2 (rounding) IEEE (round to nearest/even) IEEE + - (interval arithmetic) - 5 -

11 IEEE < < NaN NaN (signaling)nan NaN (quiet)nan NaN - 6 -

12 1) NaN 2) ( ) + (+ ) 3)0 4)0/0 / 5) x REM 0 REM y 6) x x + x = x (-x) x IEEE [2 n 2 n+1 ] 0 0 IEEE [ ]

13 (gradual underflow) 2.4 Exception IEEE NaN overflow 1) 2) 3) 4) - 8 -

14 2.4.4 underflow / IEEE 754 [4]

15 [1] [6] 1 C B [7] (CSA, Carry-Save Adder) 48 A 3:2CSA A B C A B C B C 74 A 48 B C 3:2 CSA [3] [3] [3] [6]

16 1 [1] [2] A B C A B C A B C B C CSA 3 2 CSA MAF MAF

17 ExpA sub ExpB ExpC A 24 Bit invert bits of A and 0's if add or bits of ~A and 1's if sub B 24 C 24 mul record ExpA LeadA ExpB LeadB ExpC LeadC Calculate the exponent of intermediate results 27-d 74-bits alignment shifter Sticky bit st1 calculation Part of sticky MSB 48 LSB sub 13:2 CSA tree ~st1 denormalized number processing Adjustment for potential denormalized results 3:2 CSA HA Carry word HA Sum word HA inv.inputs Carry word LZA Logic for the LSBs MSBs processing Part of Dual adder mux Part of Dual adder 24 bits 49 bits XX GG XX.PP complement Sign detection to the add/round module 75-bits 75-bits normalization normalization shifter shifter Bits shifted-in during normalization Carry word: Sum word: (if complement=0) (if complement=1) bits 50 bits X. X.... X X X X. X.... X X X L bit st1 complement Exponent calculationone bit correction Rest of 22-bits Flagged prefix adder Rounding Correction Carry and sticky bits calculation Rounding Mode RN=1 if rounding to nearest RI=1 if rounding to infinity Exponent Resul MAF

18 3 1 B C (Booth) C 24 C 0 13 B 0 ±1 ±2 3: [7] 2 A B C A+ B C A A (a) 24 A A B C d = exp(a) (exp(b) + exp(c)) 3.2.2(b) d = 27 d 27 A B C B C B C A exp(a) d 27 A 0 1 shift amount = 27 d 75 d A (sticky bit)

19 st A A A B C (a) 2 24 A 51 B C (b) (c) 49 3:2 CSA B C A 26 3:2CSA :2CSA (d) 3:2CSA MAF 3 1 A B C 1 24 lead 0 lead=0-14 -

20 75 B C 26+leadB+leadC 27+leadB+leadC A leada + shift amount A B C :2 (Carry Save Adder) A B C A st B C 0 3:2 CSA (d) B C 48 B C 3:2 CSA B C B C [0,4) 4 11.*+01.* 1X.*+1X.* 01.*+11.* B C B C [1,4) 10.*+01.* 1 B C [0,2) 2 (1X.*+XX.* XX.*+1X.*) B C multi-carry 3:2 CSA carry[50] A 49 3:2 CSA :2 CSA

21 49 multi-carry 0 carry[50] multi-carry 1 carry[50] multi-carry 1 carry[50] :2 CSA (Leading Zeros Anticipator) 1 3:2 CSA A A 51 [8] 1 [9] [8]

22 T = A B, G = AB, Z = AB f = TT ( i+ 1 i+ ) 1( 1 ) 1 i i+ i+ 1 f = T G Z + Z G + T Z Z + GG, i> 0 i i 1 i i i i (3.1) 51 A A t[n]^ (~z[n+1]) 1 A t[n]^ (~z[n+1]) 1 A A t[n] ^ (~g[n+1]) 0 A t[n] ^ (~g[n+1]) 51 [3]

23 Lz 75 a) A 0 A 2525 A B C 2 24 A B C 3 A B C 3 A ( ) A A A A 25 B C b) ( ) A 1 A

24 c) A 25 A B C B C ExpBC = + ExpC Ebias A Lz ExpR 1 ExpR = ExpBC Lz Lz Lz ExpBC + 2 Lz > ExpBC ExpR ARS NLS ExpR NLS ExpR ARS = 0 0 ExpA ARS <25 ARS ExpA ARS <25 A ARS ExpA 0<ARS<25 A ARS - 1 ExpA + 1 ARS 25 Lz ExpBC Lz ExpBC Lz -3 ARS 25 Lz > ExpBC ExpBC 1 ARS 25 Lz ARS< IEEE A B C B C

25 3 [3] NLS [10] MAF A+B A+B+1 [11] flagged prefix adder [11] IEEE 754 IEEE

26 3.3 [10] MAF (Eone ) 0 C F, S F, R F C I, S I, R I m0, m1 n0, n1 l g(m) st C S R C S R S I C I R I S F C F R F R = S + C + 1 ( 1 ) R I = S I + C I R F = S F + C F S F,C F [0,1) R F [0,2) g R F st2 st1 49 R F 49 1 st2 r 1 R F

27 r c R F m R F l R I R F n0 n1 0 1 R I m0 m1 p R F l p R I X 2 = 4 R I 25 R F R I,R I l p c lp fix0,fix1 Sns0, Sns1, Sls0, Sls1 50 m0,m1 n0,n1 c,m st1 st st2 NOR 1 Eone [10] IEEE

28 3.3.1 p=0 RF (LS) (NS) [0,0.5) RI (n, l, st): (X0X): RI (010): RI (011): RI + 2 (11X): RI + 2 [0.5,1) (l, st): (00): RI (01): RI ( l 1) (n, l, st) (X0X): RI (X1X): RI+2 (1X): RI+2 ( l 0) [1,1,5) (l): (0): RI ( l 1) (n, l, st): (000): RI (1): RI +2 ( l 0) (001): RI + 2 (01X): RI + 2 (1XX): RI + 2 [1.5,2) (l, st): (0X): RI + 2 RI + 2 (10): RI +2 ( l 0) (11): RI + 2 Sns0 Sns1 24 R I R I +2 Sls0 Sls1 24 R I R I l NS LS R1 R2 R3 R4 R F Sls0 & ~ ~ Sls0 = LS & (R1 R2 & ~l R3 & ~l) LS LS = ~m0 & (R1 R2) ~m1 & (R3 R4) R1 = ~c & ~m R2 = ~c & m R3 = c & ~m

29 R4 = c & m m0 0 R I m0 = R I [23] m1 1 R I R I +1 R I R I +2 m1 = R I [23] & l (R I +2)[23] & ~l Eone LS = ~Eone & (~m0 & (R1 R2) ~m1 & (R3 R4)) Sls1 Sns1 Sns0 fix0 fix1 R I +3 R I 1 1 p = C F.m S F.m 24 R I +p R I +p RF (LS) (NS) [0,0.5) RI+p (lp): (0): RI + p (1): RI + p + 2 [0.5,1) (l, p): (00): RI + p ( l 1) ( lp, p) (00): RI + p +2 (10): RI + p + 2 ( l 0) (01): RI + p (X1): RI + p (10): RI + p + 2 (11): RI + p + 2 [1,1,5) RI + p (1): RI +2 ( l 0) [1.5,2) (lp): (0): RI + p ( l 0) (1): RI + p + 2 ( l 1) (lp): (0): RI + p (1): RI + p + 2 RI + p + 2 Sls0 Sls1 Sns1 Sns0 fix0 fix1-24 -

30 MAF RN p=0 Slns0 = ~m0 & ~c & (~m ~l) ~m1 & c & ~m & ~l Sls1 = (~m0 & ~c & m & l ~m1 & c & (m l)) & ~m1 Sns0 = m0 & ~c & ( ~l ~m & ~n0 & ~st ) m1 & c & ~m & ~n1 & ~l & ~st Srs1 = m0 & l & ~c & (n0 st m) m1 & c & (n1 l st m)) ( ~m0 & ~c & m & l ~m1 & c & (m l)) & m1 fix0 = ~m0 & l & ~c & m ~m1 & l & c & (~m ~st) fix1 = ~m0 & ~c & m & ~l & st ~m1 & c & ~m & ~l RI p = CF.m SF.m Sls0 = ~m0 & ~c & (~m & ~st ~lp p) ~m1 & c & ( ~m & ~st ~lp) Sls1 = ~m0 & ~c & ( m st ) & lp & ~p ~m1 & c & lp Sns0 = m0 & ~c & ~lp & (~m & ~st p) ~m1 & c & ~m & ~st & ~lp Sns1 = m0 & ~c & (lp ~p & (m st)) m1 & c fix0 = ~m0 & ~c & lp & ~p & (m st) ~m1 & c & lp fix1 = ~m0 & ~c & ~lp & ~p & (m st) ~m1 & c & ~lp RZ p = 0 Sls0 = ~m0 & ( ~c ~l) Sls1 = ~m1 & c & l Sns0 = m0 & (~c ~l) Sns1 = m1 & c & l fix0 = ~m1 & c & l fix1 = ~m1 & c & ~l Eone m0 m1 m1 = Eone R I [23] & l (R I +2)[23] & ~l m0 = Eone R I [23] n0 = R I [0]

31 n1 = R I [0] & l (R I +2)[0] & ~l NS LS 3.4 MAF MAF Verilog HDL SMIC 0.18µm Synopsys Design Compiler 7.15ns 1.8 (tdetect) A (talign) 3:2 CSA (tcsa) LZD (tcalculate) (tnorm) (tadd) tmaf = tdetect + talign + tcsa + tcalculate + tnorm + tadd MAF CSA MAF MAF LZD CSA MAF 8 NOR

32 MAF MAF 350MHz

33 4.1 SRT FPU 4 SRT IBM eserver z990 P i+1 = r P i q i+1 D (4.1) P q D r q i+1 P i+1 q i+1 q i+1 P i+1 <(q max D)/(r-1) FPU q {-3,-2,-1,0,1,2,3} r 4 P<D P-D IBM z990 PD PD P in <D

34 4.1.2 PD Qpos Qneg Pcarry, Psave 5 Psave i+1 + Pcarry i+1 = 4 (Psave i + Pcarry i ) q i+1 D (4.2)

35 q i >0 Qpos i = q i q i <0 Qneg i = q i Q = Qpos+Qneg = qi 4 -i (4.3) / PD / 5 Qpos Qneg PD 1 0 [1,2) (0.5,2) 1 ExpA, ExpB leada, leadb ExpR = ExpA ExpB + Ebias leada +leadb 1 1 (0.5,2) ExpR

36 :P<D (D 1.00 Pin<0.010) (0.5,1) Qpos Qneg ExpR< ExpR<1 23+ExpR 23+ExpR (27+ExpR)/2 (29+ExpR)/2 23+ExpR (26+ExpR)/2 (28+ExpR)/2 4.3 [11]

37 Qpos 13 Qneg / Qpos Qneg 1 1 Qpos + ~Qneg = Qpos Qneg

38 5.1 IBM z990 FPU 2 SRT 1 4 SRT {-2,-1,0,1,2}, X s X X [1,2) s = X 1/2 ε s [1, 2) s m ε <4 -m j S[j] S[0] = 1 j i i i { } (5.1) S[ j] = s 4, s 2, 1,0,1,2 i= 0 s = S[m] ε w[j] = 4 j ( x S[j] 2 ) w[j+1] = 4w[j] 2S[j]s j+1 s 2 j+1 4 -(j+1) (5.2) 4 4 j 4 4 S[ j] + 4 w[ j] S[ j] j (5.3) PD [12] Ŝ[j] j S[j] 4 A 1.A 2 A 3 A 4 A 1 =1 A 1 S 1 (1,1, 0, ), j = 0 ( S1, S2, S3, S4) = (1,1,1,1), A1 = 0 & j 0 (1, A2, A3, A4), j 0 (5.4)

39 m k (i) w[j]<m k+1 (i) s j+1 =k i Ŝ[j] 0 8/16 1 9/ / / / / / /16 m 2 (i) 3/2 7/ /4 5/2 5/2 11/4 m 1 (i) 1/2 1/2 1/2 1/2 3/4 3/4 1 1 m 0 (i) -1/2-5/8-3/4-3/4-3/ m -1 (i) -13/8-7/ /8-9/4-5/2-11/4-23/8 [11] 5.2 w[j+1] = 4w[j] 2S[j]s j+1 s j (j+1) 1) 4w[j] 2) 4w[j] S[j] s j+1 3) w[j+1]

40 X S[m] w[j] w[j+1] = 4w[j] + F[j] F[j] = 2S[j]s j+1 s j (j+1) S[j] s j [11] S[j] A[j] = S[j] B[j] = S[j] 4 -j ( j+ 1) Aj [ ] + sj+ 14, sj+ 1 0 Aj [ + 1] = ( j+ 1) B[ j] + ( 4 Sj+ 1 ) 4, sj+ 1 < 0 (5.5) ( j+ 1) Aj [ ] + ( sj+ 1 1)4, sj+1 > 0 B[ j+ 1] = ( j+ 1) B[ j] + ( 3 sj+ 1 ) 4, sj+ 1 0 (5.6)

41 s [1, 2) A[0] = B[0] = w[j+1] F[j]= 2S[j]s j+1 s j+1 4 -(j+1) ( j+ 1) ( ) 2 Aj [ ] + sj+ 14 sj+ 1, sj+ 1 > 0 F[ j] = 0, sj+ 1 = 0 (2 B[ j] + 8 s 4 ) s, s < 0 ( j+ 1) ( ) j+ 1 j+ 1 j+ 1 (5.7) w[j] s[j+1] A[j] B[j] F[j] s [1, 2)

42 5.3 MAF S[m] 1 1 [13] A[j] B[j] S[j] C[j] A[j] = S[j] B[j] = S[j] 4 -j C[j] = S[j] + 4 -j C[j] A[j] B[j] s j+1 A[j+1] B[j+1] C[j+1] 0 (A[j],0) (B[j],3) (A[j],1) 1 (A[j],1) (A[j],0) (A[j],2) -1 (B[j],3) (B[j],2) (A[j],0) 2 (A[j],2) (A[j],1) (A[j],3) -2 (B[j],2) (B[j],1) (B[j],3) A[m] B[m] C[m]

43 2003 International Technology Roadmap for Semi-conductor, ITRS2003 2:1 3: Intel

44 IEEE 754 constrains biasing X X

45 IEEE 754 C CPU CPU CPU verilog verilog

46 1 Synopsys VCS Coverage Metrics license (line/statement coverage) (toggle coverage) (path coverage) (condition coverage) if?: 100% 100% case 6.2 (symbolic simulation) (model checking) (Theorem Proving) Intel STE IBM SixSense AMD ACL2 MAF [14]

47 Synopsys Formality MAF MAF

48 Verilog HDL Synopsys VCS Synopsys Design Complier Synopsys Astro SMIC 0.18µm Synopsys Design Compiler 3.07ns V 91.2mW mw mw 1.64 uw DC

4mm 4mm PAD 1mm 1mm 47% 6.68ns MAF PAD FPU 2004 [15] 12 32 32 (RF) 6.2.2 6.2.1 [15] SMIC 0.18 CMOS TSMC 0.

49 4mm 4mm PAD 1mm 1mm 47% 6.68ns MAF PAD FPU 2004 [15] (RF) [15] SMIC 0.18 CMOS TSMC 0.18 CMOS 1.8V Core 2.5V PAD 1.8V Core 2.5V PAD 1.00mm 1.00mm 1.06mm 1.06mm MHz 266MHz [15]

50 [15] IBM z99 MAF Intel P4 AMD Athon K7 IBM z FPU

51 8.1 IEEE SRT FPU 1mm 2 150MHz 64 MAF SRT VCS DC Astro CAD Solaris UNIX

52 1 AMD ACL2 AMD Athlon K5 20 [16] 2 CPU DSP CPU DSP CPU DSP CPU DSP 2005 ISSCC IBM SONY SCE Toshiba 90nm SOI Cell 2500 Cell IBM 64 Power 8 FPU FPU

53 [1] G. Gerwig, H. Wetter, E. M. Schwarz, J. Haess, etc, all. The IBM eserver z990 floating-point unit, In: IBM Journal of Research and Development, v 48, n 3-4, May/July, 2004, p [2] G. Gerwig, H. Wetter, E. M. Schwarz, and J. Haess, High Performance Floating-Point Unit with 116 Bit Wide Divider, In: Proceedings of the 16th Symposium on Computer Arithmetic, Santiago de Compostela, Spain, June 2003, pp [3] L. Tomas and B. Javier D, Floating-point multiply-add fused with reduced latency, In: IEEE Transactions on Computers, v 53, n 8, August, 2004, p [4] ANSI/IEEE Standard : IEEE standard for Binary Floating-Point Arithmetic. Poscataway, NJ: IIEEE Press, [5] B. Neil, the "Flagged prefix adder" for dual additions, In: Proceedings of SPIE - The International Society for Optical Engineering, v 3461, 1998, p [6] Chichyang Chen, Liang-An Chen and Jih-Ren Cheng, Architectural Design of a Fast Floating-point Multiplication-Add Fused Unit Using Signed-Digit Addition, In: IEE Proceedings: Computers and Digital Techniques, v 149, n 4, July, 2002, p [7] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits, a Design Perspective, Second Edition,,, 2004, p [8] Schmookler, M.S.; Nowka, K.J., Leading zero anticipation and detection - A comparison of methods, In: Proceedings - Symposium on Computer Arithmetic, 2001, p [9] Bruguera, Javier D. and Lang, Tomas, Leading-one prediction with concurrent position correction, In: IEEE Transactions on Computers, v 48, n 10, Oct, 1999, p [10] Q, Nhon T., T. Naofumi, F. Michael J., Systematic IEEE Rounding Method for High-Speed Floating-Point Multipliers, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v 12, n 5, May, 2004, p

54 [11] Neil Burgess, Prenormalization Rounding in IEEE Floating-Point Operations Using a Flagged Prefix Adder, In: IEEE Transcations on VLSI Systems, Vol. 13. NO 2. Feb, p [12] M. D. Ercegovac and L. Tomas, Radix-4 square root without initial PLA, In: IEEE transactions on Computers. Vol. 39, NO. 8, Aug p [13] E., Milos D. and L. Tomas, On-the-fly rounding for division and square root, In: Proceedings - Symposium on Computer Arithmetic, 1989, p [14] Jacobi, C. ; Weber, K.; Paruthi, V.; Baumgartner, J. Automatic formal verification of fused-multiply-add FPUs, In: Proceedings. Design, Automation and Test in Europe, 2005, pt. 2, p Vol. 2 [15] K., Taek-Jun; M., Joong-Seok; S., Jeff and D., Jeff, A 0.18µm implementation of a floating-point unit for a processing-in-memory system, In: Proceedings - IEEE International Symposium on Circuits and Systems, v 2, 2004 [16] Russinoff, D.M., A case study in formal verification of register-transfer logic with ACL2: the floating point adder of the AMD Athlon/sup TM/ processor, In: Formal Methods in Computer-Aided Design. Third International Conference, FMCAD Proceedings (Lecture Notes in Computer Science Vol.1954), 2000, p

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56 IBM eserver z990 G. Gerwig H. Wetter E. M. Schwarz J. Haess C. A. Krygowski B. M. Fleischer M. Kroener IBM eserver z990 FPU IBM SRT IBM zseries IEEE754 FPU 4 SRT 2 IBM z990 eserver*[1] (FPU) IEEE754 [2] BFP) IBM z/architecture*[3] (HFP) IBM PowerPC * z * HFP BFP z990 FPU 1996 G3 FPU[4] 1997 G4 FPU[5,6] 1998 G5 FPU[7,8] 1990 G6 FPU 2000 z900 FPU[9] z990 FPU BFP z Linux** JAVA** C++ BFP G5 G6 z900 FPU BFP HFP BFP

57 BFP HFP BFP IBM p POWER4* [10] z POWER4 SRT [11,12] z990 1 SRT SRT SRT BFP HFP 1998 IBM z G5 HFP BFP HFP BFP HFP BFP [13] HFP 2 n-1 BFP

58 (2 n-1-1) BFP HFP XBPFi=(-1) Xs (1+Xf) 2 Xe-biasBi bias Bii =2 n-1-1=32767 X HFPi =(-1) Xs Xf 2 Xe-biasHi, bias Hii =2 n-1 =32768 [10] 3 (FPU FPU E1 E2 E3 E4 E5 E (E-1)

59 E0 (FPR) E0 E1 E2 E3 0 E4 E5 E6 E0 A B C (LWRs) 16 FPR 4 5 LWR E0-54 -

60 4 FPU RX RR RX RR [13]IBM PowerPC RX PowerPC RR z HFP

61 BFP 1 Y X P X Wj lzcl[14,15] 0 n 1 X x x = + i i= 1 i 2 i 0 n 1 Y = y + y i2 j= 1 j j Y n = W i 4 j= 1 j j j { 2, 1, 0, 1, 2} W + + n P= W ixi 4 j= 1 j j 1 n 1 = + i X x x i= 1 i 2 i X = X x 0 n j P = Wj ix i4 Yi x j=

62 lzcl = Yi x 0 D D+1 D-1 [10] HFP BFP BFP cccc...cGGG xx.pppp...pggggggggg ^ ^

63 G c p E c 1 60 E p 2 LZC E n =E p -LZC En<Emin BFP En<Emin LZCmin=Ep-Emin En Emin [10] IEEE754 LSB BFP

64 SRT 1 FPU SRT SRT P i+1 =r P i -q i+1 D P q D r

65 P i+1 =r P i =q i+1 2Q i -q 2 i+1r -(i+1) P q Q r 6 q i+1 P i+1 q i+1 q i+1 P i+1 <(q max D)/(r-1) P-D q i

66 4 [16,17] P i+1 =P Ci+1 +P Ci+1 P Si+1 +P Ci+1 =4(P Si +P Ci )-q i+1 D q i+1 {-3,-2,-1,0,0,+1,+2,+3} q i+1 =q i+1,1 + q i+1,2 P Si+1 +P Ci+1 =4(P Si +P Ci )-q i+1,1 1D-q i+1,2 2D P S P C -q i+1,1 q i+1, (r=2) P i+1 =P Si+1 +P Ci+1 Q i =Q Pi +Q Ni, P Si+1 +P Ci+1 =2(P Si +P Ci )-q i+1 2Q Pi +q i+1 2Q Ni -q 2 i+1 r -(i+2) q i+1 {-1,0,0,+1} q 2 i+1 r -(i+2)

67 7 BFP 113 PD +/

68 q i+1,1 q i+1,2 HFP :2 3:2 (CSAs) CPAs CPA CPA CPA 116 Q pos Q neg q i+1 Q pos Q neg q i+1 FPU BFP FPU IEEE

69 3 IEEE q i+1 n V n D n Q n Q0 =n V -n D V norm <D norm n I =n V -n D+1 V norm D norm n Qe P Start P Stop P Start =64-n Qe

70 P Stop =64 4 FPU FPU 6% IBM 0.13 m CMOS SOI 1.15V GHz A B C FPR A B C CMOS FPU

71 8 IBM eserver z

72 80 z990 FPU Juergen Foag Andree Marth Hans-Juergen Muenster Lukas Daellenbach, Dave Rude, Peter Cook, Steve Klepner, Fanchieh Yee, Harald Mielich, Rainer Clemen Juergen Vielfort Klaus Keuerleber * (IBM) ** Linus Torvalds Sun Microsystems, Inc

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NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94

NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz 23 90 CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94/188GHz LC class-b 0.70 0.75 mm 2 pad 1 V 19.6 ma (ƒ