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1 2014 华南先进封装技术研讨会 2014/08

2 华进半导体简介华进半导体封装先导技术研发中心有限公司于 2012 年 9 月在无锡新区正式注册成立公司英文全称为 :National Center for Advanced Packaging Co., Ltd. (NCAP China) 公司是由中科院微电子所和集成电路封测产业龙头企业长电科技通富微电华天科技深南电路苏州晶方安捷利 ( 苏州 ) 中科物联兴森快捷九家单位共同投资而建立公司目标 : 建设在国际半导体封测领域中具有影响力的国家级封装与系统集成先导技术研发中心, 在部分领域能够引领国际产业技术发展面向我国集成电路产业结构调整和创新发展需求, 建设世界一流水平的国际化产业技术研发中心, 在全球创新链中占有自己的位置, 从而推动我国集成电路产业做大做强公司作为国家级封测 / 系统集成先导技术研发中心, 通过以企业为主体的产学研用结合新模式, 开展系统级封装 / 集成先导技术研究, 研究领域包括 2.5D/3D 硅通孔 (TSV) 互连及集成关键技术晶圆级高密度封装技术 SiP 产品应用以及与封装技术相关的材料和设备的验证改进与研发, 为产业界提供系统解决方案公司团队由具有国际知名企业和研发机构长期技术与管理经验入选中科院百人计划国家千人计划的领军人才和具有丰富研发经验的本土团队相结合, 研发人员百余人, 其中一半以上具有博士学位和硕士学位公司的研发平台包括 : 先进封装设计仿真平台 3200 平米的净化间及 300mm 晶圆整套先进封装研发平台 ( 包括 2.5D/3D IC 后端制程和微组装 ) 封装基板线测试实验室及可靠性与失效分析平台服务宗旨 : 以市场需求为导向, 以有偿服务为原则, 以技术成果出让创收益, 为产业服务, 为提升中国集成电路封装产业整体技术水平服务

3 个人简介林挺宇现在华进半导体封装先导技术研发中心总监新加坡微电子所 TSV 项目总监年分别工作在新加坡飞利浦消费电子, 朗讯科技 (AT&T bell Lab) 及摩托罗拉移动产品全球供应链中心从事和电子封装设计, 新产品导入及大规模生产, 工艺开发和可靠性相关的工作, 六西格玛质量黑带国际 CSRboard member 及高级顾问从事 100 多种消费电子产品的设计和开发, 在国际刊物和会议上发表 150 余篇论文,10 项国际专利, 多次获优秀论文奖

4 2.5D/3D 集成及封装中的优化解决方案 OPTIMUM PACKAGING SOLUTIONS FOR 2.5D/3D IC MANUFACTURING Moore s Law will continue for the next decade, but may face challenge below the 28nm node due to three critical limitations which included materials, device physics and lithography. This uncertainty around the extendibility of Moore s Law provided huge opportunity and challenge for 2.5D/3D silicon & package integration. 2.5D/3D package integration is generally facing challenges from three aspects: 1. Pressure on 2.5D/3D integration cost, yield and cycle time 2. TSV process integration, wafer thinning & die stacking D IC is using Si interposer which is expensive, alternative solutions are needed for explorations Over last 6-7years, global efforts are intensively pursued for above challenges, and not yet fully optimized and solved. This presentation reviews the latest development in 2.5D/3D packaging, and discusses in detail for the optimum packaging solutions for 2.5D/3D packages and alternatives. Finally some works are introduced for NCAP current development works on TSV process and interposers.

5 OUTLINE -. Moore s Law: Termination of Moore s Law? -. Optimum Selection of Packaging Integration Technology -. Development of 2.5D/3D Packaging Technology -. Low cost alternatives of 2.5D/3D -. Packaging solutions and implementation D/3D Development Updates at NCAP -. Summary

6 Cost ($) Memory Bandwith TERMINATION OF MOORE S LAW? Gordon Moore, co-founder of Intel, observed that the number of Transistors per square inch on integrated circuits had doubled every year since the integrated circuit was invented. Moore predicted that this trend would continue for the foreseeable future. $1 $0.1 $0.01 Price per Transistor source: Lam research, GFS 2014 DDR667 DDR800 DDR1066 $0.001 $ $ DDR333 DDR533 source: Lam research, GFS 2014 $ DDR400 Year DDR226 DRAM Device Speed

7 LIMITATION OF MOORE S LAW Cost drives need for increased functionality Cu 0.05micron 0.1micron Material limitation Device physics limitation Lithography limitation Moore s Law drives faster, smaller, less expensive IC

5%) (US$29B) Packaging Trend 2D SoC (QFN, FBGA, fcbga, ewlb, WLCSP) 3D SIP (PoP, PiP, FBGA, module) 3D IC (TSV, HMC,

8 PACKAGING FACES GROWING OPPORTUNITY &CHALLENGE 3C Market Computer (CAGR:2.8%) (US$136B,2013) Communication (CAGR:4.8%) (US$81B,2013) Consumer (CAGR:37.5%) (US$29B) Packaging Trend 2D SoC (QFN, FBGA, fcbga, ewlb, WLCSP) 3D SIP (PoP, PiP, FBGA, module) 3D IC (TSV, HMC, IPD, ewlp, PoP-TSV) Implication to OSAT Packaging cost, yield & cycle time Wafer thinning, handling &stacking Silicon interface know how &IP 2.5D/2.1D/organic interposer with balanced cost, yield & cycle time

9 ADVANTAGE OF 3D PACKAGING PoP vs TSV Sources: Samsung and Nomura estimates 3D IC has better form factor, performance, and integration

10 3D MARKET FOCUS

11 SELECTIVE PACKAGING SOLUTIONS Application I/O Density (X-Y plane) requirement (L/S pitch, um) I/O Density (Z) (# via/mm 2 ) Integration Technology Solution FPGA (Si partitioning &synthesis) Logic + DRAM integration/si Partitioning Si Partitioning /Discrete function integration 0.5-2um 1X10 3-1X10 4 TSV 2-5um 2X10 2-1X10 3 LC TSV/WL Fan-out 4-10um 1X10 2-6X10 2 WL Fan-out TSV, Fan-out WLP, and laminate packaging technologies are needed to meet I/O densities requirements.

12 2.5D VS FOWLP Packaging Structure Density Form Factor Cost infrastructure Product applications Si TSV based 2.5D/3D FPGA, HPC, GPU/CPUmemory Fan-out/eWLB based 2.5D/3D Mobile, Tablet (AP/memory, AP Partitioning) 12

OPTIMUM PACKAGING SOLUTIONS I/O Count >10000 1000-5000 Si Interposer FCCSP (no

13 OPTIMUM PACKAGING SOLUTIONS I/O Count > Si Interposer FCCSP (no interposer) Fanout Total Silicon Die Area (mm 2 ) >700

TSV ECOSYSTEM WITH FOUNDRY & OSAT PARTNERSHIP Foundries EDA &IP partners TSV Fab TSV MEOL &BEOL Packaging Assembly Test design Test Dev (DtF) Reticle sets Wafer Fab Bump Probe Thin& bonding Assy &

14 TSV ECOSYSTEM WITH FOUNDRY & OSAT PARTNERSHIP Foundries EDA &IP partners TSV Fab TSV MEOL &BEOL Packaging Assembly Test design Test Dev (DtF) Reticle sets Wafer Fab Bump Probe Thin& bonding Assy & test Design Partners OSAT Partners Customer Benefits: 1. open, flexible, cost effective supply chain 2. Aligned with customer s preferred partners 3. Active co-development to ensure smooth volume ramp

15 3D TSV MANUFACTURING MODEL Foundries OSA Product Product photos TSMC Xilinx/Altera/Ibiden/Amkor/TSMC; 2.5D supply chain Altera 2.5D FPGA; TSMC CoWoS UMC GF UMC and Stats ChipPAC (SCP) announced TSV-enabled 3D IC chip stack consisting a wide I/O, 300mm mid-end processing & low volume manufacturing GF, Amkor & open silicon, 2 ARM die with a high density silicon interposer (2014, 22/20nm) The 3D chip stack, a wide I/O memory test chip stacked upon TSV embedded 28nm processor test chip 2.5D ARM core product Demo SMIC 40nm production in 2014, 28nm R&D& qualification (Q3, 2014) SMIC's Center for Vision, Sensors and 3DIC (CVS3D).

16 FIRST COMMERCIAL 3D CHIP MAKING CAPABILITY IBM used 32nm, high k metal gate process technology HMC Advantage: time faster than DDR SDRAM (128GB/s); 2. Required 70% less energy to transfer data; 3. Offering a small form factor just 10% of footprint of conventional memory

17 AVAILABLE TSV IN CIS PRODUCT 17

18 NCAP S VALUE PROPOSITION 江阴长电通富微电中科院微电子所深南电路天水华天晶方 Major share holders 华进 (NCAP) 9 investors Including the largest packaging companies and substrate suppliers in China, and the Institute of Microelectronics, Chinese Academy of Sciences Independent business entity NCAP first registrar in 29 Sept., 2012 It is a National Centre for Advance Packaging; work as driving leaders for National Projects Expected impact in TSV, WLCSP, Flip Chip, 2.5D and 3D IC Integrations; Critical R&D and product commercialization partnership NCAP Confidential & Proprietary

19 NCAP LOCATION Wuxi Headquarters 2000m 2 Cleanroom Class 10/100/1,000/10,000 8 /12 wafer Beijing Center Beijing, PR China Wuxi Headquarters PR China 1000m 2 Cleanroom Class 1,000/10,000 NCAP Confidential & Proprietary

R&D, COMMERCIALIZATION AND SERVICE Innovate R&D, IP Incubate Influence Transfer, Roadmap, incubation, Standards commercialization Impact Eco-system, Supply Chain TSV & Wafer Level Process Line (8 /12

20 R&D, COMMERCIALIZATION AND SERVICE Innovate R&D, IP Incubate Influence Transfer, Roadmap, incubation, Standards commercialization Impact Eco-system, Supply Chain TSV & Wafer Level Process Line (8 /12 ) Advanced Substrate Fabrication Line Focus Areas SIP design & simulation 2.5D/3D IC Integration Design & Simulation Platform NCAP Platform Packaging Assembly Line High density WLP RF & Opto-electronics Test technology Test Platform Reliability/FA Labs Reliability & FA Materials & equipment technology Industrialization 20 NCAP Confidential & Proprietary

21 NCAP TEAM Team 110 people (Wuxi + Beijing); >60% with MS/Ph.D. degrees - Target people in 2014 Most team members have working experience with large international and domestic enterprises and institutes Collaborative Innovation Platform for Virtual IDM & Supply Chain Materials & Equipment System House IC Design Foundry OSAT 21

22 NCAP PROCESS MODULE Platform Process Modules Litho. Etch Thin Film Wet Wafer Preparation Bonding Encapsulation Backend Coating DRIE CVD Wafer Cleaner Wafer Bonding Die Bond Plasma Ball Attach Stepper PVD ECD De-bonding Wire Bond Underfill Marking Developer UBM Sputter CMP Tapping Flip Chip Attach Molding FOL (Front of Line) Process Module Wafer Etcher Grinder/ Polisher Mechanical Saw Reflow Deflux EOL (End of Line) Process Module NCAP Confidential & Proprietary 22

Device & Application Capability NCAP CAPABILITY Design & Simulation 2.5D/3D (TSV) Integration Technology Assembly Technology System Integration Package design (including 2.

5D/3D integration for high performance system 200/300mm wafer BSI CIS, high performance computing, networking Wafer level package 40um pitch Cu pillar bumping assembly 40N Low K chip wire bonding

23 Device & Application Capability NCAP CAPABILITY Design & Simulation 2.5D/3D (TSV) Integration Technology Assembly Technology System Integration Package design (including 2.5D/3D) Substrate design SI, PI, RF, EMI & EMC Thermal/ mechanical codesign 2.5D/3D integration for high performance system 200/300mm wafer BSI CIS, high performance computing, networking Wafer level package 40um pitch Cu pillar bumping assembly 40N Low K chip wire bonding Multi chip stacking Advanced substrate Testing RF package with Si interposer mmw communication High speed optoelectronics device MEMS/Sensor Package design C2C stack L/S=15/15um substrate OE module 4 10 Gbps QSFP AOC Thermal distribution Cu filled TSV TSV with 2 layers RDL Low K Cu wire bonding OE module 2.5D integration Eye diagram NCAP Confidential & Proprietary RF/mmW interconnection 23

24 NCAP SERVICE TSV manufacturing Wafer Thinning pocess, equipment & materials:lit ho, etch, Oxide liner, CuBS, ECD, C MP, Patterning, E test. TBDB Material & process optimization Cu Cu Diffusion Bonding micro Cu Pillar (30-60um; design/ manufacturing/ bonding) underfill (film type) FC+WB technologies evaluation of Cu wire bonding low k TCB, BOT and FC+WB proce ss development & optimization Reliability Test Requirement Samples Test Electrical 22# TC Precon. to JESD22 A113 D MSL 3, 1000 cycles 40 C to +125 C 22# Unbiased HAST - Precon. to JESD22 A113 D MSL 3, 130 C 85%, 96 hours 22# High Temperature storage to JESD22- A103-B Condition A: +125 C, 1000 hours TBD Electromigration Testing at maximum current density and temperature for up to 2000 hours Electrical test before & after Electrical test before & after Measure resistances before, at 100, 200, 500, 750, 1000 hours Continuous monitoring C2W/C2C/W2W Pre-applied underfill, Surface cleaning Low temp/fine pitch/high density bonding Substrate design & PCB Manufacturin g BOL, EPP substrate development - 6-9ppm/C 和 3-4ppm/C); - high density TSV and TSI (design & manufacturing) NCAP Confidential & Proprietary

25 2.5D INTERPOSER UPDATES Compatibility of TSV lithography and Bosch process; 20x200um ~3x100um TSV etching; High aspect ratio TSV clean; High step coverage PECVD process; High step coverage PVD process; TSV overburden and backside reveal solution; Dual sides process solution; 2.5DIC assembly; Interposer cross section TSV backside pickup TSV cross section TSV front side pickup

NCAP EQUIPMENT CONSORTIUM 建立 1-1 合作模式 ( 阶段 1) 推动设备改进达到封装主流要求建立合作联盟 ( 阶段 2) 推动设备国产化及进入国际市场 (1:10, 及性价比 ) Local Equipment & Material Suppliers NCAP Total Solution Platform

26 NCAP EQUIPMENT CONSORTIUM 建立 1-1 合作模式 ( 阶段 1) 推动设备改进达到封装主流要求建立合作联盟 ( 阶段 2) 推动设备国产化及进入国际市场 (1:10, 及性价比 ) Local Equipment & Material Suppliers NCAP Total Solution Platform Customer: Foundry IDM and OSAT 设备及材料评估及验证 ; 与设备厂商合作提出改进措施 ; 在实施改进措施后 ; 进行再评估, 验证通过华进平台向市场宣传在华进进行试运行, 展示及推广推动国产化设备进入国内及国际市场与 Foundry 及 IDM, OSAT 合作共同评估及验证 ( 通过专项 ), 及验收和购买设备

27 SUMMARY 1. Moore s Law still drives economic value of semiconductor, which is performance per cost D/3D packaging integration is an extension of Moore s Law, the opportunity and challenge are co-existing. 3. Innovative and cost effective solutions are dominated in 2.5D/3D FO-WLP/eWLB 4. Design, Foundry and OSAT are working very closely and building cost effective partnership 5. Optimum packaging solutions are focusing on fan-out 2.5D, ewlb SIP and 3D integration

28 Thank YOU

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4 020 Application Trend and Fabrication Introduction of 3D Integrated Circuits Through Silicon Vias Technology Abstract The three-dimensional integrated circuits through silicon vias (3D IC TSV) technology