IP Deliverables (course topics)
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- 丕留 荤
- 5 years ago
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1 FPGA Synthesis & Prototyping 國立雲林科技大學電子系 許明華
2 本單元在 DIP 設計中的角色 Write function spec. Write technical spec. Develop area/timing/power constraints Write RTL Run lint Develop testbench FPGA Synthesize Simulate Measure verification coverage Not enough Digital IP Prototyping
3 IP Prototyping System Digital Data GPIO Instrument Key Board RAM, ROM LED, LCD Analog Sensor A/D FPGA D/A Analog Device Printer Port RS232
4 IP Deliverables 在 DIP 設計中的角色 作為 DIP 之 FPGA 合成與實現 評估 DIP 雛型電路之功能驗証完整度 評估 DIP 雛型電路之效能 (Speed, Cost) 評估 DIP 雛型電路之介面完整度之查核點 評估 DIP 雛型電路在系統中之整合度
5 Course Contents FPGA Device Altera, Xilinx (pp. 5~39) FPGA Design Flow & Synthesis ISE, Quartus II (pp. 40~83) DIP Rapid Prototyping Platform (pp. 84~104) DIP Prototype System Measurement (pp.105~141) Design Example (pp.142~167)
6 FPGA Device FPGA Design Flow & Synthesis DIP Rapid Prototyping Platform DIP Prototype System Measurement Design Example
7 Increasing PLD Complexity PLD Complexity Drives Design Methodology Changes Increasing Time-to-Market Pressures Drive Change Glue Logic Control Logic Equations Schematics Complex Control Synthesis Macrofunctions SOPC Design Block-Based Design Second-Generation Synthesis IP Megafunctions Time
8 Altera Device Families Programmable Logic Families High & Medium Density FPGAs Stratix, APEX II, APEX 20K, & FLEX 10K Low-Cost FPGAs Cyclone & ACEX 1K FPGAs With Clock Data Recovery Mercury & Stratix GX CPLDs MAX 7000 & MAX 3000 Embedded Processor Solutions NiosTM, ExcaliburTM Configuration Devices EPC
9 APEX 20K Family Industry s first MultiCore Architecture Look-up table (LUT) logic Product-term logic Embedded memory Fabricated on SRAM Process 2.5-V, 0.25/0.22-Micron Process 1.8-V, 0.18-Micron Process
10 APEX MultiCore Architecture MultiCore Makes Million-Gate PLD Design Possible Facilitates Efficient IP Integration Look-up Table Core Product-Term Core Memory Core
11 Enhanced FastTrack Interconnect 4-Level FastTrack Interconnect Continuous Routing Fast, Predictable Timing
12 APEX 20K Device Features
13 The Stratix Device Family Process Density Feature Performance Embedded Memory Digital Signal Processing (DSP) Functionality Clock Management I/O Capabilities Description 0.13-µm Technology 10,570 to 114,140 Logic Elements (LEs) Average 40% Increase TriMatrix Memory Incorporating 3 Block Sizes for Maximum Bandwidth & Capacity Embedded DSP Blocks for Complex Arithmetic Functions Advanced System Clock Control for On- & Off-Chip Clock Needs 840-Mbps Differential I/O Signaling, High-Speed Interface Support, External Memory Interfaces & On-Chip Termination Technology
14 Stratix Architecture Overview Logic Array Blocks (LABs) Phase-Locked Loops (PLLs) DSP Blocks MegaRAM Blocks I/O Elements (IOEs) M512 RAM Blocks M4K RAM Blocks
15 Advanced I/O Capabilities Differential & Single- Ended I/O Standards LVDS, LVPECL, HyperTransport, PCML HSTL, SSTL PCI, PCI-X, Compact PCI PCI High-Speed Interface Protocols 10-Gigabit Ethernet XSBI POS-PHY Level 4 HyperTransport RapidIO (Parallel) External Memory Device Interfaces DDR SDRAM & SRAM SDR SDRAM QDR & QDRII SRAM ZBT SRAM DDR FCRAM Terminator Technology On-Chip Differential Termination On-Chip Series & Parallel Termination Driver Impedance Matching
16 TriMatrix Memory Structure
17 DirectDrive Technology Each Interconnect Line Driven by Single Source Consistent Access to Routing Eliminates Congestion Uniform Routing Resources Across Device Ensures Blocks Can be Moved within or between Designs
18 DSP Block
19 DSP Block Modes
20 The Stratix Device Family Device Logic Elements 32x18 M512 Blocks 128x36 M4K Blocks 4,096x144 MegaRAM Blocks Total RAM Bits DSP Blocks Sample Availability EP1S10 10, ,448 6 July EP1S20 18, ,669, Q3 EP1S25 25, ,944, June EP1S30 32, ,317, Q4 EP1S40 41, ,423, Q3 EP1S60 57, ,215, Q4 EP1S80 79, ,427, July EP1S ,140 1, ,118,
21 Package Offerings & User I/O Device 672-Pin BGA Wire-Bond 1.27 mm 35 x 35 mm 956-Pin BGA Flip-Chip 1.27 mm 40 x 40 mm 672-Pin FBGA Wire-Bond 1.0 mm 27 x 27 mm 780-Pin FBGA Flip-Chip 1.0 mm 29 x 29 mm 1020-Pin FBGA Flip-Chip 1.0 mm 33 x 33 mm 1508-Pin FBGA Flip-Chip 1.0 mm 40 x 40 mm 1923-Pin FBGA Flip-Chip 1.0 mm 45 x 45 mm EP1S EP1S EP1S EP1S EP1S EP1S ,018 EP1S ,199 1,234 EP1S120 1,310 Vertical Migration Supported
22 Nios Flexibility & Scalability Network Processor System High-Performance Low-Cost Custom DSP Embedded Processor DSP Excalibur ARM922T + Memory ESB ESB ESB ESB ESB ESB ESB ESB 75K Gates Available 150K Gates Available ESB ESB ESB ESB ACEX EP1K100 APEX EP20K200E 500K Gates Available Excalibur EPXA10
23 Nios System Architecture Nios CPU On-Chip Debug Core Off-Chip Software Trace Memory Instr. Data Address Decoder Interrupt Controller Wait State Generation Data in Multiplexer Master Arbitration Avalon Master/ Slave Port Interfaces UART 0 Timer 0 SPI 0 GPIO 0 DMA 0 Memory Interface UART n Timer n SPI n GPIO n DMA n Dynamic Bus Sizing Avalon Bus Module User-Defined Interface
24 ARM-Based Excalibur Embedded Processor 200-MHz ARM922T Processor Up to 3.3 Mbits of Memory Up to 1M Gates of Programmable Logic Dual-Port RAM Single-Port RAM PLD Area for Customer Design ARM922T Core
25 Embedded Processor PLD Architecture JTAG PLL Timer UART Watchdog Timer External Memory Interfaces Processor & Interfaces I-CACHE D-CACHE Interrupt Controller ARM 8 Kbytes 8 Kbytes Trace Module ARM922T SRAM SRAM SRAM DPRAM DPRAM DPRAM Embedded Stripe EPXA1 LEs 4,160 ESB (Bytes) 6.5K 32 Kbytes SRAM 16 Kbytes DPRAM PLD LEs 16,400 ESB (Bytes) 26K EPXA4 128 Kbytes SRAM 64 Kbytes DPRAM LEs 38,400 ESB (Bytes) 40K EPXA Kbytes SRAM 128 Kbytes DPRAM
26 Introduction to Xilinx Product FPGA : Spartan/XL, Spartan II,Spartan-IIE, Virtex, VirtexE,Virtex II,Virtex-II Pro CPLD : XC9500/XL, CoolRunner Software :Foundation4.2i, ISE Alliance4.2i, ISE 4.2 Core : IP, LogiCore, Alliance Core Technical Support : support.xilinx.com, FAEs
27 Xilinx has a solution for every design Density (gates) ASICs 200K 10M High end FPGAs <200K Spartan Mid <5K CPLD Low Serves Density, Performance, Cores & Memory PAL Designs
28 Spartan-II Architecture Delay Lock Loop (DLL) Configurable Logic Block (CLB) Clock management Multiply clock Divide clock De-skew clock Block Memory True Dual-Port TM 4K bit RAM 4Kx1 2Kx2 1Kx4 512x8 256x16 CL DLL I O B I O B CL DLL R A M... R A M IOB CLB CLB IOB IOB I/O Routing Ring CLB... CLB I/O Routing Ring IOB R A M R A M DLL DLL CL I O B I O B CL Logic and Distributed RAM SelectI/O TM Technology Chip to Backplane PCI 33MHz 3.3V PCI 33MHz 5.0V PCI 66MHz 3.3V GTL, GTL+, AGP Chip to Memory HSTL-I, HSTL-III HSTL-IV SSTL3-I, SSTL3-II SSTL2-I, SSTL2-II CTT Chip to Chip LVTTL, LVCMOS
29 Simplified CLB Structure
30 3 Level Memory Hierarchy
31 Virtex-II Pro Platform FPGA Gbps Multi-Gigabit Transceivers (MGTs) Supports 10 Gbps standards Up to 24 per device PowerPC 405 Core 300+ MHz / 450+ DMIPS Performance Up to 4 per device MGT MGT MGT MGT Fabric IP-Immersion Fabric ActiveInterconnect 18Kb Dual-Port RAM Xtreme Multipliers 16 Global Clock Domains
32 PowerPC 405 Processor Local Bus (PLB) I-Side On-Chip Memory (OCM) I-Cache (16KB) D-Cache (16KB) MMU (64 Entry TLB) Fetch & Decode Execution Unit (32x32 GPR, ALU, MAC) Timers and Debug Logic JTAG Instruction Trace 5-stage data path pipeline 16KB D and I Caches Embedded Memory Management Unit Execution Unit Multiply / divide unit 32 x 32-bit GPR Dedicated on-chip memory interfaces Timers: PIT, FIT, Watchdog Debug and trace support Performance: 450 DMIPS at 300 MHz 0.9mW/MHz Typical Power D-Side On-Chip Memory (OCM)
33 Virtex -II Family 12 Devices, 10 Packages, 37 combinations Virtex-II XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V Part Number LUTs + FFs 512 1,024 3,072 6,144 10,240 15,360 21,504 28,672 46,080 67,584 93, ,880 BRAM (Kb) ,008 1,728 2,160 2,592 1,024 3,456 Multipliers DCM Units CS FG FG FG FF FF FF ,104 1,108 1,108 BG BG BF
34 XC9500XL Overview Superset of XC9500 CPLD Optimized for 3.3V systems compatible levels with 5.0/2.5V High f MAX = 200 MHz Fast t PD = 4 nsec Best ISP/JTAG support Best pin-locking Advanced packaging
35 Technology Optimized for high speed 3.3V systems Leading-edge FLASH technology 0.35um feature-size (0.25um Leff) 4 layers of metal Superior reliability Reprogramming endurance = 10,000 Charge retention = 20 years Fast programming characteristics
36 High Level Architecture
37 XC9500XL Family 9536XL 9572XL 95144XL 95288XL Macrocells Usable Gates t PD (ns) f MAX (MHz) Packages 44PC 44PC QFP 64VQ 64VQ 100TQ 100TQ 144TQ 144TQ 208PQ CSP/BGA 48CS 48CS 144CS 352BG
38 Higher Density Enables New Applications Spartan-IIE 250K System Gates 30K FIFOs PALs HDLC UARTs 32-bit, 33-MHz PCI Spartan-XL 40K PCI- MIPS Bridge 64 Bit PCI Spartan-II 100K ATM Reed IMA Solomon Encoder Ethernet MAC Video Line Buffer 250k unit Cable Modem Graphics Card Office Networking Set-Top Box Embedded µpapps
39 Spartan-II Family Overview Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Logic Cells Block RAM Bits 16,384 24,576 32,768 40,960 49,152 57,344 Block RAM Qty Max. User I/Os Package VQ100 VQ100 CS144 CS144 TQ144 TQ144 TQ144 TQ144 PQ208 PQ208 PQ208 PQ208 PQ208 FG256 FG256 FG256 FG256 FG456 FG456 FG456
40 FPGA Device FPGA Design Flow & Synthesis DIP Rapid Prototyping Platform DIP Prototype System Measurement Design Example
41 FPGA Design Flow and Synthesis Specification System-Level Sim SystemC Model C/C++ Matlab / Simulink Device Selection Xilinx Altera Design Entry CoreGen LogiBox IP Verilog/VHDL Schematic FSM Verilog/VHDL/AHDL Schematic Waveform LPM MegaCore Design Entry Function Sim Simulation Model & TestBench Cadence Verilog-XL Synopsys VCSi Debussy ModelSim Synthesis Synthesis Constraints FPGA Compiler II FPGA Express Synplify LeonardoSpectrum FPGA Express FAE Synplify Synthesis Constraints Synthesis
42 FPGA Design Flow and Synthesis P&R P&R Constraints, Floorplaning Placement & Routing Back Annotate Routing Delay Fitting Back Annotate Routing Delay Fitting Constraints Fitting Timing Sim Timing Model & TestBench Cadence Verilog-XL Debussy Synopsys VCSi ModelSim Prototyping Third Party Prototyping Prototyping Development Programming & Debug Hardware Debugger Programmer Programming & Debug JTAG Programmer ChipScope ILA SignalTap
43 Xilinx ISE
44 ISE Design Flows
45 Project Navigator
46 Creating New Projects
47 Adding Source Files
48 Creating HDL Source
49 HDL Wizard
50 HDL Wizard Confirm information
51 Setting Implementation Option
52 Setting Synthesis Options
53 Accessing Advanced Options
54 Initiating a Design Flow
55 Accessing Reports
56 Static Timing Report
57 Proactive Timing Closure
58 Xilinx Synthesis Technology
59 HDL Bencher
60 HDL In, Test Bench Out
61 Simulating with Testbench Waveforms
62 Simulating with Testbench Waveforms
63 ModelSim HDL Simulator
64 Using I/O Buffers
65 Configuration Download
66 Altera Quartus II
67 Design Methodologies Quartus supports three common design methodologies: Top-down Create a top-level of the design first, and then break down the design into lower-level design blocks. Bottom-up Begin by creating the lower-level design blocks first and then stitch together the design at the top-level. Middle-out Start in-between Top-down and Bottom-up design methodologies
68 PLD Design Flow(1)
69 PLD Design Flow(2)
70 Design Entry Multiple design entry methods Quartus Block/Schematic Editor Text Editor AHDL, VHDL, Verilog Memory Editor Hex, Mif Third party EDA tools EDIF HDL VQM Add flexibility and optimization to the design entry process by: Mixing and matching design files Using LPM and Megafunctions to accelerate design entry
71 Design Entry Files Quartus Block Editor Quartus Text Editor Quartus Memory Editor Verilog VHDL AHDL Schematic MegaWizard Manager Top- Level File Top-level design files can be.bdf,.tdf,.vhd,.vhdl,.v,.vlg,.edif or.edf Exemplar, Synopsys, Synplicity, etc... Schematic.bdf.gdf.bsf.tdf.vhd.v.edf.edif.v,.vlg,.vhd,.vhdl, vqm Block File Symbol File Text File Text File Text File Text File Text File Generated within Quartus Imported from third-party EDA tools
72 Main Toolbar and Modes
73 New Project Wizard What is the working directory for this project What is the name of this project What is the name of the top-level design entitiy in your project
74 New Project Wizard
75 Set Chips & Devices Device Select
76 Set User Libraries
77 Compiler Click this button to execute compiler Show the section of compiler summary When compilation was successful will appear this message Compiler Message
78 Timing Analysis Features Quartus II has built in static timing analysis Single clock timing analysis fmax (maximum clock frequency) Tsu, Th, Tco (setup time, hold time, clock-to-out time) Optional system fmax reporting Multi-clock analysis Allows analysis of multiple synchronous clocks Slack analysis is used
79 Timing Analysis
80 fmax The worst fmax is listed on the top. Select fmax
81 Locate Delay Path in Floorplan
82 Download Click this button to open programmer Make sure Type is ByteBlasterMV Make sure is JTAG Select.sof file to programmer
83 Download When it show 100% meaning download finished Enable this field
84 FPGA Device FPGA Design Flow & Synthesis DIP Rapid Prototyping Platform DIP Prototype System Measurement Design Example
85 IP Rapid Prototype Platform Altera Demo Board Xilinx Demo Board FPGA+µp Demo Board Application Specific Demo Board ARM SoC Development Platform
86 Nios Board (Altera) PIO_buttons Flash Configuration Controller SRAM seven_segment JTAG Header uart
87 EPXA10 Development Board (Altera) POWER BOOT_FLASH JP40 RS 232 Flash Mem UART JTAG Ethernet PCI Connector
88 EPXA10 Development Board Features Platform for Device Evaluation & Application Development Memory Support 1. SDR SDRAM: 256 Mbytes 2. Flash: 16 Mbytes Flexible Clocking 50-MHz Embedded Stripe Clock External Clock Generator Can Be Used Dedicated Stripe PLLs for Frequency Synthesis PLD Clocks Dedicated Crystals for Each of Four PLD PLLs Application Support Two UARTs ByteBlasterMV JTAG Connector Multi-ICE & Trace Port Connectors Ethernet PHY
89 EPXA10 Development Board Features PCI Two 3.3-V 33-MHz PCI Connectors Provided for Off-the-Shelf Applications User Interface 1. Eight LEDs 2. Four Push-Buttons 3. Nine-Position DIP Switch Power Supply 3.3-Volt DC Supply 1.8-V Generated 1.25-V Generated for V REF & V TT ATX Power Supply Required for PCI Same Voltage Regulation as 3.3-V DC Supply
90 Altera IP Development Kits APEX DSP Development Kit APLEX 20KE PCI Development Kit SOPC Development Board DIGILAB 10K*240 Development Board PROC20K Prototyping Board Bluetooth Prototype Board Constellation 20K Prototype Board PCISYS Data Acquistition and Processing PCI Board Megalogic 2A15 Development Board XT1000 Device Emulation Kit
91 MicroBlaze Kits with Boards (Xilinx)
92 MicroBlaze IP Peripherals Development Kit MicroBlaze CPU OPB Arbiter Watchdog Timer/Timebase Timer/Counter Block Interrupt Controller SRAM Controller Flash Memory Controller ZBT Memory Controller BRAM UART Lite GPIO SPI Master and Slave Additional Peripherals UART UART IIC Master & Slave Ethernet 10/100 MAC Future Peripherals ATM Utopia Level 2 SDRAM DDR
93 The FPGA + µp Demo Board DRAM Module µp 8051 or AVR A/D, D/A Module SRAM Module
94 The Hardware Module of FPGA+µp Demo Board 8051 or AVR
95 Application Specific Demo Board (Natl. Yunlin Univ.) ADC IC Image Sensor Input Power LED FPGA I/O Pin DIP Sw. UART JTAG FPGA I/O Pin E 2 PROM FPGA I/O Pin
96 ARM SoC Development Platform ARM Integrator ARM 720T Core module AP ASIC Development Platform Xilinx XCV2000E Logic module
97 ARM Integrator/AP System controller (FPGA) Clock generator Flash Memory(32MB) Boot Rom SRAM(512k) System expansion(cm,lm) PCI Interface, EBI Interface FPGA
98 System Architecture Peripheral input/output Core Module connectors Logic Module connectors HDR EXP System bus GPIO System controller FPGA PCI Host Bridge Standard PCI Slots PCI PCI bridge Flash SRAM Boot ROM EBI CompactPCI
99 System controller FPGA System Extrnal PCI bridge bus System bus (AHB) PCI bridge PCI Host Bridge System bus Local bus controller Interface Interface Arbiter Static memory controller External Bus Interface Flash,SSRAM and ROM I AHB/APB bridge Peripheral bus (APB) Counter/ timers Real time clock GPIO UART *2 KMI LED/ switch Interrupt controller status and Control register Peripheral input/output Interrupts System resources
100 Core Module(CM720T) 256KB to 1MB Synchronous SRAM SDRAM DIMM socket (up to 256MB) AMBA system bus interface to platform board Clock generators Reset controller JTAG interface to Multi-ICE ARM FPGA SDRAM (DIMM)
101 CM System Architecture SSRAM Clock generator Status / Control register Reset controller Memory bus SSRAM Controller (PLD) ARM core System bus bridge SDRAM controller FPGA SDRAM System bus Multi-ICE System bus connectors HDRA/HDRB
102 Logic Module(LM-XCV600E+) 1MB ZBT SRAM 9 General-purpose LEDs 8 General-purpose switches Clock generators Push button FPGA programming via Multi-ICE (JTAG) Flash-1 Flash-0 XCV2000E
103 LM System Architecture ZBT SSRAM OSC1 OSC2 Multi-ICE Trace Module/motherboard connectors FPGA Interface module connector LA connector Push button Switches LEDs Prototyping grid
104 System Architecture Core Module SSRAM Status/ Control register SDRAM ASB/PCI Bridge PCI Slot PCI Slot PCI Slot PCI/CPCI Bridge SSRAM Cntl ARM720T Sys Bus Bridge SDRAM Cntl AHB Arbiter AHB Bus Static memory cntl AHB/APB Bridge ROM Flash(32MB) SSRAM(512k) RTC UART AP Module Status/ control register Logic Module FLASH SSRAM FPGA APB Bus Counter/ Timers Keypad controller Interrupt Controller
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