chapt01.ppt

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2 PC Laptop Mainframe Server (PDA) MP3 MP3 :

3 : :,

4 225 ; % ; Intel Pentium, Motorola PowerPC, etc. 6%

5 ,,, (RTOS)

6 Minimally Requirement for an Embedded System NMI Address Bus Microprocessor Data Bus Status Bus Other Peripheral Devices Clock Generation and Distribution Glue Logic and Address Decode To Outside World Random Access Memory - RAM I/O Interface ( D/A, A/D, Digital ) Read Only Memory - ROM ( FLASH ) Communications Watchdog Timer Real Time Clock To outside world To other devices To host Computer To User To Outside World Peripheral Bus DEBUG Port Microprocessor 4, 8, 16, 32, 4 bit bus CISC, RISC, DSP Integrated peripherals Debug/Test Port Caches Pipeline Multiprocessing Systems Software Application Code Driver Code / BIOS Real Time Operating System User Interface Communications Protocol Stacks C, C++, Assembly Language Legacy Code Non-volatile memory EPROM, FLASH, DISK Hybrid Volatile Memory DRAM, SRAM Hybrid System Clocks RTC circuitry System clocks Integrated in uc Imported/Exported Custom Devices ASIC FPGA PAL Standard Devices I/O Ports Peripheral Controllers Communication Devices Ethernet RS-232 SCSI Centronics Proprietary Microprocessor Bus Custom PCI VME PC-102

7 (SOC) (1), Example: Pentium, AMD K6 etc. Microprocessor Real-time Clock Program Memory Data Storage I/O I/O I/O To outside world Source: Arnold S. Berger

(2) Program Data Memory Storage : Serial ports ( COM ), Parallel Ports, Ethernet I/O ports, A/D & D/A Microprocessor Core Interval timers, I/O watchdog timers, event counter/timers, real time clock (

8 (2) Program Data Memory Storage : Serial ports ( COM ), Parallel Ports, Ethernet I/O ports, A/D & D/A Microprocessor Core Interval timers, I/O watchdog timers, event counter/timers, real time clock ( RTC ) I/O Real-time Other local processors Clock ( DSP, numeric coprocessor, peripheral controller ) To outside world Example: Motorola coldfire (3) System-on on-chip (SOC) : : Intel StrongARM Source: Intel

9 Intel Gordon Moore Source: Intel Source: ITRS 99

10 SOC (IP) IP : : ARM, PowerPC,.. : RAM, memory controller, : PCI, DMA controller, : MPEG/JPEG encoder/decoder (DSP) : Ethernet controller, router,.. : Sequential program code (e.g., C, VHDL) Compilers (1960's,1970's) Assembly instructions Assemblers, linkers (1950's, 1960's) Machine instructions Behavioral synthesis (1990's) Register transfers RT synthesis (1980's, 1990's) Logic equations / FSM's Logic synthesis (1970's, 1980's) Logic gates Implementation + s: VLSI, ASIC, or PLD :,,,, ;. Source: Vahid/Givargis

11 / /

12 Unified Modeling Language (UML) UML HDLC++ C++ /

13 Technolog y ASIC FPGA Performance / Cost Very High Medium Time until running Very Long Medium Time to high performanc e Very Long Long Time to change code functionality Impossible Medium ASIP/ DSP High Long Long Long Generic Low-Medium Very Short Not Attainable Very Short

14 SOC

16 --SOC 5K gates re-usable : Processors: ARM, PowerPC,.. Memory: RAM, memory controller, Peripherals: PCI, DMA controller, Multimedia: MPEG/JPEG encoder/decoder Digital Signal Processor (DSP) Telecommunication: Ethernet controller, router,..

17 Soft cores ( code ) HDL IP Firm cores ( code+structure ) Hard cores ( physical ) IP or ATPG. system specification Behavioral HDL Soft RTL HDL Synthesizable RTL Gate Netlist Firm Mask Data Hard scheduling, binding system design control generation, FSM synthesis Bus Functional ISA model RTL Functional logic design Gate Functional floorplanning, placement, routing physical design Timing models Power models Fault Coverage

18 Licensable Foundary Captive 1. DSP Group (Pine and Oak Cores), 3Soft, ARM (RISC) HDL. 2. TI, Motorola, Lucent VLSI, SSI, Cirrus, Adaptec 3., LSI logic, TI, Lucent 74%. 26% IP : 40% hard, 68% soft, 32% firm

19 MEMORY SRAM 82% ROM 57% HighSpeed 46% Multiport 44% Low power 38% DRAM 38% Cache 20% Video 16% PROCESSORS 16-bit uc 40% 8-bit uc 30% RISC 28% 32-bit uc 20% x86 20% 68xx 18% DSP 16% PPC 14% Fixed 56K 4% Floating 4% INTERFACE etc. PCI 49% Comm. 40% UART 32% Video 18% USB 16% Graphics 14% Firmware 14% PCMCIA 12% GENERICS Accumulator 34% Adder 30% Mpy 30% Shifter 28% ANALOG ADC/DAC 44% PLL 44% Analog 32% RAMDAC 10% Rambus 4% DSP TI TEC320C52 16-bit fixed-point TMS320C52 1Kx16 data RAM, 4Kx16 program RAM 22 serial ports, 1 16-bit timer and 0.8 micron 15,000-gate gate array Motorola 7-Day CSIC 8-16 MHz HC08, DMA, MMU,.. SGS-Thomson ST18932, ST bit fixed-point DSPs, 0.5 u, 3.3 volt CMOS, 80MHz has no off-the-shelf DSP IC used in PC sound cards, 950 has a better assembly

20 Processor cores LSI Logic CW4001, CW4010 ARM (7) processors Motorola FlexCore Memory cores 16M/18M Rambus DRAM Multimedia cores CompCore CD2 Networking Media Access Controller (MAC) Encryption cores VLSI cores, ASIC international. Advanced RISC Machines (ARM ) A family of 32-bit RISC processor cores ARM6, ARM7: MPU with Cache, MMU, Write Buffer and JTAG ARM7TDMI :ARM7 with Thumb ISA, ICE, Debug ARM8 : cached, low power, 5-stage pipe (vs 3 in others) StrongARM1, StrongARM2: available as Digital SA-110 (21285) Manufacturing partnerships and/or licensing with Cirrus logic, GEC Plessey, Sharp, TI and VLSI Tech.

ARM Processor Cores Family Xstrs Process Size Clk Vcc Power MIPS mm 2 MHz (V) (mw) ARM6 33K 0.6u 5.6 45 5 225 40 ARM7 36K 0.6u 5.6 45/28 5/3 225/46 40/25 ARM7TDM 59K 0.6u 4.26 40/27 5/3 200/44 38/.

21 ARM Processor Cores Family Xstrs Process Size Clk Vcc Power MIPS mm 2 MHz (V) (mw) ARM6 33K 0.6u ARM7 36K 0.6u /28 5/3 225/46 40/25 ARM7TDM 59K 0.6u /27 5/3 200/44 38/.. ARM8 NA 0.5u NA 120 (est) Source: ARM Inc. Enhancements: ARM7D, ARM7DM, ARM7DMI M = 64-bit result hardware multiplier running at 8bits/cycle D = 2 boundary scan chains for basic debug I = Embedded ICE debug (in-circuit Emulator ) T = Thumb instruction set ARM Processor Cores

22 ARM : ICEin-circuit emulate ARM 40KB/s software download ASIC Debug Host running ARMsd ICE Uses boundary scan pins EmbeddedICE Cell (creates to core) ARM Core ARM Thumb ISA 16/32 816, 32 Thumb 32ARM 16-bit 32 ARM % 8/16 ARM130% 32 ARM85% always Rd Constant maj. opc.min. opc. dest. and src. 16-bit Thumb instr. ADD Rd #constant zero extended Rd 0 Rd 0000 Constant 32-bit ARM instr.

23 ARM 16,,, CD 32 ATM 32,, (RAM, ROMs) FlexCore CPU cores based on 680x0 family EC000, EC020, EC030 all with static operation, 5/3.3 volt supplies performance: EC000: mw EC020: 7.4 MHz, 150 mw EC030: 11.8 MHz, 258 mw Serial I/O cores: 68681UART, MBus, SPI RT clock, Dual timer cores SCSCI, Parallel I/O, 8051 interfaces DRAM, Interrupt, JTAG controllers PLA, PLL, oscillators, power management cells.

24 IP MPEG input Source: CompCore JPEG compression, CD2 MPEG decoding, Video Decoder microc. interface DAC, etc. IBM Microelectronics, LSI logic, PalmChip, virtual mem. controller Silicon Engineering, synchronization Audio Mentor Graphics, Decoder CompCore, Intrinsix SRAM SRAM SRAM VGA Example: MPEG-2 phy. mem. controller decoder from CompCore 70K-80K gates 18K bits of internal 1Mx16 SDRAM SRAM 16Mbit SDRAM audio stream video str. (external) Video Decoder PCI 25Verilog IP. IP, IP

25 SOC PCI Interface LAN Interface Processor Core Glue Graphics VRAM Motion Commodity Software: MEMORY - encryption/decryption - device drivers - legacy code Cache/SRAM - operating/runtime or even system DRAM EISA Interface Glue Video Commodity Hardware: -compression -encryption -modem -signal proc. -image proc. DSP compression Processor encryption Core SCSI Encryption/ Decryption I/O Interface SOC HDL Interface Analog I/O 4.,, ATPG automatic test pattern generation DMA Processor Interface Memory ASIC 3.,,.

26 ,? HDL?. 9 EDA Code generator Algorithm(s) C code Machine Definition Hardware Design & Synthesis Compiler Generator Compiler Assembly

27 System specification C description partitioning VHDL parts C parts synthesis compile Specific hardware + Standard Processor hardware

28 IP (FPGA) IP Datapath

30 (CGG) JBURG JBCORE/ Windows MIPS/ Irix X86/ Win9X SOC-System System on a Chip System on A die System on a package +

31 ? Intel Intel XScale XScale VLIW VLIW Thumb Thumb,

1 CPU

1 CPU 2000 Tel 82316285 82317634 Mail liuxd@buaa.edu.cn 1 CPU 2 CPU 7 72 A B 85 15 3 1/2 M301 2~17 : 3/4 1/2 323 IBM PC 1. 2. 3. 1. 2. 3. 1.1 Hardware Software 1.2 M3 M2 M1 1.2 M3 M1 M2 M2 M1 M1 M1 1.2 M3 M1