QT8-PV-DIS

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1 P STK UP LYER : TOP LYER : IN LYER : IN LYER : V LYER : IN LYER : OT able ocking PGE VG RJ- IR/Pwr btn SPIF Out Stereo MI Headphone Jack US Port VOL ntr SYSTEM HRGER(ISL) PGE SYSTEM POWER ISLIRZ-T PGE R II SMR_VTERM.V/.VSUS(TPSREGR) PGE VP +.V N +.V(MX) VGORE(.V~.V)Oz PGE PU ORE ISL PGE PGE 0 LN SMUS TLE lock gen/robson/tv tuner S--SL0/S0 /R/R thermal/ccelerometer E --SL/S E--SL/S epress card Wlan ard attery charge/discharge VG thermal/system thermal X Realtek PIE-LN RTL0E/ (0/00/GagaLN) PGE, RJ PGE TWO ST - H PGE ST - -ROM PGE E-ST +V +VS +VPU +V RII-SOIMM RII-SOIMM Keyboard Touch Pad IR (UIO ONN) PGE QT SYSTEM IGRM PGE, PGE, X Express ard (NEW R) PGE 0 ccelerometer LISLV0L PGE PGE PGE PGE apacitive Sense SW PGE RII /00 MHz RII /00 MHz X Mini PI-E ard PI-E (Wireless LN/TV TUNNER) PGE ST0 0M LVS PGE,, ST0, 0M SOUTH RIGE US.0 Ports lueflame Webcam Fingerprint X PGE 0 PGE 0 X PGE 0 PGE 0 ST 0M SMUS FN LP ENE K K x PGE P (upg)/w PGE,,, NORTH RIGE mm X mm, pin G PGE,,0,, LINK X S00 PU THERML SENSOR US.0 mm X mm, pin G.W(Ext) PIE US JMIRON JM0 for.w(int) iscrete zalia only PGE,... PGE PGE SPI PGE M Griffin SG Processor HT Lion Sabie RX / RS0MN M ONN PGE igital MI PGE 0 PI-Express X Side port mb RM for UM only PGE UIO ONN (Phone/ MI) PGE PGE IT H PGE UIO mplifier TP0 PGE udio onn PGE HMI PGE RT PGE PU_LK NGFX_LK NGPP_LK SLINK_LK IEEE connect for iscrete only PGE TI M-S for iscrete only it,r* M-SE PGE,, 0,, SSR_LK Memory ardreader PGE N/R Size ocument Number Rev ustom lock iagram ate: Tuesday, February, 00 Sheet of.mhz Flash Media for UM only RTS PROJET : QT Quanta omputer Inc. 0 LOK GEN ISLPRSKLFT-->HP SLGSPVTR-->HP RTM0N- -->HP PGE 0 PI-E WLN ard x PGE TV-TUNER ard x PGE Express ard x PGE able ocking x PGE PGE Touch Screen for iscrete only

2 +.V 00 0U/.V_ 0 ohm, 0. L LMPGSN(0,.)_ 0.U/0V_ 0.U/0V_ 0.U/0V_ +.V_LKVIO 0.U/0V_ 0.U/0V_ 0.U/0V_ LOKS name NGFX_LKP NGFX_LKN EXT_GFX_LKP EXT_GFX_LKN RX0 RP STUFF RP STUFF RS0 RP STUFF RP N lock pin function to N for VG reference clock to M-S external reference clock -RX0 only 0 +V R: 0. ohm 00 ohms@00mhz +V_LKV 0 ohm, 0. L LMPGSN(0,.)_ 0U/.V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ +V_LKV 0 0.U/0V_ 00 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ NGPP_LKP NGPP_LKN RP0 STUFF RP0 N SLINK_LKP SLINK_LKN RP STUFF RP STUFF to N for RX0 for PIEX interface reference clock only RS0 is internal share with -LINK clock,rs0 not need to N for -LINK reference clock +V_LKV HIPSET_PIE_SLOW_S# EXT_N_OS LK_M_US LK_M_R EVG-XTLI OS_SPRE +V Place very close to /G can remove MOSFET level shift S/clock gen / R is.v/s0 power level,,,, PLK_SM,,,, PT_SM *0P/0V_ *0P/0V_ *0P/0V_ *0P/0V_ *0P/0V_ SI- modified -- reserve for EMT L LMPGSN(0,.)_ 0U/.V_ P/0V_ P/0V_ Y.MHZ G_XIN G_XOUT +V_LK_V +V_LK_V +V_LKV +.V_LKVIO G_XIN G_XOUT LK_P# PLK_SM PT_SM S_SR_SLOW# *H0H-0PT L-F when driven low S_SR clocks slow only supported with to reduced setpoint custom G I R R R R 0.U/0V_ 0 0.U/0V_ *.K_ *.K_ *.K_ *.K_ if use clock request pin, need to pull Hi for default sttting LKREQ0# LKREQ# LKREQ# LKREQ# U0 V GN VREF GNREF V VTIG VPU VHTT VS_SR VSR VST VOT X X SMLK SMT P# S_SR_SLOW# THERML GN egn egn egn U0 SLGSPVTR IS SLG RTL SLGSPVTR * default SEL_HTT 0* PUKG0T_LPRS PUKG0_LPRS TIG0T_LPRS TIG0_LPRS TIGT_LPRS TIG_LPRS 0 TIGT_LPRS TIG_LPRS S_SR0T_LPRS 0 S_SR0_LPRS S_SRT_LPRS S_SR_LPRS VPU_IO SR0T_LPRS VTIG_IO SR0_LPRS VS_SR_IO SRT_LPRS VSR_IO SR_LPRS 0 VSR_IO SRT_LPRS SR_LPRS SRT_LPRS GN SR_LPRS GNTIG SRT_LPRS 0 GNOT SR_LPRS GNPU SRT_LPRS GNHTT SR_LPRS GNST SRT/STT_LPRS GNS_SR SR/ST_LPRS GNSR SRT_LPRS/Mhz_SS GNSR SR_LPRS/Mhz_NS HTT0T/M_LPRS 0 HTT0/M_LPRS MHz_0 MHz_ 0 REF0/SEL_HTT REF/SEL_ST REF/SEL_ LKREQ0# LKREQ# LKREQ# 0 LKREQ# LKREQ# egn egn egn MHz.V single ended HTT clock 00 MHz differential HTT clock LK_VG_M_SS LK_VG_M_NSS PULKP PULKN NGFX_LKP NGFX_LKN EXT_GFX_LKP EXT_GFX_LKN PIE_MINI_LKP PIE_MINI_LKN LK_PIE_R LK_PIE_R# NGPP_LKN_R NGPP_LKN_L PIE_NEW_LKP PIE_NEW_LKN PIE_MINI_LKP PIE_MINI_LKN SLINK_LKP SLINK_LKN SSR_LKP SSR_LKN PIE_LN_LKP PIE_LN_LKN LK_VG_M_SS LK_VG_M_NSS NHTREFLK0P NHTREFLK0N LK_M_R_L LKMUS SEL_HT SEL_ST SEL_ ISLPRKLFT--JRS0000 SLGSPVTR--J RTM0N--- J LKREQ0# EXT_NW_LK_REQ# LKREQ# LKREQ# LKREQ# R,R,R STUFF R,R,R N Place within 0." R *_ of LKGEN RP *0_PR_ PULKP PULKN RP RP T T RP RP *0_PR_ NGFX_LKP NGFX_LKN *0_PR_ EXT_GFX_LKP EXT_GFX_LKN *0_PR_ PIE_MINI_LKP PIE_MINI_LKN *0_PR_ LK_PIE_R LK_PIE_R# EXT_NW_LK_REQ# lock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose. +V_LKV To M-S Mhz - RX0 only SEL_ SEL_ST SEL_HT el RP for TP on PV PULKP PULKN NGFX_LKP 0 NGFX_LKN 0 EXT_GFX_LKP EXT_GFX_LKN NHT_REFLKP 0 NHT_REFLKN 0 LK_M_R LK_M_US PIE_MINI_LKP PIE_MINI_LKN LK_PIE_R LK_PIE_R# to N for external Graphics reference clock to M-S -RX0 only to TV TUNER R to PIE-R REER T el RP for NGPP LK T RP *0_PR_ PIE_NEW_LKP PIE_NEW_LKP PIE_NEW_LKN PIE_NEW_LKN to EPRESS R RP *0_PR_ PIE_MINI_LKP PIE_MINI_LKP PIE_MINI_LKN PIE_MINI_LKN to WLN RP *0_PR_ SLINK_LKP SLINK_LKP 0 SLINK_LKN SLINK_LKN 0 to N for -LINK reference clock RP *0_PR_ SSR_LKP SSR_LKP SSR_LKN SSR_LKN to S RP *0_PR_ PIE_LN_LKP PIE_LN_LKP PIE_LN_LKN PIE_LN_LKN to PIE-LN SI- Modified --remove to ROSON R _ OS_SPRE OS_SPRE R /F_ EVG-XTLI SSIN - for M -.V level input R0 00/F_ X_TLIN --for M -.V level input R 0_ NHT_REFLKP R 0_ NHT_REFLKN R0 _ LK_M_R R _ LK_M_US R *.K_ R.K_ T T R Ra Rb Ra Rb EXT_NW_LK_REQ# LK_P# RX0.V.R 0R S_SR_SLOW# /F_ R 0./F_ RS0.V R 0.R RES HIP 0 /W +-%(00)L-F -->S0F RES HIP /W +-%(00) -->SF00 RES HIP 0. /W +-%(00) -->S00F RES HIP. /W +-%(00) -->S0F.K_.K_.K_ EXT_N_OS 0 R R0 R +V SEL_ST 0* SEL_ * 0 00 MHz non-spreading differential SR clock 00 MHz spreading differential SR clock MHz non-spreading singled clock 00 MHz spreading differential SR clock R0.K_ R0 *.K_ RS0M/RX0M N/R PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom lock Generator ate: Tuesday, February, 00 Sheet of

3 +.V R 0_ R 0_ HT_N_PU H[..0] HT_N_PU L[..0] HT_N_PU_LK_H[..0] HT_N_PU_LK_L[..0] HT_N_PU_TL_H[..0] HT_N_PU_TL_L[..0] HT_PU_N H[..0] HT_PU_N L[..0] HT_PU_N_LK_H[..0] HT_PU_N_LK_L[..0] HT_PU_N_TL_H[..0] HT_PU_N_TL_L[..0] +.V_VLT +.V_VLT HT_N_PU H[..0] HT_N_PU L[..0] HT_N_PU_LK_H[..0] HT_N_PU_LK_L[..0] HT_N_PU_TL_H[..0] HT_N_PU_TL_L[..0] HT_PU_N H[..0] HT_PU_N L[..0] HT_PU_N_LK_H[..0] HT_PU_N_LK_L[..0] HT_PU_N_TL_H[..0] HT_PU_N_TL_L[..0].U/.V_.U/.V_ 0.U/.V_ 0P/0V_ FOX PZ-R-F G0^00000 I SOKET SM P S(P.,H.) MLX - G0^00000 I SOKET SM P S(P.,H.) TY -00- G0^00000 I SOKET SM P S(P.,H.) +.V +.V_VLT +.V_VLT +.V_VLT +.V_VLT HT_N_PU H0 E HT_N_PU L0 E HT_N_PU H E HT_N_PU L F HT_N_PU H G HT_N_PU L G HT_N_PU H G HT_N_PU L H HT_N_PU H J HT_N_PU L K HT_N_PU H L HT_N_PU L L HT_N_PU H L HT_N_PU L M HT_N_PU H N HT_N_PU L N HT_N_PU H E HT_N_PU L F HT_N_PU H F HT_N_PU L F HT_N_PU H0 G HT_N_PU L0 H HT_N_PU H H HT_N_PU L H HT_N_PU H K HT_N_PU L K HT_N_PU H L HT_N_PU L M HT_N_PU H M HT_N_PU L M HT_N_PU H N HT_N_PU L P HT_N_PU_LK_H0 HT_N_PU_LK_L0 HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H0 HT_N_PU_TL_L0 HT_N_PU_TL_H HT_N_PU_TL_L LMPGSN(0,00M,)_ W/S= mil/0mil +PUV L LS00-00M-N 0U/.V_ U VLT_0 VLT_ VLT_ VLT_ L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L J L0_LKIN_H0 J L0_LKIN_L0 J L0_LKIN_H K L0_LKIN_L N L0_TLIN_H0 P L0_TLIN_L0 P L0_TLIN_H P L0_TLIN_L SOKET PIN HT LINK.U/.V_ 0.U/.V_ VLT_0 E VLT_ E VLT_ E VLT_ E L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H W L0_OUT_L W L0_OUT_H V L0_OUT_L U L0_OUT_H U L0_OUT_L U L0_OUT_H T L0_OUT_L R L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H Y L0_OUT_L W L0_OUT_H V L0_OUT_L V L0_OUT_H V L0_OUT_L U L0_OUT_H T L0_OUT_L T L0_LKOUT_H0 Y L0_LKOUT_L0 W L0_LKOUT_H Y L0_LKOUT_L Y L0_TLOUT_H0 R L0_TLOUT_L0 R L0_TLOUT_H T L0_TLOUT_L R 00P/0V_ +.V_VLT.U/.V_ +.V_VLT 0.U/.V_ +.V_VLT 0P/0V_ +.V_VLT HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H0 HT_PU_N_LK_L0 HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H0 HT_PU_N_TL_L0 HT_PU_N_TL_H HT_PU_N_TL_L PU_THERM R 0_ PU_THERM R 0_ PU LK PU_LT_RST# 00_ R PULKP PU_LT_STOP# 00_ R0 PULKP PULKN PU_PWRG 00_ R PULKN PU_LT_REQ#_PU 00_ R Keep trace from resisor to PU within 0." +PUV keep trace from caps to PU within." U W/S= mil/0mil +PUV F 0 PULKIN R /F_ PULKIN# +PUV V KEY F V KEY PULKP 0 00P/V_ PULKIN PULKN 0 00P/V_ PULKIN# LKIN_H SV LKIN_L SV PU_LT_RST# 0, PU_LT_RST# PU_PWRG RESET_L PU_PWRG PU_LT_STOP# PWROK 0, PU_LT_STOP# F0 PU_LT_REQ#_PU LTSTOP_L THERMTRIP_L LTREQ_L PROHOT_L PU_SI MEMHOT_L PU_SI F Sideand Temp sense I PU_SI SI PU_SI F PU_LERT SI PU_LERT E LERT_L THERM R./F_ PU_HTREF0 THERM R +.V_VLT R./F_ PU_HTREF HT_REF0 P place them to PU within." HT_REF 0 PU_V0_RUN_F_H F V0_F_H VIO_F_H 0 PU_V0_RUN_F_L E V0_F_L VIO_F_L 0 PU_V_RUN_F_H Y V_F_H VN_F_H 0 PU_V_RUN_F_L V_F_L VN_F_L PU_RY G0 PU_TMS RY PU_TK TMS REQ_L PU_TRST# TK PU_TI TRST_L TO F TI PUTEST T TEST TEST_H SI- modified for M PUTEST TEST_L T H0 sighting update PUTEST TEST T G TEST TEST +.VSUS R 0/F_ PUTESTH TEST E R0 0/F_ PUTESTL TEST_H TEST E TEST_L TEST +.VSUS R R 00/F_ 00/F_ R 00_ T T T R 0_ PUTEST PUTEST0 PUTEST PUTEST PUTEST PUTEST TEST F TEST0 E TEST E TEST TEST F TEST TEST TEST RSV RSV RSV RSV RSV SOKET PIN TEST TEST0 TEST TEST_H TEST_L RSV0 RSV RSV RSV RSV M W F W W W Y H G H_THRM H_THRM +.V PU_SV_R PU_SV_R PU_THERMTRIP_L# PU_PROHOT_L# PU_MEMHOT_L# PU_THERM PU_THERM VIO_F_H VIO_F_L E0 PU_REQ# R E PU_TO J H E F K H H PUTESTH PUTESTL PUTEST PUTEST PUTEST PUTEST PUTESTH PUTESTL 0 SI- modified -- confirm M R need to stuff VIO_F_H VIO_F_L PU_VN_RUN_F_H 0 PU_VN_RUN_F_L 0 T0 T T T T T T T0 00/F_ +.VSUS SI- modified for M sighting update +V R 0K/F_ Q PU_LT_REQ#_PU NTR_VREF R 0.U/0V_.K/F_ *SS_NL/SOT NTR_VREF PU_LT_REQ# 0 NTR_VREF PU_LT_RST# R 0_ +V R K/F_ PU_LT_RST_HTP# Q0 SS_NL/SOT Serial VI R *.K_ R K/F_ +.VSUS R K/F_ PU_SV_R R 0_ PU_SV_R R 0_ PU_PWRG R 0_ R0 *0_ R *0_ *0.U/0V_ PU_SV PU_SV PU_PWRG_SVI_REG PU_SV 0 PU_SV 0 PU_PWRG_SVI_REG 0 VFIX MOE VI Override ircuit SV SV Voltage Output 0 0.V 0.V 0.0V 0.V R0 0_ G *SHORT_ P SI- remove for power up seq +.VSUS R 0K/F_ for debug only +.VSUS R 00_ PU_MEMHOT_L# Q MMT0 PU_MEMHOT# PU_MEMHOT#, HT onnector +.VSUS PUTEST0 PUTEST PUTEST PUTEST PUTEST PUTEST PUTEST R R R00 R0 R0 R0 R0 *00/F_ *00/F_ *00/F_ *00/F_ *00/F_ *00/F_ *00/F_ +.VSUS R 0K/F_ +.VSUS R 00_ PU_PROHOT_L# Q MMT0 PU_PROHOT# +.VSUS R0 0K/F_ +.VSUS R 00_ Q0 MMT0 PU_THERMTRIP_L# PU_THERMTRIP# PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO *0.U/0V_ 0 0 KEY N *HT ONN PU_LT_RST_HTP# SI- reserve for M recommend N/R PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom SG HT,TL I/F / ate: Tuesday, February, 00 Sheet of

4 E E M_ZN M_ZP MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_T PU_VTT_SENSE MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_RESET# MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_RESET# MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEMVREF_PU MEM_M_LK_P MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_LK_N MEM_M_[0..], MEM_M0_OT0, MEM_M0_OT, MEM_M0_S#0, MEM_M0_S#, MEM_M_KE0, MEM_M_KE, MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_NK0, MEM_M_NK, MEM_M_NK, MEM_M_RS#, MEM_M_S#, MEM_M_WE#, MEM_M_NK0, MEM_M_NK, MEM_M_NK, MEM_M_RS#, MEM_M_S#, MEM_M_WE#, MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_KE0, MEM_M_KE, MEM_M0_S#0, MEM_M0_S#, MEM_M0_OT0, MEM_M0_OT, MEM_M_[0..], MEM_M_T[0..] MEM_M_M[0..] MEM_M_QS0_P MEM_M_QS0_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS0_P MEM_M_QS0_N MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_M[0..] MEM_M_T[0..] PU_VTT_SENSE +0.VSMVREF, +0.VSMVTT +0.VSMVTT +.VSUS +0.VSMVTT +0.VSMVTT +.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N/R SG RII MEMORY I/F / ustom Tuesday, February, 00 PLE THEM LOSE TO PU WITHIN " Processor Memory Interface Place close to socket 0 lose to PU within 00 mils Reserved 0 m 0 0.U/.V_.U/.V_ P/0V_.P/0V_ R./F_ 0.U/.V_ MEM:M/TRL/LK U SOKET PIN VTT 0 VTT 0 VTT 0 VTT 0 VTT W0 VTT 0 VTT 0 VTT 0 VTT 0 M_OT V M_OT0 U M0_OT V M0_OT0 T M_OT0 Y M0_OT W M0_OT0 W RSV_M M_S_L0 U M0_S_L W M0_S_L0 V M0_S_L U M_S_L V0 M_S_L0 U0 M0_S_L0 T0 M_ K M_ K M_ V M_ K0 M_ L M_0 R M_ K M_ L M_ L M_ M M_ L0 M_ M M_ M M_ N M_ M0 M_0 N M_NK J M_NK R M_NK0 R0 M_RS_L R M_S_L T M_WE_L T MEMZP F0 MEMZN E0 VTT_SENSE Y0 MEMVREF W M_LK_H P M_LK_L P0 M_LK_H Y M_LK_L M_LK_H E M_LK_L F M_LK_H N M_LK_L N0 M_LK_H R M_LK_L R M_LK_H F M_LK_L F M_LK_H M_LK_L M_LK_H P M_LK_L R M_KE0 J M_KE J0 M_KE0 J M_KE H M_ J M_ J M_ W M_ L M_ L M_0 T M_ K M_ M M_ L M_ N M_ L M_ N M_ N M_ P M_ N M_0 P M_NK J M_NK U M_NK0 R M_RS_L U M_S_L U M_WE_L U RSV_M H 0P/0V_ R./F_ 0 000P/0V_ 000P/0V_.P/0V_ R K/F_ 0 0P/0V_.U/.V_ 000P/0V_.U/.V_ T 0.U/.V_.U/.V_ 0 000P/0V_ 0P/0V_ R K/F_ 0.U/.V_.P/0V_ R *0_ T 0P/0V_ MEM:T U SOKET PIN M_T M_T F M_T F M_T0 E M_T Y M_T M_T M_T F M_T F M_T F M_T M_T F M_T M_T0 M_T E M_T M_T 0 M_T 0 M_T F M_T F M_T F0 M_T E0 M_T M_T0 M_T E M_T M_T M_T M_T E M_T M_T M_T M_T G M_T0 G M_T M_T M_T G M_T G M_T E M_T E M_T M_T M_T 0 M_T0 0 M_T M_T M_T M_T 0 M_T M_T M_T M_T M_T 0 M_T0 M_T M_T M_T M_T M_T E M_T G M_T M_T M_T M_T0 M_T M_T M_T M_T0 M_T W M_T Y M_T M_T M_T M_T M_T M_T Y M_T Y M_T0 W M_T W M_T M_T Y M_T M_T M_T M_T M_T M_T 0 M_T0 Y0 M_T M_T Y M_T W M_T W M_T M_T M_T M_T Y M_T H M_T0 H0 M_T E M_T E M_T J M_T H M_T F M_T F0 M_T M_T M_T F M_T0 E M_T E0 M_T M_T M_T G M_T G M_T M_T F M_T E M_T H M_T0 E M_T E M_T H M_T E M_T M_T H M_T H M_T G M_T H M_T F M_T0 G M_M M_M M_M E M_M M_M E M_M M_M M_M0 M_QS_H F M_QS_L E M_QS_H E M_QS_L M_QS_H F M_QS_L F M_QS_H M_QS_L M_QS_H F M_QS_L E M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H0 M_QS_L0 M_M Y M_M M_M Y M_M M_M F M_M E M_M M_M0 E M_QS_H W M_QS_L W M_QS_H Y M_QS_L W M_QS_H M_QS_L 0 M_QS_H M_QS_L M_QS_H G M_QS_L G M_QS_H M_QS_L M_QS_H G M_QS_L G M_QS_H0 G M_QS_L0 H.P/0V_ 0.U/0V_

5 ,, +VORE0 UE G V0_ V_ H V0_ V_ J V0_ V_ J V0_ V_ J V0_ V_ J V0_ V_ K V0_ V_ K0 V0_ V_ K V0_ V_ K V0_0 V_0 L V0_ V_ L V0_ V_ L V0_ V_ L V0_ V_ L V0_ V_ L V0_ V_ M V0_ V_ M V0_ V_ M V0_ V_ M0 V0_0 V_0 N +PUVN V0_ V_ N V0_ V_ N V0_ V_ V_ K VN_ V_ M VN_ V_ P VN_ T +.VSUS VN_ VIO V VN_ VIO VIO H VIO VIO J VIO VIO K VIO VIO K VIO VIO K VIO VIO0 K VIO VIO L VIO VIO M VIO VIO M VIO VIO M VIO0 VIO M VIO VIO N VIO VIO SOKET PIN NTR_VREF Q MLK MLK *SS_NL/SOT MT MT Q *SS_NL/SOT Q SMLERT# *SS_NL/SOT P P0 R R R R T T T T0 T T U U U U U V V V0 V V W Y Y V V V V U T T T T R P P P P +VORE PU_SI PU_SI R 0_ PU_LERT +.VSUS +.VSUS R 0_ R K/F_ PU_SI PU_SI PU_LERT UF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 E VSS E VSS E VSS E VSS E VSS E VSS E VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 E VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS0 H VSS H VSS H VSS H VSS J VSS SOKET PIN VSS J VSS J VSS J0 VSS J VSS0 J VSS J VSS J VSS K VSS K VSS K VSS K VSS K VSS K VSS K VSS0 L VSS L VSS L0 VSS L VSS L VSS L VSS L VSS M VSS M VSS VSS0 M VSS N VSS N VSS N0 VSS N VSS N VSS P VSS P VSS P VSS P VSS00 P VSS0 R VSS0 R0 VSS0 R VSS0 R VSS0 T VSS0 T VSS0 T VSS0 T VSS0 T VSS0 T VSS U VSS U VSS U VSS U0 VSS U VSS U VSS U VSS U VSS V VSS0 V VSS V VSS V VSS V VSS V VSS V VSS W VSS Y VSS Y VSS N +VORE0 U/.V_ +VORE +PUVN +.VSUS +.VSUS 0 U/.V_ U/.V_ OTTOM SIE EOUPLING 0 U/.V_ 0 U/.V_ +.VSUS 0.U/.V_ EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE 0.U/.V_ 0.U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0.U/.V_ 0.U/.V_ 0 U/.V_.U/.V_ 0.0U/V_ U/.V_ U/.V_.U/.V_ 0 0.0U/V_ 0 0.U/.V_ U/.V_ 0P/0V_ 0 0.U/.V_ PROESSOR POWER N GROUN 0.0U/V_ 0.0U/V_ 0 0.U/.V_ 0 0P/0V_ 0 0P/0V_ 0.U/.V_ 0 0.U/.V_ 0.0U/V_ 0P/0V_ 0P/0V_ 0 +V +V +VORE0 +VORE el R0, R on PV,, MLK MT PM_THERM# R 0K/F_ R 0K/F_ SI- Modified for H/W thermal shutdown 00/F_ Update U P/N R0 *0_ SYS_SHN# SYS_SHN#, R on PV +.V E 0.0U/V_ reserve for 0K/F_ power shutdown +.V E 0.0U/V_ ( if can ) *H00H 0.U/0V_ +VPU E 0.0U/V_ U SLK V S XP LERT# XN OVERT# GN MSOP GP R H_THRM 00P/0V_ SMLERT# H_THRM R 0_ Q MMT0 H0H-0PT R 0_RST# EPWROK 0K/F_ +V 0_RST#, EPWROK, +.VSUS +V +VG_ORE E0 E E E E 0.0U/V_ *0.0U/V_ *0.0U/V_ 0.0U/V_ 0.0U/V_ +VPU +VPU +V +V +.VSUS E 0.0U/V_ +V +V +.V +V E 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ For fix HyperTransport nets across plane splits +VPU +.VSUS +.VSUS PU_THERMTRIP_L# R0 *0K/F_ R0 *00_ Q *MMT0 PU_THERMTRIP_L# SMLERT# PQ0 *N00E-G R0 *0K/F_ TEMP_FIL VG TEMP_ FIL function MX is active Hi, MX acvite Low +VS E *0.U/0V_ +VS E *0.U/0V_ +V +.V E E *0.U/0V_ *0.U/0V_ N/R PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom SG PWR & GN / ate: Tuesday, February, 00 Sheet of

6 MEM_M_N MEM_M_ MEM_M_ MEM_M_NK0 MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK PT_SM PLK_SM MEM_M_T MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEMHOT_SOIMM#_ MEM_M_ MEM_M_RESET# MEM_M_NK0 MEM_M_ MEM_M_ MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_NK MEM_M_T MEM_M_N MEM_M_RESET# MEMHOT_SOIMM# PT_SM MEM_M_T PLK_SM MEMHOT_SOIMM#_ MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 MEM_M_M MEM_M_M MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ IM_S0 IM_S IM_S0 IM_S IM_S0 IM_S IM_S0 IM_S +0.VSMVREF_IMM PT_SM,,,, PLK_SM,,,, MEM_M_T[0..] MEM_M_M[0..] MEM_M_M[0..] MEM_M_QS0_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS0_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_QS_N MEM_M_LK_P MEM_M_LK_N MEM_M_LK_P MEM_M_LK_N MEM_M_KE0, MEM_M_KE, MEM_M_RS#, MEM_M_S#, MEM_M_WE#, MEM_M0_S#0, MEM_M0_OT0, MEM_M0_OT, MEM_M0_S#, MEM_M_NK[0..], MEM_M_[0..], MEMHOT_SOIMM# MEM_M_QS_N MEM_M_QS_N MEM_M_KE0, MEM_M_KE, MEM_M_QS_N MEM_M_QS_N MEM_M_RS#, MEM_M_S#, MEM_M_WE#, MEM_M0_S#0, MEM_M0_OT0, MEM_M0_OT, MEM_M_QS_P MEM_M_QS_P MEM_M0_S#, MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_QS_P MEM_M_LK_P MEM_M_QS0_N MEM_M_LK_N MEM_M_QS0_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_N MEM_M_LK_P MEM_M_LK_N MEM_M_NK[0..], MEM_M_[0..], MEM_M_T[0..] +0.VSMVREF, +.VSUS +.VSUS +V +0.VSMVREF_IMM +0.VSMVREF_IMM +V +.VSUS +V +0.VSMVREF_IMM Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N/R R SOIMMS: / HNNEL ustom Tuesday, February, 00 o o SMbus address SMbus address 0 H=. H=. 0 Only for reserved.u/.v_ R *0_ R 0K/F_ T R 0K/F_ 0 0.U/0V_ T 0 0.U/0V_ SO-IMM (Normal) N0 R SO-IMM SOKET.V Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 GN 0 GN 0 SO-IMM (REVERSE) N R SO-IMM SOKET.V Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 GN 0 GN 0 R0 0_ R K/F_ 0.U/0V_ 0.U/.V_ R0 0_ 000P/0V_ R0 K/F_ 000P/0V_ R0 0K/F_ T 0 0.U/0V_ R 0K/F_ T

7 , MEM_M_[0..], MEM_M_NK[0..] MEM_M_[0..] MEM_M_NK[0..], MEM_M_[0..], MEM_M_NK[0..] MEM_M_[0..] MEM_M_NK[0..] 0 +0.VSMVTT +0.VSMVTT, MEM_M_KE0, MEM_M_WE#, MEM_M_S#, MEM_M0_OT, MEM_M0_S#, MEM_M_KE, MEM_M0_S#0, MEM_M_RS#, MEM_M0_OT0 MEM_M_KE0 RP0 MEM_M_NK MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_ RP MEM_M_ MEM_M_0 RP0 MEM_M_NK0 MEM_M_WE# RP MEM_M_S# MEM_M0_OT RP0 MEM_M0_S# MEM_M_ RP MEM_M_KE MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_0 MEM_M0_S#0 MEM_M_RS# MEM_M_ MEM_M0_OT0 RP RP RP RP RP RP _PR PR PR PR PR PR PR PR PR PR PR PR PR PR_ U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS, MEM_M_KE0, MEM_M_WE#, MEM_M_S#, MEM_M0_OT, MEM_M0_S#, MEM_M_KE, MEM_M0_S#0, MEM_M_RS#, MEM_M0_OT0 MEM_M_KE0 MEM_M_NK MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_NK0 MEM_M_WE# MEM_M_S# MEM_M0_OT MEM_M0_S# MEM_M_KE MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_NK MEM_M_0 MEM_M0_S#0 MEM_M_RS# MEM_M0_OT0 MEM_M_ RP RP RP RP RP RP RP RP RP RP0 RP RP RP RP _PR PR PR PR PR PR PR PR PR PR PR PR PR PR_ U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS +.VSUS PLE LOSE TO PROESSOR WITHIN. INH PLE LOSE TO PROESSOR WITHIN. INH +.VSUS +.VSUS 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PLE LOSE TO SOKET( PER EMI/EM) PLE LOSE TO SOKET( PER EMI/EM) +VS SI- modified --S internal pull HI to vs +V R *0K/F_ R *0K/F_ PU_MEMHOT#, lose R socket U +V R *_,,,,,,,, PT_SM PLK_SM +V PT_SM PLK_SM 0 0.U/0V_ 0 +VS MEMHOT_SOIMM# O.S Q S *N00E-G SL GN ddress:h *SU+T&R Q *N00E-G +V R 0K/F_ MEMHOT_SOIMM# MEMHOT_SOIMM# PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom R SOIMMS TERMINTIONS ate: Tuesday, February, 00 Sheet of

8 SI- modified -- follow M check list to change part number 00 ohm to 0 ohm R HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H0 HT_PU_N L0 HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N H HT_PU_N L HT_PU_N_LK_H0 HT_PU_N_LK_L0 HT_PU_N_LK_H HT_PU_N_LK_L HT_PU_N_TL_H0 HT_PU_N_TL_L0 HT_PU_N_TL_H HT_PU_N_TL_L R 0/F_ HT_RXLP HT_RXLN U Y HT_RX0P HT_TX0P Y HT_RX0N PRT OF HT_TX0N V HT_RXP HT_TXP V HT_RXN HT_TXN V HT_RXP HT_TXP V HT_RXN HT_TXN U HT_RXP HT_TXP U HT_RXN HT_TXN T HT_RXP HT_TXP T HT_RXN HT_TXN P HT_RXP HT_TXP P HT_RXN HT_TXN P HT_RXP HT_TXP P HT_RXN HT_TXN N HT_RXP HT_TXP N HT_RXN HT_TXN HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N Y HT_RXP Y HT_RXN W HT_RXP W0 HT_RXN V HT_RXP V0 HT_RXN U0 HT_RXP U HT_RXN U HT_RXP U HT_RXN T HT_RXLK0P T HT_RXLK0N HT_RXLKP HT_RXLKN M HT_RXTL0P M HT_RXTL0N R HT_RXTLP R0 HT_RXTLN HT_RXLP HT_RXLN RS0(RX0) HYPER TRNSPORT PU I/F HT_TXP HT_TXN HT_TXP HT_TXN HT_TX0P HT_TX0N HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXP HT_TXN HT_TXLK0P HT_TXLK0N HT_TXLKP HT_TXLKN HT_TXTL0P HT_TXTL0N HT_TXTLP HT_TXTLN HT_TXLP HT_TXLN E E F F F F H H J J K K K K F G G0 H J0 J J K L J M L M P P M H H L L0 M M P R HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H0 HT_N_PU L0 HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU H HT_N_PU L HT_N_PU_LK_H0 HT_N_PU_LK_L0 HT_N_PU_LK_H HT_N_PU_LK_L HT_N_PU_TL_H0 HT_N_PU_TL_L0 HT_N_PU_TL_H HT_N_PU_TL_L HT_TXLP HT_TXLN R R 0/F_ SI- modified -- follow M check list to change part number 00 ohm to 0 ohm HT_PU_N H[..0] HT_PU_N L[..0] HT_PU_N_LK_H[..0] HT_PU_N_LK_L[..0] HT_PU_N_TL_H[..0] HT_PU_N_TL_L[..0] HT_N_PU H[..0] HT_N_PU L[..0] HT_N_PU_LK_H[..0] HT_N_PU_LK_L[..0] HT_N_PU_TL_H[..0] HT_N_PU_TL_L[..0] HT_TXLP HT_TXLN HT_RXLP HT_RXLN HT_PU_N H[..0] HT_PU_N L[..0] HT_PU_N_LK_H[..0] HT_PU_N_LK_L[..0] HT_PU_N_TL_H[..0] HT_PU_N_TL_L[..0] HT_N_PU H[..0] HT_N_PU L[..0] HT_N_PU_LK_H[..0] HT_N_PU_LK_L[..0] HT_N_PU_TL_H[..0] HT_N_PU_TL_L[..0] signals RS0 RX0 R 0 ohm % R 0 ohm % R.k ohm % R.k ohm % 0 RES HIP.K /W +-%(00) P/N : SF RES HIP 0 /W +-%(00) P/N : S0F *0.U/0V_ *0.U/0V_ R Within 00mils +.V_MEM_VQ *00_ R *K_ R *K_ SPM_0 SPM_ SPM_ SPM_ SPM_0 SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_ SPM_0 SPM_LKN SPM_LKP SPM_KE SPM_S# SPM_WE# SPM_RS# SPM_S# SPM_M0 SPM_M SPM_OT SPM_QS0P SPM_QS0N SPM_QSP SPM_QSN SPM_VREF SPM_ U L 0 L R P M 0/P P P P N N N N M M M 0 K K J K K KE L S K WE K RS L S F LM UM K OT F LQS E LQS UQS UQS J VREF N# E N#E L N#L R N#R R N#R R N#R Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 V V V V V VL VSSL VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ0 VSS VSS VSS VSS VSS F F H H H H G G E G G G G E J M R J J E F F H H E J N P This block is for UM RS0 only, RX0 can remove all component SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q0 SPM_Q SPM_Q SPM_Q SPM_Q U SPM_Q PR OF SPM_Q SPM_0 SPM_Q0 SPM_ MEM_0(N) MEM_Q0/VO_VSYN(N) E SPM_Q SPM_ MEM_(N) MEM_Q/VO_HSYN(N) V SPM_Q SPM_ MEM_(N) MEM_Q/VO_E(N) E SPM_Q SPM_ MEM_(N) MEM_Q/VO_0(N) SPM_ MEM_(N) MEM_Q(N) SPM_ MEM_(N) MEM_Q/VO_(N) +.V_MEM_VQ SPM_ MEM_(N) MEM_Q/VO_(N) SPM_ MEM_(N) MEM_Q/VO_(N) SPM_ MEM_(N) MEM_Q/VO_(N) SPM_0 MEM_(N) MEM_Q/VO_(N) SPM_ MEM_0(N) MEM_Q0/VO_(N) T E SPM_ MEM_(N) MEM_Q/VO_(N) SPM_ MEM_(N) MEM_Q(N) Y MEM_(N) MEM_Q/VO_(N) SPM_0 MEM_Q/VO_0(N) SPM_ MEM_0(N) MEM_Q/VO_(N) E SPM_ MEM_(N) MEM_(N) MEM_QS0P/VO_IKP(N) L SPM_RS# MEM_QS0N/VO_IKN(N) W SPM_S# MEM_RSb(N) MEM_QSP(N) Y SPM_WE# MEM_Sb(N) MEM_QSN(N) *LMPGSN(0,.)_ SPM_S# MEM_WEb(N) SPM_KE MEM_Sb(N) MEM_M0(N) MEM_VQ_VL SPM_OT MEM_KE(N) MEM_M/VO_(N) V MEM_OT(N) SPM_LKP IOPLLV(N) V SPM_LKN MEM_KP(N) IOPLLV(N) W MEM_KN(N) *U/0V_ R0 *0./F_ SPM_OMPP IOPLLVSS(N) E R0 *0./F_ SPM_OMPN MEM_OMPP(N) MEM_OMPN(N) MEM_VREF(N) +.V_MEM_VQ RS0(RX0) S_MEM/VO_I/F 0 Y V Y 0 E 0 Y W 0 E W E SPM_Q0 SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q0 SPM_Q SPM_Q SPM_Q SPM_Q SPM_Q SPM_QS0P SPM_QS0N SPM_QSP SPM_QSN SPM_M0 SPM_M E +._IOPLLV_N E +.V_IOPLLV E SPM_VREF R *K_ R +.V_MEM_VQ 0mils wdith or more R *.U/.V_ *K_ 0 *U/0V_ *0.U/0V_ *0.U/0V_ *0.U/0V_ *0U/.V_ *0.U/0V_ IOPLLV - memory PLL not applicable to RX0 *.U/.V_ +.V_MEM_VQ *0U/.V_ *U/0V_ *0_ PROJET : QT Quanta omputer Inc. +.V el L, L for TP on PV IOPLLV- memory PLL not applicable to RX0 *HYTF- N/R Size ocument Number Rev ustom RS0/RS0-HT LINK I/F / ate: Tuesday, February, 00 Sheet of

9 PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX0 PEG_RX#0 PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX0 PEG_RX#0 PIE_RXP0 PIE_TXP0_ PIE_RXP0 E PIE_RXN0 GPP_RX0P GPP_TX0P 0.U/0V_ PIE_TXP0 PIE_TXN0_ PIE_RXN0 PIE_RXP GPP_RX0N GPP_TX0N 0.U/0V_ PIE_TXN0 PIE_TXP_ PIE_RXP E 0.U/0V_ PIE_RXN GPP_RXP GPP_TXP PIE_TXP PIE_TXN_ PIE_RXN PIE_RXP_LN GPP_RXN GPP_TXN 0 0.U/0V_ PIE_TXN PIE_TXP_ PIE_RXP_LN 0.U/0V_ PIE_TXP_LN PIE_RXN_LN GPP_RXP GPP_TXP PIE_TXN_ PIE_RXN_LN PIE I/F GPP 0.U/0V_ PIE_TXN_LN PIE_RXP GPP_RXN GPP_TXN PIE_TXP_ PIE_RXP V PIE_TXP PIE_RXN GPP_TXP Y 0.U/0V_ GPP_RXP PIE_TXN_ 0.U/0V_ PIE_RXN W PIE_TXN T PIE_RXP GPP_RXN GPP_TXN Y U PIE_TXP_ T T PIE_RXN GPP_RXP GPP_TXP Y U PIE_TXN_ PIE_RXP GPP_RXN GPP_TXN Y PIE_TXP_ 0.U/0V_ PIE_RXP U PIE_TXP PIE_RXN GPP_RXP GPP_TXP V T PIE_TXN_ PIE_RXN U GPP_RXN GPP_TXN V 0 0.U/0V_ PIE_TXN PIE_S_N_RX0P PIE_S_N_RX0N PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN U GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN E GFX_RXP F GFX_RXN G GFX_RXP G GFX_RXN H GFX_RXP H GFX_RXN J GFX_RXP J GFX_RXN J GFX_RXP J GFX_RXN L GFX_RXP L GFX_RXN M GFX_RXP L GFX_RXN P GFX_RX0P M GFX_RX0N P GFX_RXP M GFX_RXN R GFX_RXP P GFX_RXN R GFX_RXP R GFX_RXN P GFX_RXP P GFX_RXN T GFX_RXP T GFX_RXN S_RX0P Y S_RX0N S_RXP Y S_RXN S_RXP S_RXN W S_RXP Y S_RXN PRT OF GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP E GFX_TXN E GFX_TXP F GFX_TXN F GFX_TXP F GFX_TXN F GFX_TXP H GFX_TXN H GFX_TXP H GFX_TXN H GFX_TXP J GFX_TXN J GFX_TX0P K GFX_TX0N K GFX_TXP K GFX_TXN K GFX_TXP M GFX_TXN M GFX_TXP M GFX_TXN M GFX_TXP N GFX_TXN N GFX_TXP P GFX_TXN P PIE I/F GFX PIE I/F S S_TX0P S_TX0N E S_TXP E S_TXN S_TXP S_TXN S_TXP S_TXN E PE_LRP(PE_LRP) PE_LRN(PE_LRN) RS0(RX0) _PEG_TX 0 _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# 0 _PEG_TX _PEG_TX# _PEG_TX0 0 _PEG_TX#0 0 _PEG_TX _PEG_TX# _PEG_TX 0 _PEG_TX# 0 _PEG_TX 0 _PEG_TX# 00 _PEG_TX _PEG_TX# 0 _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX0 _PEG_TX#0 _TX0P TX0N TXP TXN TXP_ 0 _TXN TXP TXN_ N_PIELRP N_PIELRN 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ R R 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX0 PEG_TX#0 PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX0 PEG_TX#0.K/F_ K/F_ PIE_N_S_TX0P PIE_N_S_TX0N PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN +.V PEG_RX#[:0] PEG_RX[:0] _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# To HMI ONN TO EPRESS R TO WLN TO PIE-LN TO TV TUNNER TO PIE R REER PEG_RX#[:0] PEG_TX#[:0] PEG_TX#[:0] PEG_RX[:0] PEG_TX[:0] PEG_TX[:0] lose to North ridge _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# RX0/RS0/RS0 difference table (PIE LINK) RS0 RX0/RS0 N_PIELRP R (GN).K (GN) RS0 isplay Port Support (muxed on GFX) GFX_TX0,TX,TX and TX P0 UX0 and HP0 GPP GPP N N GPP GPP P GFX_TX,TX,TX and TX UX and HP PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom RS0/RS0-PIE I/F / ate: Tuesday, February, 00 Sheet of

10 RX0: Powered from the.-v rail and driven by S00 LT_RST#, or S00 LT_RST# or _RST#. RS0: Powered from the.-v rail and driven by S00 LT_RST#, or S00 LT_RST# or _RST#. RX0 R *0_, PU_LT_RST# RS0 R0 0_ N_PLTRST# North ridge RESET +V RS0 only selects Loading of straps from EPROM : use default vaule, default 0 : I Master can load strap values from EEPROM if connected, or use default values if not connected RX0 --RS0_UX_L RS0 -- SUS_TT Enables ebug us acess through memory T/O pads and GPIO. 0 : Enable RS0, efault : isable RS0 (RS0 use VSYN#) Indicates if memory Side port is available or not 0: available RS0, efault : Not available RS0 ( RS0 use HSYN#) For extrnal EEPROM ebug only STRP_T Enables ebug us acess through memory T/O pads and GPIO. : Enable RX0, efault 0 : isable RX0 R R R VSYN_OM HSYN_OM N_RST#_IN.K_.K_.K_ RS0_UX_L R R S- el NGPP LK HTV_ET N_I_T N_I_LK R R R R RS0,,, RT_R RT_G RT_,, HSYN_OM,, VSYN_OM, T, LK RX0 RS0 RS0/RX0 0K/F_ *0K/F_ R0 K_ K_ *K_ +VG_N N_PWRG_IN NHT_REFLKP NHT_REFLKN +V Reserved only +V RX0 EXT_N_OS R0 for UM use 0 ohm +.V R R0 R R0 R R R R0 R R R *0_ *0/F_ *0_ *0/F_ *0_ *0/F_ *0_ *0_ *0_ *0_ */F_ +.V R RS0 RS0 R0.K_.K_ NGFX_LKP NGFX_LKN T T SLINK_LKP SLINK_LKN R *0_, EIT R *0_, EILK R *0_ HMI T R *0_ HMI LK K_ *K_ YN_PWR_EN RX0 -->N / RS V L LMPGSN(0,.)_ V- nalog not applicable to RX0 L LMPGSN(0,.)_ 0 0U/.V_ PLLV - Graphics PLL not applicable to RX0 +.V VPIEPLL -PIE PLL 0mils width L +.V_VPIEPLL LMPGSN(0,.)_ VHTPLL -HT LINK PLL +V_V_N +.V_VI_N +.V_VQ_N S- RT_R_ RT_G_ RT R 0_ T T +V_V_N 0.U/.V_ HSYN_INT VSYN_INT T_INT LK_INT _RSET_N +.V_PLLV +.V_PLLV +.V_VHTPLL +.V_VPIEPLL N_RST#_IN N_PWRG_IN N_LT_STOP# N_LLOW_LTSTOP NGFX_LKP NGFX_LKN NGPP_LKP NGPP_LKN SLINK_LKP SLINK_LKN +.V_PLLV.U/.V_.U/.V_ 0mils width L +.V_VHTPLL LMPGSN(0,.)_.U/.V_ NHT_REFLKP NHT_REFLKN R 0_ T N_REFLK_P N_REFLK_N N_I_T N_I_LK HTV_ET RS0_FT_GPIO0 RS0_FT_GPIO STRP_T RS0_UX_L +.V +.V +.V_PLLV +.V_VI_N LMPGSN(0,.)_ +.V_VQ_N L.U/.V_, L U F L_TP0 V(N) TXOUT_L0P(N) L_TP0 E L_TN0 V(N) PRT OF TXOUT_L0N(N) L_TN0 F L_TP VI(N) TXOUT_LP(N) L_TP G L_TN VSSI(N) TXOUT_LN(N) L_TN H L_TP VQ(N) TXOUT_LP(N) 0 L_TP H L_TN VSSQ(N) TXOUT_LN(G_GPIO0) 0 L_TN L_TP TXOUT_LP(N) T E L_TN _Pr(FT_GPIO) TXOUT_LN(G_GPIO) T F Y(FT_GPIO) F L_TP0 OMP_Pb(FT_GPIO) TXOUT_U0P(N) L_TP0 L_TN0 TXOUT_U0N(N) L_TN0 G L_TP RE(FT_GPIO0) TXOUT_UP(PIE_RESET_GPIO) L_TP G L_TN REb(N) TXOUT_UN(PIE_RESET_GPIO) L_TN E L_TP GREEN(FT_GPIO) TXOUT_UP(N) 0 L_TP F L_TN GREENb(N) TXOUT_UN(N) L_TN E L_TP LUE(FT_GPIO) TXOUT_UP(PIE_RESET_GPIO) T F L_TN LUEb(N) TXOUT_UN(N) T0 L_LK _HSYN(PWM_GPIO) TXLK_LP(G_GPIO) L_LK L_LK# _VSYN(PWM_GPIO) TXLK_LN(G_GPIO) L_LK# E L_LK _S(PE_TLRN) TXLK_UP(PIE_RESET_GPIO) L_LK F L_LK# _SL(PE_RLRN) TXLK_UN(PIE_RESET_GPIO) L_LK# G _RSET(PWM_GPIO) +.V_VLTP_N VLTP(N) PLLV(N) VSSLTP(N) PLLV(N) +.V_VLT N PLLVSS(N) VLT_(N) VLT_(N) H +V_VLT_N VHTPLL VLT_(N) VLT_(N) VPIEPLL E VPIEPLL VSSLT(VSS) VSSLT(VSS) SYSRESETb VSSLT(VSS) 0 POWERGOO VSSLT(VSS) 0 LTSTOPb VSSLT(VSS) 0 LLOW_LTSTOP VSSLT(VSS) E0 VSSLT(VSS) HT_REFLKP HT_REFLKN I RS0 only E REFLK_P/OSIN(OSIN) F I ISP_ON LVS_IGON(PE_TLRP) E R *0_ REFLK_N(PWM_GPIO) ISP_ON, LVS_LON LVS_LON(PE_RLRP) F R *0_ LVS_LON, T PST_PWM GFX_REFLKP LVS_EN_L(PWM_GPIO) G R *0_ PST_PWM, T GFX_REFLKN I/O U GPP_REFLKP U GPP_REFLKN I/O R *.K/F_ For RX0 only V R *.K/F_ GPPS_REFLKP(S_REFLKP) V GPPS_REFLKN(S_REFLKN) R I_T UM only TMS_HP0 I_LK MIS. TMS_HP(N) *0_ TMS_HP, TMS_HP _T/UX0N(N) HP(N) 0 T _LK/UX0P(N) SUS_STT#_N UXP(N) TVLKIN(PWM_GPIO) R 0_ SUS_STT# UXN(N) R_N_THRM THERMLIOE_P E 0 R_N_THRM STRP_T THERMLIOE_N T T G TEST_EN RSV TESTMOE R UX_L(N).K/F_ RS0(RX0) LMPGSN(0,.)_ R0 0_ PU_LT_STOP# PU_LT_REQ# PLLV - Graphics PLL not applicable to RX0.U/.V_.U/.V_ RT/TVOUT LOKs PM PLL PWR RS0 Q SS_NL/SOT RS0 Q SS_NL/SOT R 0_ LVTM VI- igital not applicable to RX0 VQ- andgap Reference not applicable to RX0 +.V R *0_ RX0 +.V +VG_N R.K_ +VG_N RS0 R.K_ RS0 +.V N_LT_STOP# N_LLOW_LTSTOP L L LMPGSN(0,.)_.U/.V_ LMPGSN(0,00M,)_.U/.V_ RX0 +.V RS0 0.U/0V_ +V +V +.V_VLTP_N VLTP - LVS or VI/HMI PLL not applicable to RX0 +.V_VLT N VLT - LVS or VI/HMI digital not applicable to RX0 R R 0_ L *0_ *LMPGSN(0,00M,)_ +V_VLT_N VLT - LVS or VI/HMI NLOG RS0 only +VG_N *.U/.V_ 0 PROJET : QT Quanta omputer Inc. LLOW_LTSTOP R *0_ RX0 N/R Size ocument Number Rev ustom RS0/RS0-SYSTEM I/F / Tuesday, February, 00 ate: Sheet of 0

11 UF E G G G H J R L L L L M N P R R R V U V V W W W W W Y E E E G E E J J K M L RX0/RS0 POWER IFFERENE TLE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 PIN NME VHT VHTRX RX0 +.V +.V RS0 +.V +.V PIN NME IOPLLV V RX0 N N RS0 +.V +.V PRT / GROUN VHTTX VPIE VG +.V +.V +.V +.V +.V +.V VI VQ PLLV N N N +.V +.V +.V VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT0 VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT0 VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS V_MEM VPIE V N +.V PLLV N +.V +.V VPIEPLL +.V +.V +.V VHTPLL +.V +.V +.V +.V E G G G H J L L L L M0 N P0 R R R R H0 U V W W W Y L M N P P R R T U U U V W W Y E0 K V_MEM VG N N +.V/.V +.V VLTP VLT N N +.V +.V IOPLLV N +.V VLT N N VHT - HT LINK digital I/O for RX0/RS0 VHTRX - HT LINK RX I/O for RX0/RS V L LMPGSN(0,00M,)_ +.V L *LMPGSN(0,00M,)_ +.V for VHTTX - HT - chip LINK TX I/O for bug, - RX0/RS0 can remove +.V +.V for RS0M 0. L LMPGSN(0,00M,)_ +.V for RS0M+S00 00m +.V L LMPGSN(0,00M,)_ VPIE - PIE TX stage.u/.v_ I/O for RX0/RS0 V - RS0 I/O transform +.V for RS0M+S00 +.V +.V.U/.V_ 0.U/.V_ L LMPGSN(0,00M,)_.U/.V_ 0.U/0V_.U/.V_ 0.U/0V_ R 0_ R 0_ V_MEM For UM RS0 only Not applicable to RX0 memory I/O transform 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.00 U/0V_ 0.00 U/0V_ +.V_VHT 0.U/0V_ +.V_VHTRX 0.U/0V_ +.V_VHTTX 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ +.V_VPIE 0 0.U/0V_ 0.U/0V_ +.V_VG_N +.V_V_MEM J K L M P R T H G F0 E E Y0 W V U T R P M J0 P0 K0 M0 L0 W H T0 R0 Y E U0 F G E UE VHT_ VHT_ PRT / VHT_ VHT_ VHT_ VHT_ VHT_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_0 VHTTX_ VHTTX_ VHTTX_ POWER VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_0 VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VG_(V_) VG_(V_) V_MEM(N) V_MEM(N) RS0(RX0) VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_0 VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) VG_(N) VG_(N) E F G H J K M L P R T V U K J U J K M L L M M N N P P P R R T T U T J E0 Y H H +.V_V_PIE 0.U/0V_ 0.U/0V_ 0.U/0V_ +.V_V_MEM 0.U/0V_ +V_VG 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0. U/0V_ 0 0.U/0V_ 0 0.U/0V_.V(0.) 0.U/0V_ R RS0.V(0.0) 0_ +V V -.V I/O 0.U/0V_ Not applicable to RX0 VPIE - PIE-E Main power R 0_.U/.V_ +.V V - ore Logic power +.V_YN 0U/.V_ 0 0U/.V_ L.U/.V_ V_MEM For UM RS0 only Not applicable to RX0 memory I/O transform +.V LMPGSN(0,00M,)_ PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom RS0/RS0-POWER/ ate: Tuesday, February, 00 Sheet of

12 PLE THESE PIE OUPLING PS LOSE TO U00 PV- Modified -- change to pull hi to VS for power leakage issue To RS0.KHZ R 0M_ 0 N_PLTRST# PIE_RST# R_PLTRST# LN_PLTRST# EPRESS_PLTRST# MINI_PLTRST# PIE_S_N_RX0P PIE_S_N_RX0N PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN PIE_S_N_RXP PIE_S_N_RXN PIE_N_S_TX0P PIE_N_S_TX0N PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN SSR_LKP SSR_LKN +.V +VS RT_X RT_X P/0V_ If PU have pull Hi,this pin should be not need 0 LLOW_LTSTOP PU_PROHOT# PU_PWRG,0 PU_LT_STOP#,0 PU_LT_RST# R R0 _ R _ R _ R _ R _ R0 RST#_S 0.U/0V RX0P_ 0.U/0V RX0N_ 0.U/0V RXP_ 0.U/0V RXN_ 0.U/0V RXP_ 0 0.U/0V RXN_ 0.U/0V RXP_ 0.U/0V RXN_ 0K/F_ PIE_N_S_TX0P PIE_N_S_TX0N PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN PIE_N_S_TXP PIE_N_S_TXN R /F_ PIE_LRP_S +.V_PIE_VR R.0K/F_ PIE_LRN_S +.V L LMPGSN(0,.)_ +.V_PIE_PV 0m PIE_PV-- PIE PLL POWER 0 0U/.V_ U/0V_ R *0M_ Y 00 P/0V_ R *0K/F_ SSR_LKP SSR_LKN R 0_ RT_X RT_X LLOW_LTSTOP PU_PROHOT# PU_PWRG PU_LT_STOP# PU_LT_RST# T N U _RST# V PIE_TX0P V PIE_TX0N V PIE_TXP V PIE_TXN U PIE_TXP U PIE_TXN T PIE_TXP T PIE_TXN U PIE_RX0P U PIE_RX0N U PIE_RXP V PIE_RXN R0 PIE_RXP R PIE_RXN R PIE_RXP R PIE_RXN T PIE_LRP T PIE_LRN P P PIE_PV RT XTL PU S00 Part of PI EXPRESS INTERFE N PIE_RLKP/N_LNK_LKP N PIE_RLKN/N_LNK_LKN P PU_HT_LKP M PU_HT_LKN M SLT_GFX_LKP M SLT_GFX_LKN J GPP_LK0P J GPP_LK0N L0 GPP_LKP L GPP_LKN M GPP_LKP M0 GPP_LKN PIE_PVSS K N_ISP_LKP K N_ISP_LKN M N_HT_LKP M N_HT_LKN 00MHZ N GPP_LKP P GPP_LKN L J J0 M_M_M_OS M_X M_X X X F LLOW_LTSTP F PROHOT# F LT_PG G LT_STP# G LT_RST# LP RT LOK GENERTOR PI LKS PI INTERFE S00 I TRL(P) S00 (SELFG) P/N : JL0T00 PILK0 PILK PILK PILK PILK PILK/GPIO PIRST# E0# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ0# REQ# REQ# REQ#/GPIO0 REQ#/GPIO GNT0# GNT# GNT# GNT#/GPIO GNT#/GPIO LKRUN# LOK# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO LPLK0 LPLK L0 L L L LFRME# LRQ0# LRQ#/GNT#/GPIO MREQ#/REQ#/GPIO SERIRQ RTLK INTRUER_LERT# VT P P P P T T N U P V T V U V V T W T R R R U U Y W V Y Y Y Y W U Y W Y U W W V E E E V E E G E H H J J H H V PI_LK_R PI_LK_R PI_LK_R PI_LK_R PIRST#_L PE_GPIO LKRUN#_R INTE# INTF# INTG# INTH# LP_LK0 LP_LK L0 L L L LFRME# LRQ0#_S LRQ#_S S_GPIO SERIRQ RT_LK INTRUER_LERT# +VT el R, R0, R, R on PV R _ PE_GPIO S_GPIO PIRST# ll the PI bus has build-in Pull-UP/own resistors RT_LK +VT U/0V_ SERR# SERR# SI- Modified-- for power leakage issue R 0_ RF_OFF# E GPIO# L_K LKRUN# PI_LK_TPM PI_LK PI_LK PI_LK PIRST# +VRT_ T T0 R change to 0 ohm on PV T INTH# LP_LK0 R _ LP_LK R 0_ PLK_LP_K0 L0, L, LFRME#, L, L, 0.P/0V_ T T0 T0 SERIRQ SI- Modified - for EMI 0MIL R R R *.K_ *00K/F_ +V 0MIL 0 +V R +VT SI- mofified for satify -- remove R0, add R,R /F_ el R for TP on PV +VT 0MIL R 0_ +VRT SI- Modified-- dd GPIO pin for control E wake up ( need low ms for Jmicron request) R 0_ R 0_ T R0 T0 T.K_ R G *SHORT_ P.K_ 0 U/0V_ *M/F_ 0 0.U/0V_ SI- Modified--reserve change, 0 type for PV P/0V_ 0MIL R00V-0 0 R00V-0 PLK_LP_EUG 0MIL 0MIL T T_ONN SI- modified -- for EMI suggestion INTRUER_LERT# Left not connected (Southbridge has 0-kohm internal pull-up to VT). +VRT_ +T PROJET : QT Quanta omputer Inc. +VPU R 0_ N/R Size ocument Number Rev ustom S00-PIE/PI/PU/LP / ate: Tuesday, February, 00 Sheet of

13 +VSUS N only,an't be install R *.K_ S_TEST0 +VSUS +VS +VS R0 R +V Z_SOUT Z_SYN Z_LK Z_RST# Z_SIN0_R Z_SOUT Z_SYN Z_LK Z_RST# S_TEST S_TEST *0K/F_ SWI# +V SL0/ST0 is V tolerance M datasheet define it R.K_ PLK_SM +VS R R PT_SM SL/ST is V/S tolerance M datasheet define it R R remove pull hi ( chip internal have pull hi ) S_SMLK S_SMT SL/ST is V/S tolerance M datasheet define it R R R G R *.K_ *.K_.K_ *.K_ *.K_ *.K_ *.K_.K_ *SHORT_ P.K_ S_SLK S_ST SUS_STT# SYS_RST# NSWON# To zalia R _ R0 _ R _ R _ R 0_ 0 To Modem oard R _ R _ R _ R _ 0 0 lock gen/robson/tv tuner /R/R thermal/ccelerometer *0P/0V_ RSMRST# SI- modified -- hange lan disable control from S to E S reserve T T, LN_ISLE#, PU_MEMHOT# PM_THERM# Z_SOUT_UIO Z_SYN_UIO *0P/0V_ IT_LK_UIO 0P/0V_ *0P/0V_ *0P/0V_ 0P/0V_ Z_RST#_UIO Z_SIN0 Z_SOUT_UIO_M Z_SYN_UIO_M IT_LK_UIO_M Z_RST#_UIO_M NEWR_ETET T T SUS# SUS# NSWON# S_PWRG_IN 0 SUS_STT# SI- modified add E function, Z_SPKR,,,, PLK_SM,,,, PT_SM GTE0 RIN# SI# KSMI# T0,, PIE_WKE# SWI# PU_THERMTRIP# W_PWRG Z_RST# *0_ RSMRST# Z_LK Z_SOUT Z_SIN0_R Z_SIN_R Z_SYN Z_RST# NEWR_ETET RI# SLP_S SUS# SUS# NSWON# S_PWRG_IN SUS_STT# S_TEST S_TEST S_TEST0 GTE0 RIN# SI# KSMI# GEVENT# SYS_RST# PIE_WKE# SWI# S_THERMTRIP# W_PWRG ST_IS LN_ISLE#_S S_NW_LK_REQ# Z_SPKR PLK_SM PT_SM S_SMLK S_SMT T T PM_TLOW# PM_TLOW# SES_INT T E_SI# E_SI# from Gevent# change to Gevent# on PV SI- Modified --for EMI suggestion S JTG T +VS +VS N R *0_ R 0_ SI- modified el T T0 R R R R R R R0 +VSUS *0_ PU_MEMHOT#_IN R *0_ SMLERT#_ R *0K/F_ S_JTG_TO S_JTG_TK S_JTG_TI S_JTG_RST# H audio interface is.s voltage K_ *0_ *0_ *0_ *0_ S_JTG_TK S_JTG_TO S_JTG_TI S_TEST S_JTG_RST# H_UX_RST# 0P/0V_ U E PI_PME#/GEVENT# E RI#/EXTEVNT0# H SLP_S/GPM# F SLP_S# G SLP_S# H PWR_TN# H PWR_GOO K SUS_STT# H TEST H TEST H TEST0 Y G0IN/GEVENT0# W KRST#/GEVENT# K LP_PME#/GEVENT# K LP_SMI#/EXTEVNT# F S_STTE/GEVENT# J SYS_RESET#/GPM# H WKE#/GEVENT# F LINK/GPM# J SMLERT#/THRMTRIP#/GEVENT# W N_PWRG RSMRST# US_O#/IR_TX/GEVENT# US_O#/IR_TX0/GPM# US_O#/IR_RX0/GPM# US_O#/IR_RX/GPM# E US_O#/GPM# F US_O#/GPM# E US_O0#/GPM0# S00 USP- USP+ H UIO SI- Modified -- discrete remove RP RP0 US O INTEGRTE u LOSE TO S S00 PI / WKE UP EVENTS E ST_IS0#/GPIO0 LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO W LK_REQ0#/ST_IS#/GPIO0 V LK_REQ#/ST_IS#/FNOUT/GPIO W0 LK_REQ#/ST_IS#/FNIN/GPIO0 W SPKR/GPIO SL0/GPO0# W S0/GPO# K SL/GPO# K S/GPO# 0 _SL/GPIO Y _S/GPIO LL#/GPIO Y SHUTOWN#/GPIO G R_RST#/GEVENT# M Z_ITLK M Z_SOUT J Z_SIN0/GPIO J Z_SIN/GPIO L Z_SIN/GPIO M Z_SIN/GPIO L Z_SYN M Z_RST# L Z_OK_RST#/GPM# H IM_GPIO0 H0 IM_GPIO H SPI_S#/IM_GPIO F IE_RST#/F_RST#/IM_GPO IM_GPIO E IM_GPIO E IM_GPIO IM_GPIO UM INTEGRTE u US MIS GPIO US. US.0 *0_PR_ Part of USLK/M_M_M_OS US_ROMP G US_FSP E US_FSN E US_FSP F US_FSN E US_HSP H US_HSN J0 US_HS0P E US_HS0N F US_HSP US_HSN US_HSP 0 US_HSN 0 US_HSP G US_HSN H US_HSP E US_HSN E US_HSP US_HSN US_HSP US_HSN US_HSP G US_HSN G US_HSP H US_HSN H US_HSP US_HSN US_HS0P US_HS0N IM_GPIO IM_GPIO IM_PWM0/IM_GPIO0 F SL/IM_GPIO S/IM_GPIO F SL_LV/IM_GPIO E0 S_LV/IM_GPIO E IM_PWM/IM_GPIO E IM_PWM/IM_GPO IM_PWM/IM_GPO E IM_GPIO G0 IM_GPIO G IM_GPIO0 IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO IM_GPIO IM_GPIO IM_GPIO 0 IM_GPIO 0 IM_GPIO 0 IM_GPIO 0 IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO USP_R- USP_R+ LK_M_US US_ROMP_S US_FSP US_FSN US_FSP US_FSN S_SLK S_ST S_SLK S_ST S_GPIO S_GPIO USP+ USP- USP0+ USP0- USP+ 0 USP- 0 USP+ 0 USP- 0 USP+ USP- USP+ 0 USP- 0 USP+ 0 USP- 0 USP+ USP- USP+ USP- USP+ 0 USP- 0 USP+ 0 USP- 0 USP0+ 0 USP0-0, SLK_WLN, ST_WLN R LK_M_US.K/F_ T0 T T T TV Min-ard WLN Min-ard US onnector US onnector NEW R FINGERPRINT LUETOOTH ocking S_GPIO S_GPIO SPI/LP define +VS +VS +V +V LK_M_US US card reader or Touch screen arama US E-ST and US onnector US onnector T T0 R K/0 Q N00EPT R K/0 N00EPT PLK_SM PT_SM *.P/0V_ for EMI & del R change.p Q PROJET : QT Quanta omputer Inc. Z_SIN_R R 0_ Z_SIN *S/W JTG EUG N/R Size ocument Number Rev ustom S00-PI/GPIO/US / ate: Tuesday, February, 00 Sheet of

14 ST PORT 0,,, can support HI mode ST ST O E-ST ST PORT, are only support IE mode ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 ST_TXP ST_TXN ST_RXN ST_RXP 0 ST_TXP 0 ST_TXN 0 ST_RXN 0 ST_RXP PLE ST_L RES VERY LOSE TO LL OF S00 NOTE: R IS K % FOR MHz XTL,.K % FOR 00MHz INTERNL LOK PLE ST OUPLING PS LOSE TO S00 R R T T T T T T T T0 T T T T R R K/F_ PLV_ST-- ST PLL POWER +V 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ ST_TXP0_ ST_TXN0_ ST_RXN0_ ST_RXP0_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_RIS_PN S_ST_LE# +V_XTLV_ST ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_X ST_X +V R 0K/F_ +.V_PLLV_ST XTLV_ST-- ST crystal power P/0V_./F_./F_ P/0V_ Y MHZ R 0M_ ST_X ST_X W U ST_TX0P E ST_TX0N 0 ST_RX0N 0 ST_RX0P E0 ST_TXP 0 ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP ST_TXP E ST_TXN ST_RXN ST_RXP E ST_TXP ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP V Y W ST_L ST_X ST_X ST_T#/GPIO PLLV_ST XTLV_ST S00 ST PWR SERIL T S00 Part of HW MONITOR SPI ROM T /00/ IE_IORY IE_IRQ IE_0 Y IE_ IE_ Y IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# Y IE_S# Y IE_0/GPIO IE_/GPIO IE_/GPIO E IE_/GPIO IE_/GPIO IE_/GPIO0 E0 IE_/GPIO 0 IE_/GPIO IE_/GPIO E IE_/GPIO 0 IE_0/GPIO 0 IE_/GPIO E IE_/GPIO IE_/GPIO IE_/GPIO E IE_/GPIO0 SPI_I/GPIO G SPI_O/GPIO SPI_LK/GPIO SPI_HOL#/GPIO F SPI_S#/GPIO F LN_RST#/GPIO U ROM_RST#/GPIO J FNOUT0/GPIO M FNOUT/GPIO M FNOUT/GPIO M FNIN0/GPIO0 P FNIN/GPIO P FNIN/GPIO R TEMP_OMM TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO VIN0/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO VIN/GPIO0 V VSS F G ROM_RST# S_FNOUT0 S_FNOUT S_FNTH0 S_FNTH PORT_0_PWR_WN TEMP_OMM TEMPIN0 TEMPIN M_THRM_S OR_I0 OR_I OR_I OR_I OR_I m +V_V_HWM *0.U/0V_ T T T T T T T T T T0 T IF THERE IS NO IE, TEST POINTS FOR EUG US T T IS MNTORY T T T T T T T0 T T T T T T T T00 T T T T0 R 0_ T T T R 0_ T0 T T T0 T0 T0 T0 T T_OFF# 0 HIPSET_PIE_SLOW_S# el R0 for TP on PV LE_EN T_OMO_EN# el WN off# and R on PV L 0_ *.U/.V_ +VS V--H/W monitor nalog power +VS SI- modified -- S internal pull Hi to VS, modified to same power rail with S R R R R0 R 0K/F_ *0K/F_ *0K/F_ *0K/F_ *0K/F_ OR_I0 OR_I OR_I OR_I OR_I SI- modified -- for fix +V power leakage in S mode R R R R R00 *0K/F_ *0K/F_ *0K/F_ *0K/F_ *0K/F_ ST_LE# U0 TSH0FU 0.U/0V_ SI- modified for ST LE fail issue S_ST_LE# +.V 0m) +.V_PLLV_ST L LMPGSN(0,.)_ +V L LMPGSN(0,.)_ U/0V_ m 0 0.U/0V_ m +V_XTLV_ST I I I I I0 X X X 0 0 X X X 0 X X X X X X X X X X UM discrete U/0V_ Place near ball PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom S00-PI/GPIO/US / ate: Tuesday, February, 00 Sheet of

15 +V el R for TP on PV 00U/.V_ +V +.V +.V L LMPGSN(0,.)_ +.V L LMPGSN(0,.)_.V : FLSH MEMORY MOE(EFULT).V: IE MOE R 0_ R For support US wakeup-->v_s +VS L LMPGSN(0,.)_ 0 0U/.V_ U/0V_ U/0V_ *0_ VQ--.V I/O power V_--.V IE I/O power.v flash memory I/O power PIE_VR--PIE I/O power V_ST--ST phy power 0U/.V_ VTX--US Phy nalog I/O power 0U/.V_ U/0V_ U/0V_ U/0V_ 0 U/0V_ U/0V_ U/0V_ +V_ 0 0 0U/.V_ U/0V_ U/0V_ U/0V_ U/0V_ 0 0U/.V_ 0.U/0V_ 0.U/0V_ +.V_PIE_VR m +.V_V_ST 0. U/0V_ 0U/.V_ 0.U/0V_ +V_V_US U/0V_ U/0V_ U/0V_ U/0V_ 0.U/0V_ 0. PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE. U L VQ_ M VQ_ T VQ_ U VQ_ U VQ_ U VQ_ V VQ_ W VQ_ Y VQ_ VQ_0 VQ_ VQ_ Y0 V V V E V S00 Part of PI/GPIO I/O P PIE_VR_ P PIE_VR_ P0 PIE_VR_ P PIE_VR_ R PIE_VR_ R PIE_VR_ R PIE_VR_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ E V_ST_ VTX_0 VTX_ VTX_ VTX_ VTX_ E VTX_ F VRX_0 F VRX_ F VRX_ G VRX_ G VRX_ G VRX_ IE/FLSH I/O -LINK I/O ST I/O PLL LKGEN I/O ORE S.V_S I/O ORE S0 POWER US I/O V_ L V_ M V_ M V_ N V_ P V_ P V_ R V_ R V_ T KV_.V_ L KV_.V_ L KV_.V_ L KV_.V_ L S_.V_ S_.V_ S_.V_ S_.V_ J S_.V_ J S_.V_ L S_.V_ L S_.V_ G S_.V_ G US_PHY_.V_ 0 US_PHY_.V_ 0 V_VREF VK_.V VK_.V V E J K E V-- S/ ORE power +.V_V_S_R +VLW_R V_US_PHY_R +V_VREF +V_VK +.V_VK m +V_V m 0.0 m m 0m KV_.V-- Internal +.V_KV clock Generator I/O power m 0.U/.V_ 0.U/0V_ 0.U/0V_ S_.--.v standby power 0 0.U/0V_ 0 0.U/0V_ hange to 00 V_VREF--PI V TOLERNE R U/0V_ U/0V_ U/0V_ U/0V_ U/0V_ 0.U/0V_ 0U/.V_ R0 0_ 0U/.V_ R 0_ +VS +V +V +.V_S +.V_S +.V L +.V LMPGSN(0,.)_ S_.V--.V standby power 0 0.U/0V_ K/F_.U/.V_ H0H-0PT R0 *0_ el R for TP on PV For S00 issue(/) - chip bug use - chip can remove UE S00 VSS_ VSS_ VSS_ VSS_ T0 VSS_ST_ VSS_ U0 VSS_ST_ VSS_ U VSS_ST_ VSS_ U VSS_ST_ VSS_ V VSS_ST_ VSS_ V VSS_ST_ VSS_0 W VSS_ST_ VSS_ Y VSS_ST_ VSS_ Y VSS_ST_ VSS_ Y VSS_ST_0 VSS_ Y VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_0 VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ E VSS_ST_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_0 VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ E VSS_US_0 VSS_ F VSS_US_ VSS_ F VSS_US_ VSS_0 G VSS_US_ VSS_ H VSS_US_ VSS_ H VSS_US_ VSS_ J VSS_US_ VSS_ J VSS_US_ VSS_ J VSS_US_ VSS_ J VSS_US_ VSS_ J VSS_US_0 VSS_ K0 VSS_US_ VSS_ K VSS_US_ VSS_0 K VSS_US_ K VSS_US_ PIE_K_VSS_ PIE_K_VSS_0 PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ H PIE_K_VSS_ PIE_K_VSS_ J PIE_K_VSS_ PIE_K_VSS_ J PIE_K_VSS_ PIE_K_VSS_ K PIE_K_VSS_ PIE_K_VSS_ M PIE_K_VSS_ PIE_K_VSS_ M PIE_K_VSS_ PIE_K_VSS_ M PIE_K_VSS_ PIE_K_VSS_0 P PIE_K_VSS_ PIE_K_VSS_ F VSS GROUN Part of VSSK F0 G H K K K L L L0 L L L L M M0 M M M N N N P P P0 P P P R R R R R0 R R T T T U U V Y E E P R R T U U0 V V0 V W W W W L U/0V_ U/0V_ U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ S00 S00 +.V_S R 0_ 0 0.U/0V_ 0.U/0V_ 0U/.V_ +.V_US_PHY_R US_PHY_.V--US Phy digital power +VS L0 LMPGSN(0,.)_ 0.U/0V_ 0 0U/.V_ +V_V V--US nalog PLL power +.V L LMPGSN(0,.)_ +.V_VK VK_.--US Phy digital power 0.U/.V_ +V +V_VK L LMPGSN(0,.)_ VK_.--nalog system PLL power.u/.v_ PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom S00-PWR/EOUPLING / ate: Tuesday, February, 00 Sheet of

16 OVERLP OMMON PS WHERE POSSILE FOR UL-OP RESISTORS. It must ready refore RSMRST# REQUIRE STRPS +VS +V +V +VS R 0K/F_ R 0K/F_ R00 *0K/F_ intermal have pull Hi 0K, confirm M ward this pull Hi not need S_GPIO S_GPIO R.K_ SI- Modified -R change from 0kohm to.kohm for fix system can not boot PI_LK_TPM PI_LK PI_LK PI_LK LP_LK0 LP_LK RT_LK Z_RST# GPIO R *.K_ R.K_ GPIO R 0K/F_ R 0K/F_ R *0K/F_ R *0K/F_ R 0K/F_ R 0K/F_ R 0K/F_ TYPE GPIO GPIO PULL HIGH PI_LK_TPM OOTFIL TIMER ENLE PI_LK USE EUG STRPS PI_LK RESERVE PI_LK RESERVE LP_LK0 IM ENLE LP_LK LKGEN ENLE RT_LK INTERNL RT EFULT Z_RST# ENLE PI ROM OOT FWH LP SPI L :.K pull down N L :.K pull down L :.K pull down L :.K pull down N PULL LOW OOTFIL TIMER ISLE EFULT IGNORE EUG STRPS EFULT IM ISLE EFULT LKGEN ISLE EFULT EXT. RT (P on X, apply KHz to RT_LK) ISLE PI ROM OOT EFULT RSV N N EUG STRPS S00 HS K INTERNL PU FOR PI_[:] SI- modified -- confirm M R need to stuff N_PWRG_IN: RS0/RX0 =.V; RS0 =.V o NOT share it with S_PWRG when use Internal lk Gen (Need S PLL initialize firstly) R *.K_ R *.K_ R *.K_ R *.K_ R *.K_ R *.K_ SI- modified -- remove +V pull Hi resistor. Use.K P. +VS 0 VRM_PWRG, EPWROK R 0K/F_ R 0_ *.U/.V_ H0H-0PT H0H-0PT S_PWRG_IN +.V U N V *0.U/0V_ GN Y R *_ *NLSZFTG SOT- +.V S_PWRG_IN R 0K/F_ RX0,RS0 N_PWRG_IN R N_PWRG_IN 0 *0K/F_ +.V N/S POWER GOO IRUIT 0_ R W_PWRG PI_ PI_ PI_ PI_ PI_ PI_ PULL HIGH USE LONG RESET EFULT USE PI PLL EFULT USE PI LK EFULT USE IE PLL EFULT USE EFULT PIE STRPS EFULT RESERVE PULL LOW USE SHORT RESET YPSS PI PLL YPSS PI LK YPSS IE PLL USE EEPROM PIE STRPS LSZ000 LUG000 I(P) NLSZFTG(SOT-) I OTHER(P) SNUGVR(SOT-) SOT- SOT- PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom S00-STRPS ate: Tuesday, February, 00 Sheet of

17 I TRL(P) (G) VG P/N : J0000T00 PEG_TX0 PEG_TX#0 PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX#.Gb/s bit rate PEG_TX0 PEG_TX#0 PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# W0 W W V V V0 U U0 P0 P PIE_RX0P PIE_RX0N PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PRT OF P I - E X P R E S S I N T E R F E PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN Y Y Y Y V V V V T T T T P P _PEG_RXP0 _PEG_RXN0 _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN _PEG_RXP _PEG_RXN U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PEG_RX0 PEG_RX#0 PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# POWER +PIE_VR=.V +V_MEM.V=.V +VG_ORE=.0~.V - MS,MS 0.~.V - MS PEG_TX PEG_TX# PEG_TX PEG_TX# P N PIE_RXP PIE_RXN PIE_TXP PIE_TXN P P _PEG_RXP _PEG_RXN 0.U/0V_ 0.U/0V_ PEG_RX PEG_RX# PEG_TX0 PEG_TX#0 PEG_TX0 PEG_TX#0 N N0 PIE_RX0P PIE_RX0N PIE_TX0P PIE_TX0N M M _PEG_RXP0 _PEG_RXN0 0.U/0V_ 0.U/0V_ PEG_RX0 PEG_RX#0 PEG_TX PEG_TX# PEG_TX PEG_TX# M M0 PIE_RXP PIE_RXN PIE_TXP PIE_TXN M M _PEG_RXP _PEG_RXN 0 0.U/0V_ 0.U/0V_ PEG_RX PEG_RX# PEG_TX PEG_TX# PEG_TX PEG_TX# K0 K PIE_RXP PIE_RXN PIE_TXP PIE_TXN L L _PEG_RXP _PEG_RXN 0.U/0V_ 0.U/0V_ PEG_RX PEG_RX# PEG_TX PEG_TX# PEG_TX PEG_TX# K J PIE_RXP PIE_RXN PIE_TXP PIE_TXN L L _PEG_RXP _PEG_RXN 0 0.U/0V_ 0.U/0V_ PEG_RX PEG_RX# PEG_TX PEG_TX# PEG_TX PEG_TX# J J0 PIE_RXP PIE_RXN PIE_TXP PIE_TXN J J _PEG_RXP _PEG_RXN 0.U/0V_ 0.U/0V_ PEG_RX PEG_RX# PEG_TX PEG_TX# PEG_TX PEG_TX# H H0 PIE_RXP PIE_RXN PIE_TXP PIE_TXN G G _PEG_RXP _PEG_RXN 0 0.U/0V_ 0.U/0V_ PEG_RX PEG_RX# EXT_GFX_LKP EXT_GFX_LKN PIE_RST# EXT_GFX_LKP EXT_GFX_LKN 00MHz (+/-00ppm) input frequency, 0-0.V single-ended swing R 0_ 0 G lock PIE_REFLKP PIE_REFLKN SM US N_SMLK N_SMT PERST alibration PIE_LRN PIE_LRP N_ N_ F E E H0 M_PIE_LRN M_PIE_LRP R K/F_ R0.K/F_.K for M-S +.V_PIE_V M-S/M-S U VG ore VG ore PP V +.V +.V +.V PIE_VR PIE_PV VR.V_elay VR 0ms 0ms N/R PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom MX/MX_PIE_Interface ate: Tuesday, February, 00 Sheet of

18 +.V +.V GPIO JMOE ROMS# GPIO(ROMS#) P without external VIOS ROM EN TEMP_FIL +.V EVG-XTLI EVG-XTLO N- MS,MS P K- MS N - M/M, M EN- M EN(0K P)- M N- MS,MS PU to.v- MS MEM_I[:0] Vendor Type Vendor P/N 0000 Qimonda (Infineon) * HYTF- 000 Qimonda (Infineon) *-00MHZ HYTF Hynix * HYPSFP- 00 Hynix *-00MHZ HPSFFR-0L 000 Samsung * KNQG-Z 00 Samsung *-00MHZ KNQG-H0 00 Reserved 0 Reserved 000 Reserved 00 Reserved 00 Reserved 0 Reserved 00 Reserved 0 Reserved 0 Reserved Reserved H M M L L H PWRNTL PWRNTL0 V-ORE 0 0 EN R R Y L=0PF *MHZ P 0.V 0 0 V-ORE PLL_PV Phase Lock Loop Power edicated analog power pin for display PLLs.. V ± % PIE_PV PI-E PLL power.. V ± % 0K/F_ 0K/F_ +.V +VG_ORE L MPV Memory Phase Lock Loop Power Same as V PLL_V Phase Lock Loop Power edicated digital power pin for display PLLs.. V ± % R00 R L *P/0V_ *P/0V_ K/F_ 0K/F_.0V.0V 0.V LMPGSN(0,.)_ L LMPGSN(0,.)_ L R *0M_ 0U/.V_ LMPGSN(0,.)_ LMPGSN(0,.)_ 0U/.V_ 0 0U/.V_.V(0m) U/0V_.V(00m) U/0V_ For Int lk Mhz 0U/.V_ U/0V_ 0.V(0m) 0, GFX_ORE_NTRL0 OS_SPRE TEMP_FIL GFX_ORE_NTRL EN 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ +VR GPIO0 GPIO T T T GPIO LVS_LON GPIO GPIO T GPIO GPIO GPIO T +V EVG-XTLI HP R 0_ +.V.V+R0(R)=.V/=0.V T R /F_ R V(m) T /F_ PSYN Memory I R 0K/F_ R *0K/F_ R *0K/F_ R *0K/F_ R 0_ R 0_ R T T T T 0K/F_ K/F_,, MEM_I0 MEM_I MEM_I MEM_I GPIO0 GPIO GPIO GPIO GPIO GPIO EXT_LVS_LON GPIO GPIO GPIO0 GPIO GPIO GPIO HMI_HP OS_SPRE VG_LERT TEMP_FIL PWRNTL_ EN ROMS# GPIO LKREQb GPIO JMOE GENERI +.V_PLL_PV PLL_PVSS +.V_VPIE_PV EVG-XTLI EVG-XTLO PSYN +0.V_M_VREFG +VGORE_MPV MPVSS +.V_PLL_V MLK MT R VTHM_LK VTHM_T +V_ELY J J L K L K K L E K L V V W W Y Y Y F G H G H H J J J K K Y V V V U U T T T T R R R P P N N P P P P V N Y M M M M L Y Y V H G H G H E J J0 H U TXM_P0P TXP_P0N TX0M_PP TX0P_PN TXM_PP TXP_PN TXM_PP TXP_PN VLI PSYN_NEW VPNTL_MVP_0 VPNTL_MVP_ VPNTL_0 VPNTL_ VPNTL_ VPLK VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_0 VPT_ VPT_ VPT_ M-S/M-S R 0_ R 0_ R R R *0_ *0_ 0K/F_ PRT OF INTEGRTE TMS/P PORT EXT TMS VO GPIO_0 GPIO_ GPIO_ GENERL GPIO_ PURPOSE GPIO_ I/O GPIO_ GPIO_ GPIO LON GPIO ROMSO GPIO ROMSI GPIO_0_ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL0 GPIO SSIN GPIO THERML_INT GPIO HP GPIO TF GPIO_0_PWRNTL GPIO EN GPIO ROMS GPIO LKREQ GPIO JMOE GPIO TI GPIO TK GPIO TMS GPIO TO GEN_ GEN_ GEN_ GEN HP GEN_E VREFG PLL_PV PLL_PVSS PIE_PV MPV MPVSS PLL_V XTLIN XTLOUT TESTEN PLLTEST PLL & XTL TEST / RT (TV/RT) SERIL USES THERML TXM_P0P TXP_P0N TX0M_PP TX0P_PN TXM_PP TXP_PN TXM_PP TXP_PN P_VSSR_ P_VSSR_ P_VSSR_ P_VSSR_ P_VSSR_ MLK MT P_PV P_PVSS P_PV P_PVSS P_VR_ P_VR_ P_VR_ P_VR_ P_VSSR_ P_VSSR_ P_VSSR_ P_VSSR_ P_VSSR_ P_LR VG_LERT HP R R G G HSYN VSYN RSET V VSSQ VI VSSI R R G G Y OMP VSYN HSYN V VQ VSSQ VI VSSI RSET SL S T LK T LK T_P_UXN LK_P_UXP T_P_UXN LK_P_UXP TS_FO PLUS MINUS VGTHRM+ VGTHRM- TX0_HMI_L- TX0_HMI_L+ TX_HMI_L- TX_HMI_L+ +.V_TPV P_PV P VR P VR P_VSSR_ TMS_HP L_RT_R L_RT_G L_RT_ +.V_V_Q +V _VSY _HSY +.V_V_Q VGTHRM- TX_HMI_L- TX_HMI_L+ TX_HMI_L- TX_HMI_L+ Thermal Sensor K L J J0 L0 K0 L K L K E F J J K L L K J H H J F G J H G L K L K L K K K0 J L H J J L K L K L K J J J E F H H G F E G J H F H F G E E E SMLK SMT -LT GN R R G-P@EV I RESS: H Remove 0R SHUNT RESISTOR for M-S from M Jackson confirm L_RT_R L_RT_G L_RT_ +V 0.U/0V_ 0 OHM +.V_V_Q -_V +.V_TPV P_PV P VR P VR ENLE H UIO ( MX-M ) M-S R 0_ el R0, R, R0, R, R, R, R for TP on PV U0 V XP XN -OVT /F_ /F_ T T R -VGTHRM R TMS_HP +V R VTHM_T VTHM_LK R0 HMI_S HMI_SL *0_ R 0/F_ R 0_ R 0/F_ R 0_ 0 VGTHRM+ 00P/0V_ +V VIP_ TX_HMI_L- TX_HMI_L+ TX0_HMI_L- TX0_HMI_L+ TX_HMI_L- TX_HMI_L+ TX_HMI_L- TX_HMI_L+ P_PV / P_PV P/TMS PLL Power (Link ) P/TMS PLL Power (Link ). V ± % P_VR / P_VR P/TMS Transmitter Power (Link ) P/TMS Transmitter Power (Link ). V ± % R *00K/F_ R 0/F_ R 0_ R0 +V_ELY V tolerance --,,S/SL V tolerance --, +V_ELY w/s 0 / 0 +V_ELY VIP_ TMS_HP 0, RT_R 0, RT_G 0, RT_ 0, HSYN_OM 0,, VSYN_OM 0,, +.V_V_Q V nalog Power 0.U/0V_ edicated power for.. V ± % VI +.V_V_Q igital Power.. V ± % +.V_V_Q V nalog Power.. V ± % VQ 0.U/0V_ U/0V_ and Gap (clean) power supply.. V ± % T T0 00/F_ *.K_ *.K_ 0.U/0V_ 0K/F_ 0.U/0V_ VI igital Power.. V ± % 0.U/0V_ +V_ELY el L for TP on PV EILK 0, el R, R, EIT 0, R, R T 0, for TP on PV LK 0, +V_ELY el R, R, R, R, R, R for TP on PV +V +.V_TPV P VR P_PV P VR P_PV 0.U/0V_ 000P/0V_ +V 0 0.U/0V_ U/0V_ +.V_TPV 0 0.U/0V_ 000P/0V_ 0 0.U/0V_ 000P/0V_.V(m) L +.V LMPGSN(0,.)_ 0U/.V_.V(0m) L +.V LMPGSN(0,.)_ 0U/.V_.V(00m) L +.V LMPGSN(0,.)_ 0U/.V_.V(0m) L0 +.V LMPGSN(0,.)_ 0U/.V_.V(S00,00m) L0 +.V LMPGSN(0,.)_ 0U/.V_ PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom MX/MX_Main Tuesday, February, 00 ate: Sheet of

19 UE PIE_VSS_ PIE_VSS_ PIE_VSS_ PIE_VSS_ E PIE_VSS_ E0 PIE_VSS_ E PIE_VSS_ F PIE_VSS_ G PIE_VSS_ G PIE_VSS_0 G0 PIE_VSS_ G PIE_VSS_ H PIE_VSS_ J PIE_VSS_ J PIE_VSS_ L PIE_VSS_ L PIE_VSS_ L0 PIE_VSS_ L PIE_VSS_ M PIE_VSS_0 M PIE_VSS_ P PIE_VSS_ R PIE_VSS_ R0 PIE_VSS_ R PIE_VSS_ T PIE_VSS_ U PIE_VSS_ V PIE_VSS_ Y PIE_VSS_ Y PIE_VSS_0 Y0 PIE_VSS_ Y PIE_VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_ VSS_ VSS_ VSS_ VSS_ 0 VSS_0 VSS_ VSS_ VSS_ E VSS_ L VSS_ VSS_ F VSS_ F VSS_ VSS_0 VSS_ E VSS_ G VSS_ E VSS_ H VSS_ K VSS_ K VSS_ J VSS_ L VSS_ L0 VSS_0 VSS_ VSS_ Part of VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_00 VSS_0 VSS_0 PI-Express GN ORE GN M-S/M-S J F F F F F F F0 F F F F F G G H J J J K L L L L L M M M M0 M P P P P P R R R0 T U U U U U E0 V V V0 P V W Y Y Y Y Y M.V -(00m) +.V L LMPGSN(0,.)_ +LVR_- UF 0 PRT OF R 0K/F_ 0 U/0V_ U/0V_ 0.U/0V_ F0 VRY_L 0_ R LVR_ PST_PWM 0, G0 LVR_ ontrol IGON ISP_ON 0,.V(00m) 0_ R0 +.V L LMPGSN(0,.)_ +.V_LV J LVS channel LV_ H0 LV_ TXLK_UP EXT_TXULKOUT+ EXT_TXULKOUT- TXLK_UN E EXT_TXUOUT0+ U/0V_ U/0V_ U/0V_ TXOUT_U0P J TXOUT_U0N J EXT_TXUOUT0- F LVSSR_ TXOUT_UP K EXT_TXUOUT+ F LVSSR_ TXOUT_UN L EXT_TXUOUT- L LVSSR_ TXOUT_UP EXT_TXUOUT+ LVR J LVSSR_ TXOUT_UN H EXT_TXUOUT- LVS Output river nalog Power Supply J LVSSR_ TXOUT_UP G. V ± % K LVSSR_ TXOUT_UN H K LVSSR_ K LVSSR_ TXLK_LP L EXT_TXLLKOUT+ LV J LVSSR_ TXLK_LN K EXT_TXLLKOUT- LVS Output river igital Power Supply L LVSSR_0 TXOUT_L0P J0 EXT_TXLOUT0+. V ± % L LVSSR_ TXOUT_L0N J EXT_TXLOUT0- TXOUT_LP K0 EXT_TXLOUT+ +.V_TPV TXOUT_LN EXT_TXLOUT- LPV TXOUT_LP K EXT_TXLOUT+ nalog Power for.v(0m) TXOUT_LN L EXT_TXLOUT- transmitter PLL. It should G LPV TXOUT_LP K H be a power for the PLL LPVSS TXOUT_LN L block of the macro.. V ± % 00P/0V_ U/0V_ 0.U/0V_ M-S/M-S PIN GPIO0 GPIO GPIO VIP GPIO HSYN GPIO IOSROM ONFIGURTION STRPS ESRIPTION OF EFULT SETTINGS PIE FULL TX OUTPUT SWING PIE TRNSMITTER E-EMPHSIS ENLE llows eitherpie.gt/s or GT/s operation ENLE H UIO ( MX-M ) ENLE H UIO ( M-S ) ENLE HMI Memory perture size M M M M M G G G GPIO GPIO GPIO ROMIFG ROMIFG ROMIFG M-S 0 0 REV 0,, HSYN_OM 0,, VSYN_OM GPIO0 GPIO GPIO VIP_ GPIO PSYN GPIO GPIO GPIO GPIO GPIO0 GPIO GPIO VIP_ GPIO SI- Modified -- follow M reference schematic change for reduce leakage to VR US GPIO GPIO GPIO GPIO R R R R R R R R R0 R R R0 *0K/F_ *0K/F_ *0K/F_ *0K/F_ 0K/F_ 0K/F_ *0K/F_ *0K/F_ +V_ELY *0K/F_ *0K/F_ *0K/F_ 0K/F_ +V_ELY It is a shared pin strap with ONFIG[:0] if IOS_ROM_EN is set to 0. PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom MX/MX_GN / LVS/ Straps ate: Tuesday, February, 00 Sheet of

20 0,,,,,,,,,, MINON HWPG V_T -- Level translation between core and I/O, excluding memory receivers.. V ± % +V V_R --IO power for. V pins (e.g. GPIO s).. V ± % R +.V +.V.K_ *H0H-0PT L-F R R 00K/F_ H0H-0PT *K/F_ VR-- I/O power for the memory interface on M. V ± % Q O0 0.U/0V_.V(.).V(0m) +.V_V_T LMPGSN(0,.)_ P-MOS,. +.V +.V Gated.V 0m by V +.V +V_ELY +VR +.V L LMPGSN(0,.)_ SI- Modified -- follow M reference schematic change./.v 0m +VR L LMPGSN(0,.)_ V_R -- Power for VPT_[:] - external TMS or GPIO; corresponds to VO_MS_VMOE register bit; '' -. V(default); '0' -. V;. V ± % or. V ± % V_R -- Power for VP control pins (VPNTL_[0-] and VPLK) and VPT_[:0] - external TMS or GPIO; corresponds to VO_LS_VMOE register bit; '' -. V(default); '0' -. V;. V ± % or. V ± % L 0 0U/.V_ Q N00E L0 0U/.V_ 0U/.V_ L0 0.U/0V_ 0U/.V_ 0U/.V_ 0.U/0V_ 0U/.V_ *0U/.V_ *0U/.V_ LMPGSN(0,.)_ U/0V_ +.V_V_T +V_ELY U/0V_ U/0V_ 0.U/0V_ U/0V_ 0 U/0V_ LMPGSN(0,.)_ +.V_VRH_ 0U/.V_ 0.U/0V_ 0.U/0V_ +VG_ORE 00 U/0V_ 0.U/0V_ 000P/0V_ U/0V_ +.V_VRH_ N -0.V 00m +VP./.V 0m 0 U/0V_ 0.U/0V_ 0 U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ U VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ H VR_ H VR_0 H VR_ H VR_ H VR_ H VR_ H0 VR_ H VR_ VR_ M VR_ V_T_ Y V_T_ V V_T_ T V_T_ J V_T_ J0 V_T_ J V_T_ L V_T_ M-S/M-S VR_ VR_ VR_ VR_ F VR_ F VR_ E VR_ E VR_ M RSV_ M RSV_ L RSV_ RSV_ 0 VRH_ VRH_ 0 VSSRH_ VSSRH_ V N_ U N_ R P_ P P_ *LMPGSN(0,.)_ L Q N00E 0.U/0V_ +VG_ORE +VP I/O Internal Memory I/O lock PRT OF P O W E R Memory I/O ack ias PI-Express ore SI- modified -- power play function Q ME0T +.V PIE_VR_ F0 PIE_VR_ F PIE_VR_ F PIE_VR_ F PIE_VR_ F PIE_VR_ G PIE_VR_ G0 PIE_VR_ G PIE_V_ PIE_V_ PIE_V_ PIE_V_ E PIE_V_ E PIE_V_ E PIE_V_ L PIE_V_ M PIE_V_ P PIE_V_0 T PIE_V_ V PIE_V_ Y V_ L V_ L V_ L V_ L0 V_ M V_ M V_ M V_ M V_ 0 V_0 P V_ P V_ P0 V_ R V_ R V_ R V_ R V_ 0 V_ U V_ U V_0 U0 V_ V V_ V V_ V V_ V V_ Y V_ Y V_ Y V_ Y0 V_ V_0 V_ V_ V_ P VI_ J VI_ J VI_ J VI_ J PIE_VR--PI-E I/O power.. V ± % +.V_PIE_VR.V(00m) +.V_PIE_VR L LMPGSN(0,.)_ 0 *0.U/0V_ U/0V_ 0U/.V_ +.V_PIE_V 0.U/0V_ 0.U/0V_ +.V_PIE_V V+VI +VG_ORE 0.~.V( peak )( Ripple <.mv) U/0V_ 0 U/0V_ U/0V_ U/0V_ 0.U/0V_ U/0V_ U/0V_ U/0V_ U/0V_ 0.U/0V_ U/0V_ U/0V_ U/0V_ U/0V_ U/0V_ +VI U/0V_ U/0V_ 0 U/0V_ U/0V_ 00 U/0V_ U/0V_ 0U/.V_ P -- onnect to VP back bias regulator / generator. If back bias is not used, connect directly to V. ack ias Enabled: (GPIO EN =. V):. V or. V ack ias isabled: (GPIO EN = 0 V): V +.V +.V.V(.0) L LMPGSN(0,.)_ PIE_V--PI-E 0U/.V_ igital Power Supply (Either.0 V or. V).0 V -% to. V +% 0U/.V_ 0U/.V_ 0 0U/.V_ V--edicated core power, provides power to the internal logic. 0. V -. V (± %) L +VG_ORE LMPGSN(0,.)_ VI--Isolated (clean) 0U/.V_ core power for the l/o logic. Voltage level should match that of V. POWER Same as V VRH_ & VRH_ --edicated power pins for memory clock pads for each channel. Should have the same voltage level as VR. EN R 00K/F_ +V Q N00E PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom MX/MX_Power_and_N ate: Tuesday, February, 00 Sheet 0 of

21 OT 0 S#_0 OT0 WE# QS[..0] LK0 LK0# LK LK# M[..0] M[..0] QM#[..0] KE0 WE0# S# S0#_0 RS0# QS#[..0] RS# S0# KE MVREF MVREFS _ LK0# M M M M M M M0 M M M0 M M M M M M M M M M M M M M0 M M M M M M M0 M M M M M M M M M M0 M M M M M M0 M M M M M M M M M M M M M M M M M0 OT OT0 S# QM# QM# QM# QM# QM# QM# M M M QM# QM#0 M0 M M M M RS# M M M M M0 QS# QS# QS# QS# QS#0 _ QS# S#_0 QS# QS# QS QS QS0 QS QS WE# LK# LK0 QS QS QS KE0 RS0# WE0# S0# LK _0 S0#_0 KE LK0 LK0# LK LK# S0#_0 S#_0 QS#[..0] QS[..0] QM#[..0] M[..0] M[..0] _0 _ OT0 OT RS0# RS# S0# S# WE0# WE# KE0 KE _ +.V +.V +.V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N/R MX/MX/MEM_Interface Tuesday, February, 00 hange MEMTEST to 0 % ohm to GN, M update SI- modified -- for support Gbit VRM ( M X ) R 00/F_ R 00/F_ R 00/F_ 0.U/0V_ R.K_ 0.U/0V_ R 0/F_ Part of MEMORY INTERFE write strobe read strobe U M-S/M-S Q_0 E Q_ E0 Q_ E Q_ Q_ Q_ Q_ 0 Q_ Q_ E Q_ Q_0 E Q_ Q_ G Q_ G Q_ E Q_ Q_ Q_ Q_ Q_ Q_0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ 0 Q_ 0 Q_0 0 Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_ Q_0 G Q_ E Q_ Q_ G Q_ G Q_ F Q_ G Q_ F Q_ Q_ Q_0 Q_ Q_ E Q_ F Q_ F Q_ F Q_ G Q_ G Q_ H Q_ H Q_0 K Q_ L Q_ L Q_ L M_0 M_ M_ M_ E M_ M_ M_ M_ G M_ E M_ M_0 M_ M_ M_ G M_0 QMb_0 0 QMb_ G QMb_ QMb_ QMb_ QMb_ QMb_ QMb_ K QS_0 0 QS_ QS_ QS_ QS_ QS_ E QS_ E QS_ J QS_0 QS_ E QS_ QS_ QS_ QS_ QS_ E QS_ J OT0 E0 LK0 LK0b RS0b G0 S0b 0 S0b_0 E S0b_ G KE0 WE0b M_ MVREF F0 MVREFS F RM_RST J TEST_MLK L TEST_YLK L MEMTEST J LKb LK Sb E RSb KE G WEb 0 Sb_0 G Sb_ E OT R 00/F_ R0.K_ R0.K_

22 QS#0 QS0 QM#0 M M M0 M M M M M QM# S0#_0 WE0# M M M0 M M M M M M0 M M M LK0 KE0 LK0# OT0 QM# KE0 QS# M M M0 M M M M M M0 M M M LK0 LK0# OT0 QS RS0# M M M M M0 M M M M M M M M0 M M M LK0 LK0# S0#_0 RS0# S0# M 0 M 0 WE0# S0# QS# QS M_VREF M M M M M M M0 M QM# QS QS# WE# RS# M M M0 M M M M M M0 M M M 0 M 0 LK# LK OT KE M[..0] M[..0] QM#[..0] QS[..0] QS#[..0] LK# S#_0 S# QS# QS QM# QM# OT KE WE# S#_0 RS# S# QS# QS M M M M M M M M M M M M M M M0 M M_VREF M_VREF QS WE# M M M M M0 M LK M QS# M M M LK M0 OT RS# M M M KE M LK# M QM# S# S#_0 M M _0 M M M QM# M_VREF M M0 M QS# M0 _ QS M M M M S0# S0#_0 OT0 RS0# WE0# KE0 LK0 LK0# _0 _ QM#[..0] M[..0] M[..0] LK LK# OT RS# S# WE# S#_0 KE QS#[..0] QS[..0] WE0# KE0 S0# RS0# S0#_0 OT0 +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V +.V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N/R MX/MX/VRM_0, Tuesday, February, 00 R G MEMORY (SSTL-.) VREF =.*VQ (SSTL-.) VREF =.*VQ R G MEMORY (SSTL-.) VREF =.*VQ (SSTL-.) VREF =.*VQ SI- modified -- for support Gbit VRM ( M X ) SI- modified -- for support Gbit VRM ( M X ) SI- modified -- for support Gbit VRM ( M X ) SI- modified -- for support Gbit VRM ( M X ) 0.U/0V_ 0.U/0V_ 0.U/0V_ R./F_ 0 0.U/0V_ 0.U/0V_ 0U/.V_ R./F_ 0U/.V_ 0.U/0V_ U/0V_ R0.K/F_ R.K/F_ 0.U/0V_ 0.U/0V_ *0U/.V_ U/0V_ 0U/.V_ R.K/F_ 0.U/0V_ 0.U/0V_ 0.0U/V_ 0.U/0V_ U HYTF-0 VREF J LM F UM Q Q Q Q Q0 Q Q Q F Q F Q H Q H Q H Q H Q G Q0 G L 0 L P 0/P M P P P N N N N 0 M M M RS K KE K OT K S L S L K J K K WE K VQ0 G VQ VQ VQ VQ VQ VQ E VQ G VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ E VSSQ F VSSQ F VSSQ H VSSQ0 H VSS VSS E VSS J VSS N VSS P UQS UQS LQS E LQS F VQ G VQ G V V E V J V M V R R Q VL J VSSL J R N# L N#R R R N#E E U/0V_ U HYTF-0 VREF J LM F UM Q Q Q Q Q0 Q Q Q F Q F Q H Q H Q H Q H Q G Q0 G L 0 L P 0/P M P P P N N N N 0 M M M RS K KE K OT K S L S L K J K K WE K VQ0 G VQ VQ VQ VQ VQ VQ E VQ G VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ E VSSQ F VSSQ F VSSQ H VSSQ0 H VSS VSS E VSS J VSS N VSS P UQS UQS LQS E LQS F VQ G VQ G V V E V J V M V R R Q VL J VSSL J R N# L N#R R R N#E E R.K/F_ 0.U/0V_ 0.U/0V_ 0.U/0V_ R.K/F_ 0.U/0V_ R./F_ 0.0U/V_ 0.U/0V_ 0.0U/V_ U HYTF-0 VREF J LM F UM Q Q Q Q Q0 Q Q Q F Q F Q H Q H Q H Q H Q G Q0 G L 0 L P 0/P M P P P N N N N 0 M M M RS K KE K OT K S L S L K J K K WE K VQ0 G VQ VQ VQ VQ VQ VQ E VQ G VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ E VSSQ F VSSQ F VSSQ H VSSQ0 H VSS VSS E VSS J VSS N VSS P UQS UQS LQS E LQS F VQ G VQ G V V E V J V M V R R Q VL J VSSL J R N# L N#R R R N#E E U HYTF-0 VREF J LM F UM Q Q Q Q Q0 Q Q Q F Q F Q H Q H Q H Q H Q G Q0 G L 0 L P 0/P M P P P N N N N 0 M M M RS K KE K OT K S L S L K J K K WE K VQ0 G VQ VQ VQ VQ VQ VQ E VQ G VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ E VSSQ F VSSQ F VSSQ H VSSQ0 H VSS VSS E VSS J VSS N VSS P UQS UQS LQS E LQS F VQ G VQ G V V E V J V M V R R Q VL J VSSL J R N# L N#R R R N#E E 0.U/0V_ R./F_ 0 0.U/0V_ 0.U/0V_ 0P/0V_ 0.0U/V_ 0.U/0V_ R.K/F_ U/0V_ 0 0P/0V_ 0.U/0V_ 0 0.U/0V_ R.K/F_ 0.U/0V_ R.K/F_ 0.U/0V_

23 +VLW +V. If L connector near GPU, then place these series Resistors near GPU. If L connector near N/, then place these series Resistors near N/ +V R.K_ EILK OPTION SIGNL FROM N to LVS for UM R O0 I 0.U/0V_ R.K_ EIT current L_LK RP 0 L_LK *0_PR_ TXLLKOUT+ 0K_. +V R0 R/F_ +LOGO_PWR 0 L_LK# L_LK# TXLLKOUT- +VSUS N-MOS,. L_TP0 RP TXLOUT0+ 0 L_TP0 *0_PR_ Q +VL L_TN0 TXLOUT0- +VL_ON 0 L_TN0 O0 L L_TP RP +VL TXLOUT+ LONG 0 L_TP *0_PR_ PY00T-_ 0U/.V_ L_TN TXLOUT- 0 L_TN SI- modified-delete R0 and 0 0.U/0V_ L_TP RP TXLOUT+ 0 L_TP *0_PR_ R R0 from 0ohm to ohm 0.0U/V_ L_TN TXLOUT- 0 L_TN R0 00K/F_ +VIN_LIGHT +VIN_LIGHT 0 L_LK L_LK RP *0_PR_ TXULKOUT+ _ +VL_ON 0 L_LK# L_LK# TXULKOUT- +VL_ON L_TP0 RP TXUOUT0+ 0 L_TP0 *0_PR_ 000P/0V_ L_TN0 TXUOUT0- LISHG 0 L_TN0 Q Q L_TP RP TXUOUT+ 0 L_TP *0_PR_ PTEU N00E 0.U/0V_ L_TN TXUOUT- 0 L_TN +V EILK 0, L_TN RP *0_PR_ TXUOUT- EIT VJ 0 L_TN 0, ISP_ON 0, EIT L_TP TXUOUT+ +LOGO_PWR 0 0 L_TP LON# Q LONON amera Pin R N00E 000P/0V_ OPTION SIGNL FROM MX to LVS for discrete.k_ TXLLKOUT+ TXULKOUT+ TXLLKOUT- 0 TXULKOUT- EXT_TXLLKOUT- EXT_TXLLKOUT- RP 0_PR_ TXLLKOUT- EXT_TXLLKOUT+ EXT_TXLLKOUT+ TXLLKOUT+ TXLOUT0+ TXUOUT0+ EXT_TXLOUT0- RP 0_PR_ TXLOUT0- TXLOUT0- TXUOUT0- EXT_TXLOUT0- EXT_TXLOUT0+ TXLOUT0+ EXT_TXLOUT0+ EXT_TXLOUT- RP0 0_PR_ TXLOUT- H0H-0PT TXLOUT+ 0 TXUOUT+ EXT_TXLOUT- EXT_TXLOUT+ TXLOUT+ PN_LON LONON TXLOUT- TXUOUT- EXT_TXLOUT+ P/0V_ EXT_TXLOUT+ RP 0_PR_ TXLOUT+ EXT_TXLOUT+ EXT_TXLOUT- TXLOUT- TXLOUT+ TXUOUT+ EXT_TXLOUT- +VPU R K_ R 00K/F_ TXLOUT- TXUOUT- EXT_TXULKOUT- EXT_TXULKOUT- RP 0_PR_ TXULKOUT- H0H-0PT 0 EXT_TXULKOUT+ EXT_TXULKOUT+ TXULKOUT+ LVS_LON R K/F_ PN_LON LI_E# 0, LVS_LON LI_E#, EXT_TXUOUT0+ RP 0_PR_ TXUOUT0+ EXT_TXUOUT0+ N EXT_TXUOUT0- TXUOUT0- EXT_TXUOUT0- EXT_TXUOUT- RP 0_PR_ TXUOUT- EXT_TXUOUT- L ONN HWPG 0,,,,, EXT_TXUOUT+ TXUOUT+ 0, PST_PWM PST_PWM EXT_TXUOUT+ R *0_ EXT_TXUOUT- RP 0_PR_ TXUOUT- EXT_TXUOUT- H0H-0PT EXT_TXUOUT+ TXUOUT+ PWM_VJ VJ EXT_TXUOUT+ R 0_ PWM_VJ L_K L_K Q el R and Pull hi R to +VS, add to HWPG on PV R PTEU PV del logo light *0K/F_ *.U/.V_ 0.U/0V_ +VS UM/ISRETE select for HMI From RS0M _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX From M-S +V Q N00E R 00K/F_ for Layout concern,placement close north bridge _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX _PEG_TX# _PEG_TX TX_HMI- TX_HMI+ TX_HMI_L- TX_HMI_L+ TX_HMI_L- TX_HMI_L+ TX0_HMI_L- TX0_HMI_L+ TX_HMI_L- TX_HMI_L+ R0 R0 R0 R0 R R R0 R00 *0.U/0V_ TX_HMI-L *0.U/0V_ TX_HMI+L *0.U/0V_ TX_HMI-L *0.U/0V_ TX_HMI+L *0.U/0V_ TX0_HMI-L *0.U/0V_ TX0_HMI+L *0.U/0V_ TX_HMI-L *0.U/0V_ TX_HMI+L /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ TX_HMI+ TX_HMI+ TX0_HMI+ TX_HMI+ *0_PR_ TX0_HMI+ TX0_HMI- TX0_HMI- TX_HMI- TX_HMI- TX_HMI- RP TX_HMI+L TX_HMI-L RP TX_HMI-L TX_HMI+L RP TX0_HMI+L TX0_HMI-L RP TX_HMI-L TX_HMI+L TX_HMI- TX_HMI+ TX_HMI- TX_HMI+ TX0_HMI- TX0_HMI+ TX_HMI- TX_HMI+ for Layout concern,placement close HMI conn for Layout concern,placement close HMI conn UM RS0M 上 0 ohm S0F IS M-S 上 ohm SF lose to HMI onnector *0_PR_ TX_HMI- TX_HMI+ *0_PR_ TX_HMI- TX_HMI+ *0_PR_ TX_HMI+ TX_HMI- +VIN el, for HMI on PV HMI_SLK HMI_ST +V L 0.U/0V_ HMI_SLK FM HM0-T(,0.0)_ 0.0U/0V_ +V_HMV H0H-0PT R.K_ +V_HMV TX_HMI+ TX_HMI- TX0_HMI- TX_HMI+ TX_HMI- TX0_HMI+ HMI_ET 0.U/0V_ H0H-0PT R0.K_ HMI_ST HMI PORT L 0_ HMISL L 0_ HMIS +V_HMV FUSEV_POLY F *0.U/0V_ *0U/V_ +VIN_LIGHT 0.U/0V_ hange R, R0 to.k for M on PV HMI ONN 0, TMS_HP HMI_S HMI_SL iscrete is V tolerance, the MOSFET level shifter no need UM is V tolerance,the MOSFET level shifter is need N/R HMI HP SENSE 0 UZS.TE- TMS_HP TX_HMI_L- TX_HMI_L+ TX_HMI_L- TX_HMI_L+ TX0_HMI_L- TX0_HMI_L+ TX_HMI_L- TX_HMI_L+ N SHELL 0 + SHELL Shield 0 HMI LK - + +V Shield - HMI LK R *0_ HMI_SLK 0+ 0 Shield HMI T R *0_ HMI_ST 0-0 K+ K Shield K- 0 HMI T E Remote N LK T GN +V HP ET SHELL SHELL +V R R 00K/F_ 0K/F_ HMI_ET UM N ISRETE HMI I SELET lose to HMI onnector RP R0 *K/0 R *K/0 0_PR_ IS +V check v or v HMI_ST HMI_SLK hange N00 to FV0N for M on PV HMI_SLK Q *FV0N +V Q0 *FV0N UM HMI_ST PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom L ONN,HMI ONN ate: Tuesday, February, 00 Sheet of

24 RT PORT +V F 0 mils FUSEV_POLY +VRT +VRT 0 0.U/0V_ 0 MIL SI- modified --hange Layout footprint / RT_R L RT_G L RT L R00 0/F_ R R 0/F_ 0/F_ R00 for UM use 0 ohm on PV(M).P/0V_ 0.U/0V_.P/0V_ U +V L L0 L.P/0V_ LM0SN(,00M)_ LM0SN(,00M)_ LM0SN(,00M)_ close conn within 00mils.P/0V_ RT_R RT_G RT_.P/0V_.P/0V_ EMI R 0_ R _ R _ R 0_ 0 RTLK RTVSYN RTHSYN RTT RT ONN N0 +V +V *VW *VW *VW *VW RT_R RT_G RT_ LK 0,, VSYN_OM U HTGH HTGH PR_VSYN *0P/0V_ *P/0V_ *P/0V_ *P/0V_ *VW RTVSYN follow M reference schematic change for reduce leakage to VR US 0,, HSYN_OM 0, LK +V_ELY +V +V_ELY +V LK R R R R.K_ *.K_.K_ *.K_ +V +V Q N00E LK PR_HSYN LK *VW *VW RTHSYN T 0, T T Q N00E T R R T.K_.K_ +VRT +VRT +V_RT H0H-0PT PR_RE PR_GEN PR_LU, PR_INSERT# PR_RE RT_R L PR_GEN RT_G L PR_LU RT L U I0 I I0 Y I Y I0 Y 0 I Y I0 I SEL V /E GN T RT SWITH RT_R RT_G RT_ +V_SW R0 0_ 0.U/0V_ RT_R 0, RT_G 0, RT_ 0, EMI +V R0 0K/F_ inputs /E SET L L L H H X function Y - port 0 Y - port isconnect PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom RT ate: Tuesday, February, 00 Sheet of

25 LK_M_R +VSUS, R_LE# For E SI- modified --Fix Y layout footprint to XTL-X_-_ (ME placement) USP_R- USP_R+ +VSUS R0 R *0K/F_ R *0K_ If S_T connect to SP, MO_SEL need to let it to N. R_LEO X_# SP S_# SP XTLO RREF XTLO XTLI *.P/0V_ G000 For R R R R *0_ *.P/0V_ *0_ *.K/F_ *P/0V_ For *00K/F_ *MHz Y MOE_SEL *00K/F RST# *U/0V_ 0 UM OM need to add U X_LE/F_ X_E#/F_ F_# X_LE/F_ GPIO0 F_0 S_T/X_RE#/F_ 0 F_ S_T/X_WE#/F_ F_ X_RY/F_ F_/SM_# S_T/X_WP#/F_ F_/X_# F_0/SM_WPM#/S_WP S_M F_0/S_# S_T/X_0/F_ F_MK# S_LK/X_/MS_LK/F_ F_/X_ S_T/X_/MS_/F_ F_MRQ F_S0# 0 MS_INS#/F_IOR# RREF S_T/X_/MS_/F_IOWR# S_T0/X_/MS_0/F_RST# S_T/X_/MS_/F_IORY X_/MS_S/F_ M P V_PLL_IN XTLO XTLI MOE_SEL RST# *RTS VREG_OUT 0 V_IN V_ IN V_ IN V_OUT V_OUT R_V_OUT SP SP SP SP SP SP SP S_M_R SP SP SP0 MS_# SP SP SP SP VREG *0.U/0V_ G G_PLL GN GN *0.U/0V_ *0.U/0V_ *U/0V_ SP SP +VR For R *0_ R +VSUS *.U/.V_ For E S_T L000 -->RTSE L >RTS SI- remove R not need -- UM OM remove *0.U/0V_ *U/0V_ *0_ +VSUS_RTS +VSUS *0.U/0V_ *0.U/0V_ *0.U/0V_ *0.U/0V_ Note: SP X_# SP S_WP SP S_# SP S_T X_ SP MS_S X_ SP S_T MS_ X_ SP S_T0 MS_0 X_ SP S_T MS_ X_ SP MS_INS# SP0 S_T MS_ X_ SP S_LK MS_SLK X_ SP S_T X_0 SP S_T X_WP# SP X_R/# SP S_T X_WE# SP S_T X_RE# SP X_LE SP X_E# SP X_LE R *.U/.V_ +VR S/MM MS X *0_ +VSUS *0.U/0V_ *0.U/0V_ X_# SP SP SP SP SP SP SP SP SP SP SP SP0 SP SP SP SP S_M_R H0H-0PT MS_# S_# H0H-0PT 0P/V_ RTS need to remove // R R R R R R R R R R R0 R R R R R R R R R R R R R *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ *0_ MS_T0_S_T0 X- MS_T X- MS_T_X_ S_T X-RE# MS_S X- S_T X_WE S_LK_MS_LK X- S_WP X-WP# X-LE X- MS_T X- X-R# X-0 X-LE X-E# S_M JM 0 Note: S/MM MS X MI0 S_T0 MS_0 X_0 MI S_T MS_ X_ MI S_T MS_ X_ MI S_T MS_ X_ MI S_M MS_S X_WE# MI S_LK MS_SLK X_E# MI S_WP X_WP# MI X_LE MI S_T X_ MI S_T X_ MI0 S_T X_ MI S_T X_ MI X_RE# MI X_R/# MI X_LE R_LEN S_LE# MS_LE# X_LE# R_PTLN S_PTL#MS_PTL#X_PTL# R_0 S_# X_V# R_ MS_# X_# +VR R *0K/F_ X-WP# el R for TP on PV.U/.V_ LOSE ONN MS_# +VR +VR 0.U/0V_ 0 *0P/V_ X-RE# X-E# X-LE X-LE X_WE X-0 X- S_T S_T S_M X-R# S_LK_MS_LK MS_T MS_# MS_T_X_ MS_T0_S_T0 MS_T MS_S R0 0K/F_ 0.U/0V_ +VR M_PWR_TRL_0# 0.U/0V_ IN R REER X,MM/S,MS/MSP N X-R/ X-RE X-E X-LE X-LE X-WE X-WP X-T0 X-T 0 S-T S-T S-M GN MS-V MS-SLK MS-T MS-INS MS-T MS-T0 0 MS-T MS-S GN IN R REER SOKET +V GN GN GN 0 GN GN S-/ S--SW S-W/P S-WP-SW X- X-V X-T X-T X-T 0 S-T X-T X-T X-T S-T0 S-LK S-V Q *O0 +VR S_# S_# S_WP S_WP X_# X_PWON R X- X- X- S_T X- X- MS_T_X_ MS_T0_S_T0 S_LK_MS_LK +VR R 0_ RESERVE for JMicron -- after programming can out-put +.V throught M_PWR_TRL_0# signal *0K/F_ S_# +V +VR SI- for 台端 onn X-R# X-RE# X-E# X-LE X-LE X_WE X-WP# X-0 X- S_T S_T S_M S_LK_MS_LK MS_T MS_# MS_T_X_ MS_T0_S_T0 MS_T MS_S +VR N x-r/ x-re x-e x-le x-le x-we x-wp x-0 x- 0 S-T S-T S-M GN MS-V MS-SLK MS-T MS-INS MS-T MS-T0 0 MS-T MS-S GN *TI TWUM IN R REER SOKET MIO00 R 0_ R 0_ MIO0 R0 0_ R0 0_ R 0_ MIO0 R 0_ R0 0_ MIO0 R 0_ R 0_ R0 0_ MIO0 R 0_ R0 0_ R 0_ MIO0 R /F_ R /F_ MIO0 R 0_ R 0_ R 0_ MIO0 R0 0_ MIO0 R0 0_ MIO0 R0 0_ MIO0 R0 0_ MIO R 0_ MIO R 0_ MIO R 0_ MIO SI- modified - for Jmicron updae GN GN GN GN N 0 N S- S-WP x- x-v x- x- x- 0 S-T x- x- x- S-T0 S-LK S-V +VR MS_T0_S_T0 X-0 S_T MS_T X- MS_T_X_ S_T MS_T S_T X- S_M MS_S X_WE S_LK_MS_LK X-E# S_WP X-WP# X-LE X- X- X- X- X-RE# X-R# X-LE S_# S_WP X_# X- X- X- S_T X- X- MS_T_X_ MS_T0_S_T0 S_LK_MS_LK P M_SPRING K/ SREW HOLE Mini ard Hole P H *H-S0P H *H-S0P H0 *H-P *H-P M_SPRING P M_SPRING H H *H-P H *H-S0P H *H-P H *H-S0P VG Hole N/R P0 P M_SPRING M_SPRING H H *H-P *H-P H *H-P SI- for N H *H-P H *H-P H0 *H-P H *H-P H H *H-P *H-P H *H-dp H0 *H-P H *H-P H *H-P H *H-S0P H *H-S0P H *H-S0P el P for TP on PV for M cable routing PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom RTS & R SOKET &HOLE ate: Tuesday, February, 00 Sheet of P M_SPRING P M_SPRING P H *H-OXXN P *M_SPRING P *M_SPRING *M_SPRING H *H-P H *H-P P *M_SPRING

26 +V 0 0.U/0V_ 0.U/0V_ TPIS0 R./F_ R./F_ 0.U/V_ 0.U/0V_ 0U/.V_ TP0N TP0P TP0N TP0N TP0P *WM-0-00T(00m) +.V L +.V_R *LMPGSN(0,.)_ 0U/.V_ 0 0.U/0V_ 0.U/0V_ 0 000P/0V_ TP0P TPIS0 K % :S0F or S0F0 R K/F_ +V MIO0 MIO0 MIO0 MIO MIO TP0P TP0N L L *WM-0-00T(00m) TP0P TP0N TP0P TP0N _ONN N 0.U/0V_ 0.U/0V_ +.V_R U V TXIN TREXT TPIS_ TPS MIO MIO R0 R./F_./F_ R.K/F_ E : mode : when card device insert can wake up card reader chip mode : need to use pin to wake up card reader device MIO0 MIO0 MIO R_LEN V 0 MIO R_LE#, +V +V E _WKEN pin :out put low ms can wake up system when system into E mode P/0V_ MIO0 MIO0 MIO0 MIO0 MIO0 MIO00 +V XRSTN XTEST PLKN PLKP PV JM0 PGN PREXT PRXP PRXN PV V V R_PTLN R_0N R_N N E_WKEN +.V_R M_PWR_TRL_0# E_WKEUP R.K_ E _WKEN pin :out put Hi into E mode out put low normal mode MS_# S_# SI- modified - for E GPIO# Jmicron updae Q N00E-G R Q for power leakage concern.k_ E_SI# +VS 0 TPP TPN TPP TPN TV 0 PTXN PTXP MIO MIO MIO0 MIO MIO R 0K/F_ 0P/0V_ R M/F_ 0 TXOUT MIO MIO P/0V_ Y.MHZ MIO MIO V MIO MIO MIO MIO0 EP T R.K_ R0V-0 +VR R_PLTRST# LK_PIE_R# LK_PIE_R +.V_R R0.K/F_ +.V_R MIO0 MIO MIO0 R R R 0K/F_ 0K/F_ 0K/F_ +V PIE_TXP PIE_TXN PIE_RXN PIE_RXP 0.U/0V_ 0.U/0V_ PIE_RXN_ PIE_RXP_ MIO R0 MIO R0 00K/F_ 00K/F_ PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev JM0 ontroller/ ate: Tuesday, February, 00 Sheet of

27 Z_SOUT_UIO +V Z_SIN0 Z_SYN_UIO JK_SEN# R0 S_# Z_SYN_UIO Z_RST#_UIO SPIF IT_LK_UIO Z_SIN0_ SENSE_ IGITL_LK 0 P/0V_ MI_R MI_L OK_MI_R OK_MI_L 0.U/0V_ ERPO_R ERPO_L 0 IGITL_ R 0_ PORT-_L HP-L 0.U/0V_ VOL_UP/MI_0 +V_V R0 0_ SENSE_ V_IO SENSE_ / N T IGITL_ VOL_N/MI_ P U/0V_ GN IT_LK_UIO SI- Modified -- change footrint QFN-X--P-H for datasheet update L 0_ 0 U/0V_ Z_RST#_UIO GN +V_V 0 0.U/0V_ 0U/.V_ +V_V SI- for EMI 0 *P/0V_ R0 _ 0.0U/V_ el R direct on PV 000P/0V_ *.U/0V_ U SI- Modified GN EP#--EFULT is Hi EP# R _ GN H 0U/.V_ +.VV GN MI-VREFO-E IT_GPIO# MI-VREFO- MI-VREFO- VREF_FLT _VSS +.VV GN MI-VREFO-E GN hange, footprint TO Internal Speakers recommand use XR /0V 0.U/.V_.U/.V_ + 00U/.V_ 00U/.V_ L *0_ 0.U/0V_ HP-R R GN ERP_R ERP_L IT_GPIO#.K_ +V +.VV GN GN TO Headphone jack R.K_ R R U/0V_ S_E# el R, R, R direct on PV.K/F_ 0K/F_ GN EXT_MI_R EXT_MI_L R 0_ GN OK_MI_L IT_LK_UIO OK_MI_R GN SHIEL GN U/0V_ MINON 0,,,,, Z_SIN0_ *P/0V_ FOR EMI E +V TO EXTERNL MI TO OK MI udio JK: Normal Open S_# -->EXT HP S_# -->EXT MI S_E#-->OK MI hange to SHORT- for EMI on PV, Z_SPKR R0 K_ +.VV V 0 R *0_ PEEP 0U/.V_ U/0V_ U/0V_ U/0V_ 0.U/0V_ R *0_ 0.U/0V_ +V_V R 00 GN GN GN GN GN GN GN 0K/F_ 0.0U/V_ +.VV MI-VREFO- R.K_ 0 0.U/0V_ R 0U/.V_.K/F_ 0K/F_ R 0.K/F_ SPIF0 V_ORE SO ITLK VSS EP SI_OE V_ORE SYN RESET# SENSE_ EP PORTE_L MI_LK PORTE_R GPIO / SPIF OUT PORTF_L GPIO PORTF_R GPIO N VSS** N PORT_R N 0 N 0 PORT_L PORT_L PORT_R V** VREFOUT-E / GPIO PORT_L N MONO_OUT VREFOUT- VREFOUT- PORT_R PORT-_R GPIO VREFFILT VSS 0 0.U/.V_.U/.V_ 0U/.V_ + R U/0V_.K_ R.K/F_ 0 U/0V_ R R R U Vout.K/F_ YP GN TPS 0K/F_.K/F_ Vin EN 0.U/0V_ 0.0U/V_ R R R R L 0_ GN SHIEL GN SHIEL GN SHIEL GN SHIEL GN SHIEL *0_ *0_ *0_ *0_ 0.U/0V_ 0U/.V_ *P/0V_ GN, IR_IN *0P/0V_ *0P/0V_ +VPU ERP_L ERP_R S_# S_# EXT_MI_L EXT_MI_R 0 *0P/0V_ *0P/0V_ GN for EMI GN GN GN 0.U/0V_ GN TO Headphone jack N UIO ONN 0 TO UIO/ ON. SI- modified -- hange footprint for ME request, pin, are 固定 pin OK MI ETET OK_MI_L R K_ R 0K/F_ KMI_SEN 0 R U/0V_ K_ S_E# +V R K_ Q MMT0 Q MMT0 GN Q N00E +V S_# R JK_SEN# R *0_ +V 00K/F_ R0 change to 0K for HP on PV R0 00K/F_ GN GN Q N00E Q N00E GN Q N00E dd for soft-star on PV +VLW Q N00E R0 0K/F_ Q N00E.0U/V_ GN ERPO_R R ERPO_L R *0_ R *0_ /F_ R /F_ hange, footprint + 00U/.V_ el R, R on PV + TO OK Headphone 00U/.V_ RSPK_K LSPK_K PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom zalia ate: Tuesday, February, 00 Sheet of E

28 UIO MPLIFIER 0 Gain Table GIN0 GIN V RIN 0 0 d 0K 0 0d 0K 0.d K.d K SI- Modified -- remove / L_SPK- +VMP LIN-,RIN- and LIN+,RIN+ swap for OO noise on PV U PV ROUT+ PV ROUT- V HP_L SPKR_L LOUT+ R 0K/F_ HP-L 0.0U/V_ HP_R SPKR_R LIN- LOUT- R 0K/F_ HP-R 0.0U/V_ RIN- P_EEP SHUTOWN LIN+ RIN+ N GN 0 MP_YPSS EP 0.U/0V_ 0 YPSS GN PV- Modified --R, R change from 0Kohm to 0 ohm UIO_G0 GN UIO_G GIN0 GN for Volume too low issue +VMP GIN GN 0 TP0/FN0/LM R 00K/F_ R K_ R0 00K/F_ UIO_G0 UIO_G R *K/F_ SI- modified -- remove, add 0 VOLMUTE# EP# 0 T +V GN R 00K/F_ GN +V 00P/0V_ GN 00P/0V_ GN R 0_ +VMP 00P/0V_ GN 00P/0V_ 0U/.V_ 0.U/0V_ R_SPK+ R_SPK- L_SPK+ L_SPK- L L 0P/0V_ impedance 0.ohm L L0 SI- modified -- for EMI suggestion 0.U/0V_ K0HM K0HM 0.0U/V_ K0HM K0HM 0P/0V_ GN GN R_SPK+ 0P/0V_ L_SPK+ R_SPK- 0P/0V_ GN N INT SPEKER ONN INT. SPEKER Vrms = Vpp / Power = (Vrms) / R QT speaker --.ohm / W R R0 *0_ *0_ R, R0 change to SHORT- on PV GN GN P-EEP GN +VMP KEY_EEP *0.UF/0 +V R *K/0 P_EEP, Z_SPKR VOLMUTE# TO OE *.U/V/0 R GN U *NSZ *0_ SI- modified - from Hp suggestion R *K/0 GN *.U/0V_ TO MP MP_GN *.U/0V_ MUTE_LE Low -->un-mute High-->Mute, SI- modified -- remove R0,Q, add R,,Q0 MUTE_LE IT_GPIO# R SI- Modified 0K/F_ T +VPU R 00K/F_ Q0 MEN00E SI- Modified -- R change from 0k to 00k cceleration sensor el R +V 0U/.V_ INTH#,,,, PT_SM,,,, PLK_SM +V 0.U/0V_ R 0 0.U/0V_ PT_SM PLK_SM 0K/F_ U Vdd_IO V Reserved Reserved INT INT SO GN S/SI/SO GN SL/SP GN S GN 0 SGT-LIS0LTR INTH# el R,,,, PT_SM,,,, PLK_SM *0.U/0V_ +V *0.U/.V_ PT_SM PLK_SM reserved second source U V Reserved V_IO Reserved 0 INT SI SK SO S GN *OSH M0 SGT-LIS0LTR interrupt pin default is low / active Hi, IOS need to programming h to change status from active Hi to low PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom MP_TP0/INT SPK ate: Tuesday, February, 00 Sheet of

29 Modem ONN H FS0 H FS0 +V E M N Z_SOUT_UIO_M GN REV Z_SOUT_UIO_M.U/.V_ 000P/0V SO REV 0.U/0V_ Z_SYN_UIO_M GN V Z_SYN_UIO_M _SIN_M _SYN GN Z_SIN R SI GN 0 R 0 RST# _LK IT_LK_UIO_M 0 *0P/0V_ M ONN Z_RST#_UIO_M *0P/0V_ For EMI R0 (White) *0K/F_ ST_R_LE R 00F_ +V LE LE P WHITE/MER + - Q (mber) R Q Q 0_ SI- modified -- Single olor,right angle LEV_EN# LTW-0TL LE_EN for fix ST LE *PTEU *PTEU no support LE light control ST_LE# PTEU SI- modified -- change LE part number LE PWR ONTROL SI- change R0 from 00k to Mohm for current limit +VLW +V 0~0mils +V +V_LE +V_LE el R0 hange R to 00 dd R, R, R, R LE PWR control no-stuff on PV, PWR_LE# P WHITE LE PWR_R_LE R 0_ P WHITE LE MT_R_LE R 0_ R *M/F_ LE_TL White P WHITE LE LE node mber R_LE, R_LE# R 0_ +V LEV_EN# *N00E *.U/V_ LEV_EN# *U/V_ *.U/V_ Q ual olor,right angle LTW-SKF- R0 *M_ R 0_ Q *N00E 0U/.V_ 0 0.U/0V_ MTLE0# LE LE SI- modified -- LE change footprint +VPU_LE +VPU_LE LE add LE auto dim function PSLE# LE P WHITE P_LE R 0_ +V_LE R 0_ +VPU LE_TL Q *N00E 0U/.V_ +VPU_LE 0.U/0V_ 0~0mils +VPU_LE TP_LE# TP_LE# LE Vf (mber) TP_LE# TP_LE# (White) I = Vcc -Vf / R R TPL R 00/F_ TPL R 0_ For P LE LE P WHITE/MER +V_LE +V_LE Vcc mber + node + White Q *O0 +V LE_TL R 0_ 0 0.U/0V_ 0~0mils *0U/.V_ +V_LE N/R PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom M. on ccelerometer/lle ate: Tuesday, February, 00 Sheet of E

30 LUETOOTH IGITL_ IGITL_LK +V USP+ USP- USP- USP+ IGITL_LK IGITL_ IGITL_LK T_OFF# SI- Modified footprint -- for ME change pitch for.mm to.0mm For iscrete Touch-Screen US MER ONNET U/0V_ L *WM-0-00T(00m) SI- dd for EMI solution *P/0V_ U VIN SHN GN VOUT SET el R on PV 0.U/0V_ R I(P) G (SOT-)EP R *0_ R +V +VPU R *K/F_ R *00K/F_ R.K_ SI- Modified +.V-MR Q0 PTEU N0 MER-OR +VSUS US0PWR USP0- USP0+ TON_P LUELE USP- USP+ TV TV mil USP0- USP0+ LUELE, USP- USP+ SI- Modified -- remove touch-screen function.u/.v_ R and R no-stuff for fix Vout on PV 0.U/0V_ N LUE TOOTH ONN -000-P-L Q ME0T 0U/.V_ T 0.U/0V_ US Fingerprint ON el R on PV L0 *00U/.V_ 0.U/0V_ *WM-0-00T(00m) +V. ES GN. SYSTEM GN. US-. US+. US PWR(+V) USP+ USP- USP+ USP- N FINGER PRINTER ONN P footprint L-0R-P-L-QT *lamp-iode_ USP- USP+ USP+ USP- +VSUS LEFT SIE USX and E-ST/US OMO U/0V_ *lamp-iode_ L GPU (TPS0) RIGHT SIE USX USP+ USP- +.V-MR USP- USP+ ST_TXP ST_TXN ST_RXN ST_RXP +VSUS 0 mils (Iout=) US0PWR L0000 I(P)GPU(MSOP-) -. L I OTHER(P) GPU(MSOP-) - *WM-0-00T(00m) L U VIN VIN EN GN *WM-0-00T(00m) + 0 *P/0V_ *00UF_V OUT OUT OUT O *P/0V_ *P/0V_ 0 0.U/0V_ *P/0V_ *0P/0V_ *lamp-iode_ 0 *0P/0V_ 0 0 +VSUS 0.U/0V_ lose to EST ON from M recommend 0.U/0V_ N UL US ONN P footprint L-0R-0P-L-QT + US0PWR USP- USP+ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ 0 00UF_V 0 *lamp-iode_ US 0 N GN GN GN GN US ONN 0 SI- modified -- hange onnector layout type from SM P to ip as SMT request US & EST N US Vcc - + GN GN Shield + - Shield GN - Shield 0 + GN Shield US_EST_OMO PROJET : QT Quanta omputer Inc. Vout=.(+R/R) N/R Size ocument Number Rev ustom T/WEM/FT/USX/EST ate: Tuesday, February, 00 Sheet 0 of

31 +F R 0_ +LN_._F Stuffed for 0E/0E/RTL +VLNV R 0_ 0.U/0V_ +TRL_E 00 0U/.V_ 0 0U/.V_ +VLNV R 0_ +V_GV el R0 on PV LN_TX# +LN_. +V LN R 0_ +LN_._RV +V LN LN_LE_00# R0 0_ LN_GLINK00# Stuffed for RTL(0/00/000) Y MHZ 0P/0V_ 0P/0V_ +LN_. +LN_. el R, R, R, R,, for on PV el R,, 0 on PV +LN_. R +TRL +V LN *0_ R SI- modified -- RTL remove, RTL,0E,0E need to stuff +V LN MI0+ MI0- +LN_._F MI+ MI- +LN_. MI+ MI- +LN_. MI+ MI- +LN_. +V_LN XTL XTL +V_GV +TRL_E LNRSET LN_GLINK0# LN_GLINK000# +LN_. +LN_. +LN_. +LN_. +V_LN +V_LN +LN_. PIE_WKE# PIE_RXN_LN_L 0.U/0V_,, PIE_WKE# PIE_RXN_LN PIE_RXP_LN_L 0.U/0V_ PIE_RXP_LN +LN_. +LN_. +LN_E. +LN_E. +LN_E. +LN_E. PIE_LN_LKN PIE_LN_LKN PIE_LN_LKP PIE_LN_LKP PIE_TXP_LN PIE_TXP_LN PIE_TXN_LN PIE_TXN_LN +V_LN LN_REST# R R0.K/F_ T T U VTRL V MIP0 MIN0 V MIP MIN V MIP 0 MIN V MIP MIN V V V *0_ EP RSET VTRL GV KTL KTL 0 V V LE_TX# LE_00# LE_0# LE_000# V V PLK_SM PT_SM LNWKE# PERST# V EV HSIP HSIN GN REFLK_P REFLK_N EV HSOP HSON GN V 0 0 LN_REST_R# N N 0 V EESK EEI V EEO EES V N V RTL-V-GR N 0 N V V ISOLTE# N N V R.K_ EEI +V_LN +V_LN +V +V_LN LN LE ETET +LN_. el R for TP on PV +V_LN el U, R on PV R *K/F_ +TRL R Stuffed for 0E/RTL0E R only for, 0E&0E& can remove Remove R and dd on PV ISOLTE R 00_ R *R0V-0 K/F_ *0_ LN_ISLE#, +V_LN +V_LN +TRL_E use IOS to programming EEPROM, EEI should be pull Hi if ISOLTE pin pull-low,the LN chip will not drive it's PI-E outputs ( excluding PIE_WKE# pin ) R 0_ R 0_ LN_GLE LN_GLE# EMI *0.U/0V_ LN_YLE LN_GLE RJ N 0 *0.U/0V_ LE_GRE_P 0 LE_GRE_N LN_MX- LN_MX+ RX- LN_MX- RX+ LN_MX- RX0- LN_MX+ TX- LN_MX+ TX+ LN_MX0- RX0+ LN_MX0+ TX0- TX0+ LN_YLE LN_YLE# LE_YEL_P LE_YEL_N GN GN LN_GLINK0# LN_GLINK00# LN_GLINK000# LN_TX# Link T R0V-0 R 0_ LN_GLE# LN_YLE# LN_PLTRST# *0.0U/V_ *0.0U/V_ L000 L00E00 LN_PLTRST# I TRL(P) RTL-V-GR(QFN) I(P)RTL0E-GR(QFN) U TSH0FU R +V_LN *0_ SI- modified -- LN_PLTRST# is VS power rail, Maybe can remove NN GTE 0.U/0V_ LN_REST_R# 0 0.0U/V_ MI0+ MI0-0.0U/V_ MI+ MI- 0.0U/V_ MI+ MI- 0.0U/V_ MI+ MI- el R on PV MT MX+ U V_ TT T+ T- V_ TT T+ T- V_ TT T+ T- MX- MT MX+ 0 MX- MT T- MX- MX+ MX- V_0 TT MT T+ MX+ LN_MT0 LN_MX0+ LN_MX0- LN_MT LN_MX+ LN_MX- LN_MT LN_MX+ LN_MX- LN_MT LN_MX+ LN_MX- NS0 NS0:GIGIT 0TLN0 NS0:0/00 0ZLN U/00V_ R LN_MX0+ LN_MX0-0.0U/00V_ R LN_MX+ LN_MX- 0.0U/00V_ R LN_MX+ LN_MX- 0.0U/00V_ R LN_MX+ LN_MX- /F_ /F_ /F_ /F_ RJ_ONN 0 000P/KV_0 PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom RTL/0E/RJ-RJ N ate: Tuesday, February, 00 Sheet of

32 +VLNV LNV.W m >0mil +V_LN Power trace Layout 寬度 > 0mil el L, L direct on PV 0 0U/.V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ these P are for LN HIP LNV pins--,, and.placement close lan chip placement close to lan chipset >0mil +V LN 0.U/0V_ 0.U/0V_ these P are for LN HIP LN_. pins-- and.placement close lan chip L RTL ( Gaga lan ) use.uh power choke >00m tolerance ±% RTL0E & RTL0E stuff 0ohm +F L RTL stuff RTL0E need to remove L +TRL L L 0 *0U/.V_ RTL 0E /0E stuff, RTL need to remove.uh,+-0%,0m_ 0U/.V_ 0U/.V_ RTL stuff RTL0E / 0E can remove 0.U/0V_ placement close to lan chipset L L 0_ >0mil R0 0.U/0V_ R 0_ +LN_. 0.U/0V_ 0.U/0V_ 0.U/0V_ +LN_E. U/0V_ +LN_. Power trace Layout 寬度 > 0mil 0 0.U/0V_ R0 0E need to remove 0E use 0 ohm use.uh these cap are for lan chip LN_. pins--,, and. placement close chip change to U on PV Power domain chart LNV LN_. LN_. LN_. RTL / RTL0E.V.V.V.V RTL RTL0E.V.V.V.V L 0_ L L RTL used 0ohm RTL 0E/0E need to remove these cap are for lan chip LN_. pins, such as and. placement close lan chip +TRL 0 L L *0_ L & 0 0E/0E stuff need to remove 0 *0U/.V_ 0 RTL stuff RTL0E / 0E can remove 0 0 0U/.V_ 0U/.V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ >0mil 0.U/0V_ 0.U/0V_ 0 0.U/0V_ Power trace Layout 寬度 > 0mil 0.U/0V_ +LN_. 0.U/0V_ these cap are for lan chip LN_. pins--,,,,,,,, and.placement close lan chip PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom LN Power ate: Tuesday, February, 00 Sheet of

33 ST -ROM ST_TXP ST_TXN ST_RXN ST_RXP +V O_V el L0 direct on PV 0U/.V_ R K/F_ O_V SI- Modified footprint -- Modify / 0.U/0V_ 0 mils 0.U/0V_ N S GN TXP TXN GN RXN RXP GN S P P +V 0 +V M GN GN P ST O 0.U/0V_ 0.U/0V_ NEWR NEWR (PIEXPRESS* + US*) USP- USP+ NEWR_ETET, SLK_WLN, ST_WLN,, PIE_WKE# PIE_NEW_LKN PIE_NEW_LKP PIE_RXN0 PIE_RXP0 PIE_TXN0 PIE_TXP0 SI- modified -- change footprint N #, as +V_NEWR ME request for Hole pad N change EXPR-0-00-P-L-QT USP- R0 0_ US- GN_ USP+ R 0_ US+ US- NEWR_ETET R 0_ PUS# US+ PUS# RSV_0 SLK_WLN RSV_ ST_WLN SMLK SMT +.V_NEWR +.V_0 0 PIE_WKE# +.V_ WKE# +VUX PERST# +.VUX PERST# +.V_ LK_NEW_OE# +.V_ NEWR_ETET R0 0_ PPE# LKREQ# PIE_NEW_LKN PPE# PIE_NEW_LKP REFLK- L *WM0-0 REFLK+ 0 PIE_RXN0 PIE_RXN0 GN_ PIE_RXP0 PIE_RXP0 PERn0 PERp0 PIE_TXN0 PIE_TXN0 GN_ N PIE_TXP0 PIE_TXP0 PETn0 N PETp0 L *WM0-0 GN_ N N N N +V +VUX +VS 0.U/0V_ 0 0.U/0V_ 0.U/0V_ E 0.U/0V_ 0 0.U/0V_ 0 0.U/0V_ +V +VS +.V_NEWR 0 0U/.V_ 0.U/0V_ +V_NEWR 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ R SI- remove --internal pull hi +VS SI- Modified footprint -- Modify 固定孔 Size as SMT request +V_H +V_H +V_H N0 SI uild ST H(ST) Main H +V V_H +V +V: ( Pin) +V: ( Pin) Gnd : ( Pin) ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 PUS# PPE# _SHN# _STY# 0. _STY# +V +VS STY#.VIN +VUX UXIN.VIN N_PLTRST# UXOUT +.V NEWR_ETET SYSRST#.VIN 0 PPE#.VIN PERST# PUS# +V_NEWR _SHN# PERST#.VOUT 0 NEWLKEN SHN#.VOUT NEW_O# O# RLKEN +.V_NEWR R0 0_ O#.VOUT GN.VOUT SI- modified for R00-TR-F add Pin ~ as U R NEW R POWER SWITH Thermal pad tied to Gnd pin name PPE# SYSRST# R R R0 R U *0K/F_ *0K/F_ *0K/F_ *0K/F_ pull hi/low internal pull up to UXIN internal pull up to UXIN +.V el R0, R, R, R for RF on PV SI- *.U/0V_ For HP request to reserve *.U/0V_ *.U/0V_ PIE_RXN0 PIE_RXP0 PIE_TXN0 PIE_TXP0 0 *.U/0V_ el R direct on PV +V_H R +V_H *0_ PUS## PERST# SHN# internal pull up to UXIN a logic level power good internal pull up to UXIN 0.U/0V_ 0.U/0V_ EXT_NW_LK_REQ# R 0_ +VS R *K_ RLKEN internal pull up to UXIN NEWLKEN 0U/.V_ 0.U/.V_ 0.U/0V_ 0U/.V_ *0U/.V_ *.U/.V_ *0.U/0V_ *0U/.V_ O# over current status Q N00E STY# internal pull up to UXIN LK_NEW_OE# follow M schematic +VS 0.U/0V_ EPRESS_PLTRST# SI- modified -- EPRESS_PLTRST# is VS power rail, Maybe can remove NN GTE EPRESS_PLTRST# U *TSH0FU R 0_ N_PLTRST# N/R PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom NEW R/ST O/ST H ate: Tuesday, February, 00 Sheet of E

34 POWER UTTON ONNET MY MY MY MY 0P/0V_ 0P/0V_ 0P/0V_ 0P/0V_ MY MY MY MY0 0P/0V_ MX 0P/0V_ 0P/0V_ MX0 0P/0V_ 0P/0V_ MX 0P/0V_ 0P/0V_ MX 0P/0V_ +PWLEV NSWON# G *SHORT_ P MY 0P/0V_ MX 0 0P/0V_ MY 0P/0V_ MY 0 0P/0V_ MX 0P/0V_ MY 0P/0V_ MY0 0 0P/0V_ MX 0P/0V_ MY 0P/0V_ MY 0P/0V_ MX 0 0P/0V_ MY 0P/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ dd R for +VPU +VPU +VPU_LE, LI_E# NSWON#, PWR_LE# 0.U/0V_ R *_ R _ +PWLEV PWR_LE# +VPU N PWR TN ONN. +VPU(LISWITH PWR). LEV(+VPU). LISWITH.POWERON#. PWRLE#. GN SI- Modified -- net swap for layout concern +VPU MY MY MY MY MY MY MY MY MY[0..] KEYOR PULL-UP MX[0..] RP 0 0K_0PR RP 0 0K_0PR MY[0..] MX[0..] MY0 MY MY MY MY0 MY MY MY MX MX MX MY MX MX MY0 MX MX MY MY MX0 MY MY MY MY MY MY MY MY MY MY MY0 MY N 0 0 K ONN gbrf0--f-p-l P SW ONNET el R0 on PV +V_LE 0.U/0V_ SI- Modified / 0 m.lev N.LEV. N. GN L-0R-TN L-0R-P-L-QT SI- Modified +VPU 0.U/0V_ +V_LE,, 0.U/0V_ MLK MT I_INT NUMLE# N P SW OR. +VPU. MLK. MT. P_INT. GN. NUM LOK LE. +V. ES_LK. ES_T P_ES_LK P_ES_T L L K0HS0 K0HS0 ES_LK ES_T 0 0P/0V_ 0P/0V_ PV modified: N update type dd L, L, 0, for ES el R0, R0 PROJET : QT Quanta omputer Inc. N/R Size ocument Number Rev ustom LE/KEYOR/SW ate: Tuesday, February, 00 Sheet of

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