r53_thames xt_si2_dis

Transcription

1 ard reader RTS-GRT / LN US. PG. PG. PG. PORT ITH PG. R M omal UM/Muxless SYSTEM IGRM PG. K PORT, US. combo Ports X PG. LN RTLE / SOIMM Max. G SOIMM Max. G PG. LN US. PI-E x LN WLN T OMO ccelerometer ITE EE PORT, K TP ROM FN PG. PG. SMUS R hannel R hannel US. PI-E x LP M Trinity PU mm X mm FSr socket pin upg TP W P Port M FH Hudson M/M.mm X.mm pin FG TP.W zalia M PG.~ UIO OE PG.~ UMI PI-E x ( ~ ) P Port P Port RT US. Ports X US. ST ST Speaker HP/MI nalog MI PG. PORT O H PG. PG. PG. TI THMES XT mm X mm TP W NX P to LVS Translator Webcam TOP PG. PG. PG. PORT PG.~ PG. RT LVS PG. HMI LVS R MHz VRM xx,bit PG. PG. PG., V/V.V/.VS PROJET : R Quanta omputer Inc. PG. PG..V/.V PG. V_ORE harger PG. VN_ORE PG..VSUS.V_VG.V_VG PG., PG. PG. ischarger Stackup TOP GN IN IN V OT VGore.V_VG V_VG PG. M Size ocument Number Rev ustom LOK EE IGRM ate: Tuesday, November, Sheet of

2 TO WLN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PIE_RXP_WLN PIE_RXN_WLN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN.V_VP / For omal. PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PIE_RXP_WLN PIE_RXN_WLN Move from PU to PH R UF E P_GPP_RXP E P_GPP_RXN P_GPP_RXP P_GPP_RXN P_GPP_RXP P_GPP_RXN P_GPP_RXP P_GPP_RXN G P_UMI_RXP G P_UMI_RXN G P_UMI_RXP G P_UMI_RXN F P_UMI_RXP F P_UMI_RXN E P_UMI_RXP E P_UMI_RXN /F_ P_ZVP G P_ZVP PI EXPRESS P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP Y P_GFX_RXN P_GFX_TXN Y Y P_GFX_RXP P_GFX_TXP Y Y P_GFX_RXN P_GFX_TXN Y W P_GFX_RXP P_GFX_TXP W W P_GFX_RXN P_GFX_TXN W W P_GFX_RXP P_GFX_TXP V W P_GFX_RXN P_GFX_TXN V V P_GFX_RXP P_GFX_TXP V V P_GFX_RXN P_GFX_TXN V U P_GFX_RXP P_GFX_TXP U U P_GFX_RXN P_GFX_TXN U U P_GFX_RXP P_GFX_TXP T U P_GFX_RXN P_GFX_TXN T T P_GFX_RXP P_GFX_TXP T T P_GFX_RXN P_GFX_TXN T R P_GFX_RXP P_GFX_TXP R R P_GFX_RXN P_GFX_TXN R R P_GFX_RXP P_GFX_TXP P R P_GFX_RXN P_GFX_TXN P P P_GFX_RXP P_GFX_TXP P P P_GFX_RXN P_GFX_TXN P N P_GFX_RXP P_GFX_TXP N N P_GFX_RXN P_GFX_TXN N N P_GFX_RXP P_GFX_TXP M N P_GFX_RXN P_GFX_TXN M M P_GFX_RXP P_GFX_TXP M M P_GFX_RXN P_GFX_TXN M Trinity PU GRPHIS GPP UMI-LINK P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN P_UMI_TXP G P_UMI_TXN G P_UMI_TXP F P_UMI_TXN F P_UMI_TXP F P_UMI_TXN F P_UMI_TXP E P_UMI_TXN E P_ZVSS H PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PIE_TXP_ PIE_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ P_ZVSS R /F_ UM can remove Move from PU to PH PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PIE_TXP_WLN PIE_TXN_WLN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN PEG X TO WLN TO PIE-LN TO PIE R REER HT onnector for ebug only V R *_/S R K/F_.V / For omal. R K/F_ VI Override ircuit SV SV OOT VOLTGE VFIX_V =V/GN VFIX_V =OPEN.., PU_RST#, PU_PWRG PU_RST# PU_PWRG U Y GN V Y LVG PU_RST_L_UF PU_PWROK_UF Note: To override VI,Remove Rd, Re, Rf, install Rc set VI via SV & SV option RES..VSUS.V PU_TI PU_TK PU_TMS PU_TRST# PU_REQ# close to HT debug HEER R R R R R K/F_ K/F_ K/F_ K/F_ K/F_ / For omal..vsus.vsus PU_TEST PU_TEST TP PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO PU_TEST PU_TEST PU_RST_L_UF PU_LT_RST_HTP# PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO PU_PWROK_UF J *HT ONN --p-l R *K/F_ Rd SV SV SV R _ PU_SV Re SV R _ PU_SV Rf PU_SV PU_SV Wait for power, PU_PWRG PU_PWRG R _ PU_PWRG_SVI_REG PU_PWRG_SVI_REG PU_PWRG have pull up ohm to.v on page R *K/F_ / For omal. for normal operation open Ra, Rb,Rc R *K_ R *K_ R *.K_ R R R */F_ */F_ */F_ Ra Rb Rc PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom Llano PIE/UMI/GPP ate: Monday, November, Sheet of

3 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M S# M S# M S# M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M S# M S# M S# M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M_ZVIO MEMVREF_PU MEMVREF MEMVREF_PU M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M KE M KE M OT M OT M S# M S# M RS# M RST# M S# M WE# M EVENT# M LKP M LKN M LKP M LKN M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M LKP M LKN M LKP M LKN M RS# M OT M OT M S# M RST# M WE# M EVENT# M KE M KE M S# M S# M Q[..] M Q[..] M M[..] M S#[..] M [:] M [:] M S#[..] M M[..] R_VTTREF,, MEMVREF_PU.VSUS.VSUS.VSUS VS.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R Llano R MEM I/F Monday, November, ustom Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R Llano R MEM I/F Monday, November, ustom Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R Llano R MEM I/F Monday, November, ustom Place close to PU within " Soldermask openings for all bottom side vias/tps under FS Reserved for M suggest Reserved / For omal. MEMORY HNNEL Trinity PU U MEMORY HNNEL Trinity PU U M_ZVIO W M_VREF W M_EVENT_L T M_RESET_L H M_WE_L W M_S_L W M_RS_L V M_S_L M_S_L V M_OT M_OT Y M_KE H M_KE H M_LK_L R M_LK_H R M_LK_L T M_LK_H T M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H E M_QS_L E M_QS_H E M_QS_L H M_QS_H J M_QS_L H M_QS_H G M_QS_L H M_QS_H G M_M M_M M_M M_M M_M F M_M E M_M J M_M E M_NK L M_NK U M_NK U M_ L M_ L M_ M_ L M_ M M_ U M_ M M_ N M_ N M_ N M_ N M_ P M_ P M_ R M_ U M_T Y M_T M_T M_T Y M_T M_T M_T Y M_T M_T M_T M_T Y M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T Y M_T M_T Y M_T M_T M_T M_T E M_T M_T M_T M_T M_T F M_T E M_T H M_T F M_T G M_T G M_T E M_T G M_T H M_T G M_T E M_T G M_T H M_T J M_T F M_T H M_T F M_T H M_T H M_T G M_T J M_T E M_T F M_T H M_T E M_T F M_T F M_T H M_T J M_T H M_T J M_T E M_ R R *_ R *_ P/V_ P/V_ R *K/F_ R *K/F_ R *_ R *_ R K/F_ R K/F_ R K/F_ R K/F_ R./F_ R./F_ P/V_ P/V_ R *_ R *_ R K/F_ R K/F_ R *_ R *_ P/V_ P/V_ - U *OPN/K - U *OPN/K * * R _ R _ MEMORY HNNEL Trinity PU U MEMORY HNNEL Trinity PU U M_EVENT_L T M_RESET_L J M_WE_L V M_S_L V M_RS_L V M_S_L Y M_S_L V M_OT Y M_OT W M_KE J M_KE J M_LK_L P M_LK_H P M_LK_L R M_LK_H R M_QS_L G M_QS_H H M_QS_L G M_QS_H G M_QS_L F M_QS_H G M_QS_L G M_QS_H G M_QS_L M_QS_H M_QS_L M_QS_H E M_QS_L M_QS_H E M_QS_L M_QS_H M_M M_M H M_M G M_M F M_M M_M M_M M_M M_NK K M_NK T M_NK U M_ K M_ K M_ W M_ K M_ L M_ U M_ L M_ M M_ M M_ M M_ M M_ N M_ N M_ P M_ P M_ T M_T F M_T E M_T F M_T G M_T M_T G M_T M_T G M_T M_T F M_T G M_T G M_T H M_T E M_T E M_T F M_T M_T M_T M_T M_T H M_T E M_T H M_T E M_T E M_T H M_T F M_T G M_T G M_T F M_T H M_T G M_T M_T M_T M_T M_T M_T M_T M_T E M_T M_T E M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T E M_T M_T M_T M_T M_T M_T M_T M_T M_T E M_T M_T M_T R K/F_ R K/F_ P/V_ P/V_ *.U/.V_ *.U/.V_

4 FH_THERMTRIP# Q *MENE Q MMT--F RV- EPWROK SMLERT# P output to ep to LVS converter P output to Hudson-M for VG translator interface / HMI change to P for omal. note --HMI P&N can not swap Note: LK_PU_HLKP/N is MHZ SS Note: LK_P_NSSP/N is MHZ non-ss Thermal P output to HMI connector Q MMT--F.VSUS _RST# _TX_HMI _TX_HMI- _TX_HMI _TX_HMI- _TX_HMI _TX_HMI- _TX_HMI _TX_HMI- PU_THERMTRIP# THERMTRIP# shutdown temperature 寬 R R R K/F_ *RV- INT_eP_TXP INT_eP_TXN INT_eP_TXP INT_eP_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN LK_PU_P LK_PU_N LK_P_P LK_P_N SV SV, PU_RST#, PU_PWRG PU_TI PU_TO PU_TK PU_TMS PU_TRST# PU_RY PU_REQ# PU_V_RUN_F_L VP_F_H PU_VN_RUN_F_H VIO_F_H PU_V_RUN_F_H V VG_LERT VG TEMP_ FIL function is active Hi *K/F_ R K/F_ K/F_ isplay port power.v min.v max :.v TP TP TP TP _RST# PU_SVT / For omal, close to PU. EPWROK,, HWPG,,,,, _TX_HMI _TX_HMI- _TX_HMI _TX_HMI- _TX_HMI _TX_HMI- _TX_HMI _TX_HMI-.V.V.V.VSUS Place caps with PU < inch U route PIE as ohm /- % NLOG/ISPLY/MIS INT_eP_TXP_ L INT_eP_UXP_ INT_eP_TXN_ P_TXP P_UXP L INT_eP_UXN_ P_TXN P_UXN / For omal. R R R *K/F_ R _ R /_ K/F_ INT_eP_TXP_ INT_eP_TXN_ PU_P_TXP_ PU_P_TXN_ PU_P_TXP_ PU_P_TXN_ PU_P_TXP_ PU_P_TXN_ PU_P_TXP_ PU_P_TXN_ LK_PU_P LK_PU_N LK_P_P LK_P_N SV SV PU_ PU_ PU_RST# PU_PWRG PU_PROHOT# PU_THERMTRIP# PU_LERT PU_TI PU_TO PU_TK PU_TMS PV change to short-pad PU_TRST# PU_RY / For omal. PU_REQ# R /_ *_/S SMLERT# TP TP PEG_HMI_TXP PEG_HMI_TXN PEG_HMI_TXP PEG_HMI_TXN PEG_HMI_TXP PEG_HMI_TXN PEG_HMI_TXP PEG_HMI_TXN PU_SVT_R FH_PROHOT# H_PROHOT# R K/F_ TP TP VSS_SENSE VP_F_H PU_VN_RUN_F_H VIO_F_H PU_V_RUN_F_H VP_F_H VPU PU_PROHOT# 可可可 input or output 可 Low 時 PU 會會 P - STTE VPU R over degree = Low to E reserve only P/V_ *U/.V_ K P_TXP K P_TXN K P_TXP K P_TXN J P_TXP J P_TXN H P_TXP H P_TXN H P_TXP H P_TXN G P_TXP G P_TXN F P_TXP F P_TXN L P_TXP L P_TXN L P_TXP L P_TXN K P_TXP K P_TXN J P_TXP J P_TXN E LKIN_H LKIN_L ISP_LKIN_H ISP_LKIN_L SV SV SVT G H F RESET_L PWROK PROHOT_L E THERMTRIP_L F LERT_L H TI J TO F TK G TMS F TRST_L G RY H REQ_L VSS_SENSE VP_SENSE VN_SENSE VIO_SENSE V_SENSE VR_SENSE *_/S R _ R ISPLY PORT ISPLY PORT ISPLY PORT JTG TRL SER. LK SENSE Trinity PU U *G V RSV PU_PROHOT# GN *_/S OT OT TMSNS RHYST TMSNS RHYST TEST ISPLY PORT MIS. P_UXP E P_UXN E P_UXP P_UXN P_UXP E P_UXN E P_UXP F P_UXN F P_UXP G P_UXN G P_HP P_HP E P_HP P_HP E P_HP F P_HP G P_LON P_IGON P_VRY_L P_UX_ZVSS TEST TEST M TEST N TEST F TEST G TEST H TEST J TEST F TEST G TEST J TEST H TEST_H E TEST_L TEST_H L TEST_L M TEST_H P TEST_L R TEST K TEST_H T TEST_L N TEST FSR W MTIVE_L.V RSV_ Y RSV_ RSV_ Y RSV_ K.VSUS When K-NT =.K Thermal Trip = R PU_P_UXP_ PU_P_UXN_ INT_HMI_UXP INT_HMI_UXN isplay port power.v min.v max :.v FH_LVS_HP FH_VG_HP HMI_HP_Q PU_LEN PU_IGON P_UX_ZVSS R PU_TEST PU_TEST PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST PU_TEST PU_TEST_SNLK PU_TEST_SNLK PU_TEST_H PU_TEST_L PU_TEST_H PU_TEST_L M_TEST PU_TEST FSR R MTIVE_L PU_THERM TEST P PU_THERM TEST R M internal test only R *K/F_, PU SUS power meet M design R K/F_ VRHOT K/F_ reserve for leakage current verify R R *.K/F_ *.K/F_ R *K_ NT *.K/F_ /F_ TP TP TP TP TP TP TP TP TP TP TP TP TP TP VS R R.V INT_eP_UXP INT_eP_UXN PU_P_UXP PU_P_UXN INT_HMI_UXP INT_HMI_UXN FH_LVS_HP FH_VG_HP HMI_HP_Q PU_LEN PU_IGON PU_LPWM,M no concern so remove TP, TP,TP,TP,TP PU_TEST PU_TEST MTIVE_L controls entry and exit from the sleep and power states MTIVE_L *K/F_.V K/F_.VSUS PU_PROHOT#, MLK, MT INT_eP_UXP R *K/F_ LVS INT_eP_UXN R *K/F_ V VG HMI To M HT FSR signals is for detect PU TYPE and protect it. FSR PU this pin is N. FSR PU this pin is LOW can remove it at MP Q *MMT--F / For omal. dd R for verify this solution R *.K/F_ R *K/F_ R _ R *K_ NT MLK MT M_TEST INT_eP_UXP_ INT_eP_UXN_ PU_P_UXP PU_P_UXN PU_P_UXP_ PU_P_UXN_ M_TEST ONNETION T.VSUS PU_TEST_L PU_TEST PU_TEST PU_TEST PU_TEST_SNLK PU_TEST_SNLK PU_TEST_H Q MMT--F RV-.VSUS Q MMT--F R R R R R R R *./F_ R./F_ R K/F_ RV- PU_TEST / For omal. PU_ PU_ V TEST PU FOR INTERNL TEST P FOR USTOMER.VSUS.VSUS.V PROJET : R Quanta omputer Inc. R Size ocument Number Rev Llano isplay/misc / For omal. R *_ Monday, November ate:, Sheet of.k_ K/F_ K/F_ R _ R K/F_.K_.K_.K_ R K/F_ R K/F_ R K/F_ R K/F_ R _ R K/F_ R K/F_ R /_ R */_

5 PIN NME V VN PU POWER TLE NET NME V_ORE VN_ORE VOLTGE.V?? EMI suggestion V_ORE VIO VP VR V.V.VSUS.V_VP.V_VR.V_V.V.V.V.V, change to u for improve VN_ORE transient.u/v_.u/v_ / For omal. U/.VS_ / For omal. U/.VS_ VN_ORE / For omal. VN_P. Up to VIO.U/V_ R U/.VS_.U/V_.U/V_.V_VP VP = *_/S U/.VS_ P/V_ P/V_ U/.VS_ U/.VS_ P/V_.U/V_ P/V_.U/V_.V_VP VN_ORE.VSUS / For omal. U/.V_ U/.V_ U/.V_.U/V_ P/V_ V_ORE U F V_ H V_ J V_ J V_ P V_ P V_ J V_ J V_ J V_ K V_ K V_ K V_ M V_ K V_ V V_ V V_ V V_ F V_ L V_ V V_ W V_ T V_ Y V_ V_ V_ V_ R V_ P V_ K V_ H V_ M V_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ E VN_ E VN_ VN_ H VIO_ K VIO_ J VIO_ K VIO_ K VIO_ L VIO_ L VIO_ L VIO_ M VIO_ M VIO_ M VIO_ N VIO_ N VIO_ N VIO_ P VIO_ P VIO_ P VIO_ VIO_ H VP H VP H VP H VP H VP V V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_P VN_P VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VR VR VR VR R T H G U W W W W W E L Y M N N T T U U Y Y Y F F F L E K K T T U U U Y T R R R V V V W W W Y G G H H H V_ORE U/.V_ U/.V_.U/V_ Maximum INspike VN_ORE VN_P.VSUS U/.VS_.V_VR_, change to u for M E dynamic test, Maximum Ispike U/.V_.U/V_ U/.V_ P/V_ EOUPLING between PROESSOR and IMMs cross VIO and VSS split U/.VS_.VSUS.U/V_ / For omal. / For omal. If the VSS plane is cut to create a VIO plane, ceramic capacitors are connected across the VIO and VSS plane split as follows VR =. ( Up to ) U/.V_ U/.VS_ U/.V_ U/.VS_ U/.VS_ U/.V_ R U/.V_ U/.VS_ P/V_ *_/S U/.V_ U/.VS_.U/V_.U/V_ U/.VS_.V.U/V_ P/V_.U/.V_.U/.V_ P/V_.U/V_ P/V_.U/.V_ *P/V_.U/.V_ *P/V_ UE J VSS_ VSS_ L VSS_ VSS_ R VSS_ VSS_ W VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ VSS_ F VSS_ VSS_ H VSS_ VSS_ H VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ VSS_ E VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ K VSS_ VSS_ K VSS_ VSS_ K VSS_ VSS_ VSS_ VSS_ L VSS_ VSS_ L VSS_ VSS_ M VSS_ VSS_ F VSS_ VSS_ V VSS_ VSS_ V VSS_ VSS_ W VSS_ VSS_ W VSS_ VSS_ W VSS_ VSS_ Y VSS_ VSS_ Y VSS_ VSS_ Y VSS_ VSS_ Y VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ K VSS_ VSS_ F VSS_ VSS_ G VSS_ VSS_ H VSS_ VSS_ J VSS_ Trinity PU E E E M N N N R R T T U U U U V E E E E E E F F F F F F F F G G H H H H H P W P E K W.U/.V_.U/.V_ P/V_ P/V_ Trinity PU.U/.V_.U/V_ P/V_ P/V_ P/V_.V L PYT-Y-N(,) V=..V_V.U/.V_.U/V_ P/V_ PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom Llano POWER/GN ate: Friday, November, Sheet of

6 VS VS R R R V VS Z_SOUT_R Z_SYN_R Z_LK_R Z_RST#_R Z_N N,no install by default R R R R R R R R R R R VG_REQ *.K_ *.K_ *.K_ FH_TEST FH_TEST FH_TEST.K_ GLK_SM to R SMUS.K_ GT_SM, change power rail from V to VS *K_ J SYS_RST# SYS_RST# internal *SOLERJUMPER- K pull up K/F_ K/F_.K_.K_.K_.K_ *.K_ *.U/V_ K/F_ SL S SL S SL S FH_THERMTRIP# NSWON# To zalia R _ R _ R _ R _ Pure UM can remove RV- Z_SOUT_UIO Z_SYN_UIO IT_LK_UIO Z_RST#_UIO Z_N LK_REQ# already internal pull up.k LKREQ# GEVENT# internal pull Hi.K to V GEVENT# internal pull Hi.K to V GEVENT# internal pull Hi.K to V GEVENT# internal pull Hi.K to VS PIE_WKE# no need to pull Hi resistor from check list LK_REQ# internal pull Hi.K to V LK_REQ# internal pull Hi.K to V LK_REQ# internal pull Hi.K to V, HP request Image sensor SMUS reserve to FH This pin is used to power down VG regulators when RT no connected GEVENT# internal pull Hi.K to VS GEVENT# internal pull Hi.K to VS SUS# SUS# NSWON# FH_PWRG E_GTE E_RIN# O_EXT_SMI# O_EXT_#, PIE_WKE# FH_THERMTRIP# V RSMRST# PIE_R_LKREQ# PIE_LN_LKREQ# Z_SPKR, GLK_SM, GT_SM SL S PIE_MINI_LKREQ# O_PLUGIN# O_#_FH / For omal. For Zero O H audio interface is V_S voltage remove PIE_RST# from M recommend / For omal. Remove ard EES function form Vendor mail T_OMO_OFF# R R R R R R R R TP TP TP TP TP TP TP TP TP TP TP TP TP VG_RST VG_ON_S PIE_RST# RI# SUS# SUS# NSWON# FH_PWRG FH_TEST FH_TEST FH_TEST E_GTE T T V E E_RIN# G FH_PME# R O_EXT_SMI# *_/S GEVENT# T SYS_RST# U PIE_WKE# K *P/V_ V FH_THERMTRIP# R K/F_ W_PWRG F RSMRST# PIE_R_LKREQ# PIE_LN_LKREQ# *_/S LL# Not Implemented,left unconnected. TP TP R _ VG_POWER_OWN TP FH_GPIO GLK_SM GT_SM SL S PIE_MINI_LKREQ# LKREQ# LL# SMRTVOLT VG_P GE_LE O_PLUGIN# O_#_FH FH_JTG_TK FH_JTG_TI FH_JTG_RST# *K/F_ Z_LK_R Z_SOUT_R *K/F_ Z_N *K/F_ Z_N *K/F_ Z_N_R *K/F_ Z_N_R Z_SYN_R Z_RST#_R T_OMO_OFF# VG_RST VG_ON_S R W T W J N U G E E F H G F T R G G J G V W Y V F M R T P F P J T Y Y Y E K J J F E F E J H G K U PIE_RST#/GEVENT# RI#/GEVENT# SPI_S#/GE_STT/GEVENT# SLP_S# SLP_S# PWR_TN# PWR_GOO HUSON-M Part of TEST TEST/TMS TEST GIN/GEVENT# KRST#/GEVENT# PME#/GEVENT# LP_SMI#/GEVENT# LP_P#/GEVENT# SYS_RESET#/GEVENT# WKE#/GEVENT# IR_RX/GEVENT# THRMTRIP#/SMLERT#/GEVENT# W_PWRG RSMRST# LK_REQ#/ST_IS#/GPIO LK_REQ#/ST_IS#/GPIO SMRTVOLT/ST_IS#/GPIO LK_REQ#/ST_IS#/GPIO ST_IS#/FNOUT/GPIO ST_IS#/FNIN/GPIO SPKR/GPIO SL/GPIO S/GPIO SL/GPIO S/GPIO LK_REQ#/FNIN/GPIO LK_REQ#/FNOUT/GPIO IR_LE#/LL#/GPIO SMRTVOLT/SHUTOWN#/GPIO R_RST#/GEVENT#/VG_P GE_LE/GPIO SPI_HOL#/GE_LE/GEVENT# GE_LE/GEVENT# GE_STT/GEVENT# LK_REQG#/GPIO/ON/ILEEXIT# LINK/US_O#/GEVENT# US_O#/IR_TX/GEVENT# US_O#/IR_TX/GEVENT# US_O#/IR_RX/GEVENT# US_O#/_PRES/TO/GEVENT# US_O#/TK/GEVENT# US_O#/TI/GEVENT# US_O#/SPI_TPM_S#/TRST#/GEVENT# Z_ITLK Z_SOUT Z_N/GPIO Z_N/GPIO Z_N/GPIO Z_N/GPIO Z_SYN Z_RST# H UIO GPIO US O USLK/M_M_M_OS US_ROMP US MIS PI / WKE UP EVENTS US. US. US_SS_TXP PS_T/S/GPIO US_SS_TXN PS_LK/E/SL/GPIO SPI_S#/GE_STT/GPIO US_SS_RXP US_SS_RXN PSK_T/GPIO US_SS_TXP PSK_LK/GPIO US_SS_TXN PSM_T/GPIO PSM_LK/GPIO US_SS_RXP US_SS_RXN KSO_/GPIO KSO_/GPIO SL/GPIO KSO_/GPIO S/GPIO KSO_/GPIO SL_LV/GPIO KSO_/GPIO S_LV/GPIO KSO_/GPIO E_PWM/E_TIMER/GPIO KSO_/GPIO E_PWM/E_TIMER/GPIO KSO_/GPIO E_PWM/E_TIMER/WOL_EN/GPIO KSO_/GPIO E_PWM/E_TIMER/GPIO KSO_/GPIO KSO_/GPIO EMEE K_/GPIO KSO_/GPIO K_/GPIO TRL KSO_/GPIO K_/GPIO KSO_/GPIO K_/GPIO KSO_/X/GPIO K_/GPIO KSO_/X/GPIO K_/GPIO KSO_/X/GPIO K_/GPIO KSO_/X/GPIO K_/GPIO US. US_FSP/GPIO US_FSN US_FSP/GPIO US_FSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN USSS_LRP USSS_LRN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN US_SS_TXP US_SS_TXN US_SS_RXP US_SS_RXN G H H H H H G K J G F K K E F H G F E E E E F F G H G J H J K H G G G E H J H K K F F E F US_ROMP_S USP USP- USP USP- USP USP- USSS_LRP USSS_LRN SL S SL S E_PWM R R R No need for GPIO USP USP- USP USP- USP USP- TP TP.K/F_ USP USP- USP USP- K/F_ K/F_ US. Not Implemented: left unconnected. US_TX US_TX- US_RX US_RX- US_TX US_TX- US_RX US_RX- E_PWM WLN Min-ard amera US FH_V SSUS_S Left side US ombo./.. Left side US ombo./.. Right side US. onnector SL of a T-capable PU's thermal bus,pulled up to PU_VIO. Resistor value verified in the relevant PU design guide. Hudson-M- PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom Hudson-M GPIO/US/Z/RGMII ate: Friday, November, Sheet of

7 R_PIE_RST# MINI_PIE_RST# LK_PIE_LNP LK_PIE_LNN P/V_ P/V_ P/V_, LN_PIE_RST# R _ PIE_RST# E _RST# PI_LK GPU_RST# R _ PIE_RST# PILK F _RST# Part of PILK/GPO F PI_LK P/V_ UMI_RXP_ PI_LK UMI_RXP PILK/GPO F E PI_LK UMI_RXN UMI_RXN_ UMI_TXP PILK/GPO G E PI_LK PI_LK UMI_RXP_ UMI_RXP UMI_TXN PILK/M_OS/GPO F Place these PIE UMI_RXN UMI_RXN_ UMI_TXP PIRST#_L R _ K_RST# UMI_RXP UMI_RXP_ UMI_TXN PIRST# *P/V_ coupling cap close to FH UMI_RXN UMI_RXN_ UMI_TXP UMI_RXP_ UMI_RXP UMI_TXN K_RST# UMI_RXN_ UMI_RXN UMI_TXP /GPIO J UMI_TXN /GPIO L /GPIO G UMI_TXP UMI_RXP /GPIO L UMI_TXN UMI_RXN /GPIO H UMI_TXP UMI_RXP /GPIO J UMI_TXN UMI_RXN /GPIO L UMI_TXP Y UMI_RXP /GPIO N UMI_TXN Y UMI_RXN /GPIO N UMI_TXP Y UMI_RXP /GPIO J UMI_TXN Y UMI_RXN /GPIO L PIE_LRP_FH /GPIO L R /F_ F.V_PIE_VR R K/F_ PIE_LRN_FH PIE_LRP /GPIO M F PIE_LRN /GPIO J PIE_TXP_R PIE_TXP_R_ /GPIO K V PIE_TXN_R_ PIE_TXN_R GPP_TXP /GPIO N V PIE_TXP_LN PIE_TXP_ GPP_TXN /GPIO G W PIE_TXN_ PIE_TXN_LN GPP_TXP /GPIO M W GPP_TXN /GPIO J GPP_TXP /GPIO L, PIE port change GPP_TXN /GPIO K from port to port GPP_TXP /GPIO N GPP_TXN /GPIO G PI_ PI_ PIE_RXP_R /GPIO E PI_ PIE_RXP_R PI_ PIE_RXN_R GPP_RXP /GPIO PI_ PIE_RXN_R PI_ PIE_RXP_LN GPP_RXN /GPIO E PI_ PIE_RXP_LN W PI_ PIE_RXN_LN GPP_RXP /GPIO F PI_ PIE_RXN_LN V GPP_RXN /GPIO H PI_ V GPP_RXP /GPIO H GPU_PWROK,,,, W HUSON_MEMHOT#_R GPP_RXN /GPIO TP W GPP_RXP /GPIO W GPP_RXN /GPIO E E# N E# J V_RT LK_LRN_FH.V_KV R K/F_ E# N F LK_LRN E# FRME# G MIL R EVSEL# K, change to Ω & Ω G PIE_RLKP IRY# L for Rise/Fall time issue G PIE_RLKN TRY# F LK_P_FH_P LK_P_P RP X PR E R LK_P_FH_N ISP_LKP STOP# H LK_P_N T ISP_LKN PERR# M PI_SERR# U/.V_ LK_NX_FH_P SERR# H LK_NX_P RP X H LK_NX_N LK_NX_FH_N ISP_LKP REQ# G H, M request ISP_LKN REQ#/GPIO G P/V_ test point LK_PU_FH_P REQ#/LK_REQ#/GPIO F LK_PU_P RP X T TP LK_PU_N LK_PU_FH_N PU_LKP REQ#/LK_REQ#/GPIO M TP T PU_LKN GNT# FH_GPIO R *_ SPI_WP Pure UM LK_VG_FH_P GNT#/GPO LK_VG_P RP X J LK_VG_FH_N SLT_GFX_LKP GNT#/S_LE/GPO TP can remove LK_VG_N K SLT_GFX_LKN GNT#/LK_REQ#/GPIO K TP LKRUN# LKRUN# LK_WLN_FH_P LKRUN# LK_WLN_P RP X H TP LK_WLN_N LK_WLN_FH_N GPP_LKP LOK# H H GPP_LKN LK_PIE_RP_FH TRVIS_EN# LK_PIE_R_P RP X INTE#/GPIO F TP J TP LK_PIE_R_N LK_PIE_RN_FH GPP_LKP INTF#/GPIO E K GPP_LKN INTG#/GPIO TP EL_INT EL_INT dd G-sensor signal INTH#/GPIO F GPP_LKP F LP_LK GPP_LKN LP_LK LP_LK LP_LK Note: LK_FH_SRP/N is MHZ SS E GPP_LKP E R LMSN(,M) GPP_LKN LPLK P/V_ Note: LK_PIE_TRVISP/N is MHZ non-ss P/V_ LPLK R _ M L GPP_LKP L L, Note: LK_P_NSSP/N is MHZ non-ss M L GPP_LKN L L, L Note: LK_PU_HLKP/N is MHZ SS L L, M L GPP_LKP L L, Note: LK_PIE_VGP/N is MHZ SS M LFRME# GPP_LKN LFRME# LFRME#, Note: GPP_LK(:)P/N is MHZ SS capable LRQ# LRQ# TP N LRQ# GPP_LKP LRQ#/LK_REQ#/GPIO E TP N SERIRQ GPP_LKN SERIRQ/GPIO E SERIRQ FH PROHOT#--- (input.v threshold ) When it isasserted, it can generate or R GPP_LKP R SMI to OS/IOS GPP_LKN PV change to short-pad P/V_ P/V_ RP Y MHZ R _ R _ R M/F_ X TP TP LK_PIE_LNP_FH LK_PIE_LNN_FH M_X M_X J UE N GPP_LKP R GPP_LKN M_M_M_OS M_X M_X Hudson-M- HUSON-M PI EXPRESS INTERFES LOK GENERTOR PI LKS PU S PLUS PI INTERFE LP M_TIVE# G PROHOT# E PU_PG E LT_STP# G PU_RST# F S_ORE_EN H RTLK F INTRUER_LERT# F VT_RT_G E K_X K_X G G MTIVE_L FH_PROHOT# PU_PWRG_R PU_STOP# PU_RST# K_X K_X S_ORE_EN LK_RT INTRUER_LERT# V_RT MIL G *SHORT_ P MTIVE_L R TP PU_RST#, TP TP *_/S LK_RT V_RT FH_PROHOT# PU_PWRG, LT_STP# let is N from schematic recommend INTRUER_LERT# Left not connected (FH has -kohm internal pull-up to VT). MIL /F_ VRT_, change R value from ohm to ohm LK EUG, change for EMI LK_M_K K_X R M_ K_X R _ VRT USE GROUN GUR FOR K_X N K_X S_ORE_EN is necessary to connect enable pin of VPU/VPU regulator for S mode implementation MIL Y.KHZ RV- RV- P/V_ MIL MIL N -L ate: Monday, November, Sheet of VRT_ T VPU PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom Hudson-M PI/PI/LOK P/V_ R K/F_

8 UM ST_LE# I I I I I ONFIG - Level OM Item N K H Hudson-M- U VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P VSS_ R VSS_ R VSS_ R VSS_ R VSS_ T VSS_ T VSS_ T VSS_ VSSN_HWM VSSXL VSSPL_SYS HUSON-M Part of GROUN VSS_ T VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ V VSS_ V VSS_ V VSS_ W VSS_ W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ L VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSSPL_ T VSSN_ L VSSNQ_ K VSO_ N EFUSE R ST H ST O U *MVHGFTG.V_V_ST GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V GPIO internal pull Hi.K to V / For omal. V ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP V R _ PLE ST OUPLING PS LOSE TO HUSON-M/M RF_OFF# TP T_OMO_EN# O_PWR _LE# L_K E_PORT_I S_ST_LE# ST_TXP ST_TXN ST_TXP ST_TXN PLE ST_L RES VERY LOSE TO LL OF HUSON-M/M R R R * K/F_ /F_ ST_LRP ST_LRN */F_ S_ST_LE# Integrated lock Mode: Leave unconnected. dd GPIO for G-sensor LE control R K/F_ R K/F_ RF_OFF# T_OFF# T_OMO_EN# O_PWR L_K E_PORT_I R K/F_ R K/F_ F G E_PORT_I U K ST_TXP M ST_TXN L ST_RXN N ST_RXP N ST_TXP L ST_TXN H ST_RXN J ST_RXP J ST_TXP H ST_TXN M ST_RXN K ST_RXP H ST_TXP J ST_TXN N ST_RXN L ST_RXP L ST_TXP N ST_TXN J ST_RXN H ST_RXP N ST_TXP L ST_TXN K ST_RXN M ST_RXP L N N N L N L N F ST_LRP F ST_LRN H FNOUT/GPIO M FNOUT/GPIO J FNOUT/GPIO K FNIN/GPIO N FNIN/GPIO L FNIN/GPIO H N H N J N J N ST_T#/GPIO ST_X ST_X Hudson-M- HUSON-M SERIL T TEMPIN K TEMPIN TEMPIN/GPIO K TEMPIN TEMPIN/GPIO K TEMPIN TEMPIN/GPIO M TEMPIN/TLERT#/GPIO S R TEMP( - ) Temp Monitor Not Implemented -KΩ % pull-up to VS or -KΩ % pull-down Samsung VG VG MINLINK HW MONITOR SPI ROM GE LN Part of S_LK/SLK_/GPIO L S_M/SLO_/GPIO N S_#/GPIO J S_WP/GPIO H S_T/STI_/GPIO K S_T/STO_/GPIO M S_T/GPIO H S_T/GPIO J VIN/GPIO N VIN/GPIO M VIN/STI_/GPIO L VIN/STO_/GPIO N VIN/SLO_/GPIO P VIN/SLK_/GPIO P VIN/GE_STT/GPIO M VIN/GE_LE/GPIO M VS GE_OL GE_RS GE_MK GE_MIO W GE_RXLK GE_RX H GE_RX F GE_RX E GE_RX GE_RXTL/RXV G GE_RXERR GE_TXLK GE_TX F GE_TX G GE_TX E GE_TX GE_TXTL/TXEN GE_PHY_P GE_PHY_RST# GE_PHY_INTR W SPI_I/GPIO V SPI_O/GPIO V SPI_LK/GPIO V SPI_S#/GPIO T ROM_RST#/SPI_WP#/GPIO V VG_RE VG_GREEN VG_LUE VG_HSYN/GPO M VG_VSYN/GPO N VG S/GPO M VG SL/GPO N VG RSET UX_VG_H_P V UX_VG_H_N V UXL ML_VG_LP T ML_VG_LN T ML_VG_LP T ML_VG_LN T ML_VG_LP R ML_VG_LN R ML_VG_LP P ML_VG_LN P ML_VG_HP/GPIO R R R R R L L M K U N G N H N N G N L K/F_ *K/F_ *K/F_ *K/F_ *K/F_ GE_OL GE_RS GE_MIO / for omal. GE_RXERR GE_PHY_INTR SPI_ SPI_SO SPI_LK SPI_S# FH_SPI_WP FH_RT_R FH_RT_G FH_RT_ VG REST UXL VG_HP IT need TP size test point E_PORT_I E_PORT_I E_PORT_I OR_I OR_I OR_I OR_I OR_I OR_I OR_I OR_I OR_I OR_I R R R R R R R R R *_/S FH_RT_HSYN FH_RT_VSYN FH_T FH_LK PU_P_UXP PU_P_UXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN VIN ( - ) Voltage Monitor Not Implemented -KΩ % pull-up to VS or -KΩ % pull-down FH_VG_HP VS VS TP E_IOS_S# TP E_IOS_SPI_LK_I TP E_IOS_WR# TP E_IOS_R# TP SPI_WP R R R R R R R *_/S *_/S *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ K/F_ *K/F_ K/F_ K/F_ K/F_ K/F_ /F_ /F_ SPI_LK FH_RT_RE FH_RT_GRE FH_RT_LU FH_VN R EMI Vender FH_VG_HP MI WINON Socket *P/V_ FH_RT_R FH_RT_G FH_RT_ FH_VN ML, Q,Q change to dual type MOS Q ual V VS *K/F_ R place close to PH Size M M R _ SPI_S# R _ SPI_LK R R _ SPI_SO _ SPI_ R R K/F_ *_ FH_VG_HP R K/F_ Q FH SPI ROM V P/N KEZN V VG Hot-plug NW--F ual KEFPN FHSFS, change power rail from V to VS U E# V SK SO HOL# R R R WP# *MXLMI-G R R * VSS /F_ /F_ /F_ V VG_HP Reserve for debug R K/F_ Q *_ NW--F VG_HP R *K/F_ R K/F_ SG / Muxless Hynix N no supprot side port R R R K/F_ K/F_ *K/F_ E_PORT_I R E_PORT_I R E_PORT_I R *K/F_ *K/F_ K/F_ PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom Hudson-M ST/HWM/SPI ate: Friday, November, Sheet of

9 V V V, add for leakage issue V,,,, MINON L PYT-Y-N(,) L PYT-Y-N(,) NOTE : LO_P stepping : will install nf cap stepping : will let it to N L PYT-Y-N(,).U/.V_ VPL_.V R _ Q.U/.V_ TRE WITH >=mil * TRE WITH >=mil FH_VN ML.U/.V_ *O *.V_VIO VQ--.V I/O power M chipset need to connect to GN M remove FH_VN R VPL_.V FH_VPL ML VPL SYS VPL *_ FH_VPL SSUS_S FH_VPL SUS_S FH_VPL PIE FH_VPL ST FH_VN VN ML -- UMI.V analog power FH_VN ML VPL US_S : US PHY PLL analog power V_V_US L PYT-Y-N(,) U/.V_.U/.V_.U/.V_ m U/.VS_ R FH_VPL SUS_S m m m m m m m m m m V PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSLE. U *P/V_ LO_P M LO_P U/.V_ HUSON-M Part of VIO PIGP_ VIO PIGP_ E VIO PIGP_ VIO PIGP_ G VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ H VPL SYS V VPL U VPL ML T VN L VPL SSUS_S VPL US_S H VPL PIE G VPL ST VPL Y VN ML_ V VN ML_ V VN ML_ V VN ML_ VIO GE_S VR GE_S_ VR GE_S_ VIO_GE_S_ VIO_GE_S_ PI/GPIO I/O MIN GE LINK PI LN EXPRESS LKGEN I/O SERIL T ORE S m for M.V_VR m for M VR-- S/ ORE power TRE WITH >=mil VR T.V VR T VR T VR U VR U U/.V_ U/.V_ U/.V_ VR V VR V R _ VR V.V_KV VR Y Q m VN LK-- Internal clock *O VN LK_ H Generator I/O power TRE WITH >=mil VN LK_ J VN LK_ K VN LK_ L VN LK_ M VN LK_ N U/.V_ U/.V_ U/.VS_ VN LK_ N VN LK_ P.V_PIE_VR m VN PIE --PIE/UMI analog power TRE WITH >=mil VN PIE_ L.V VN PIE_ Y LMPGSN(,.)_ VN PIE_ E VN PIE_ VN PIE_ U/.V_ U/.V_ U/.VS_.VS VN PIE_ VN PIE_ F.V_V_ST VN PIE_ G m VN ST--ST PHY analog/io power TRE WITH >=mil VN ST_ L.V VN ST_ Y LMPGSN(,.)_ VN ST_ VN ST_ if support US VN ST_ U/.V_ U/.V_ U/.VS_. wake up VN ST_ should be VN ST_ change pull hi VN ST_ VN ST_ to S power VN ST_ VS Reserve for VN L leakage current issue L.V LMPGSN(,.)_ MINON,,,, VPL_.V VN_.V_HWM VPL SYS_S : System lock Gen PLLs analog power L PYT-Y-N(,) VN HWM_S -- Hardware monitor interface I/O power L PYT-Y-N(,).U/.V_.VS VN US_S : US PHY I/O analog power.vs VR US_S : US PHY core power.vs VS VS VN US_S : US PHY PLL analog power M chipset need to stuff for support US. L PYT-Y-N(,) R M chipset need to connect to GN M remove if support Modem wake up should be change pull hi to S power L *_ L PYT-Y-N(,) U/.V_.U/.V_ PYT-Y-N(,), M SR tool review need one more.u PYT-Y-N(,), M SR tool review FH_V SSUS_S R FH_VPL SSUS_S M chipset need to stuff for support US. V_V_US TRE WITH >=mil m FH_VN US_S m.u/.v_ TRE WITH >=mil m FH_VR US_S TRE WITH >=mil m FH_VN SSUS_S_R VN SSUS_S : US. PHY PLL analog power V FH_VR SSUS_S VR SSUS_S : US. PHY core power M chipset need to stuff for support US. L PYT-Y-N(,) R L *_/S *_/S U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ R U/.V_ *_/S VIO_Z_S -- H udio Interface I/O power U/.V_ VIO_Z U/.V_ m.u/.v_ G VN US_S_ H VN US_S_ J VN US_S_ K VN US_S_ K VN US_S_ M VN US_S_ M VN US_S_ N VN US_S_ N VN US_S_ M VN US_S_ N VN US_S_ M VN US_S_ U VN US_S_ U VN US_S_ T VR US_S_ T VR US_S_ P VN SSUS_S_ M VN SSUS_S_ N VN SSUS_S_ P VN SSUS_S_ P VN SSUS_S_ N VR SSUS_S_ N VR SSUS_S_ P VR SSUS_S_ M VR SSUS_S_ Hudson-M- US.V_S I/O US SS POWER VN HWM_S, remove discharge circuit, reserve for leakage issue VIO_.V m VIO S--.v S I/O power TRE WITH >=mil VIO S_ N VIO S_ L VIO S_ M VIO S_ V VIO S_ V *.U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ VIO S_ Y VIO S_ Y VIO S_ W m VXL S-- MHZ XTL IO power VXL S G VXL_.V VR_._S--.V S ore power m VR_.V VR S_ N.VS TRE WITH >=mil VR S_ M * m VPL SYS_S J VPL_.V U/.V_.U/.V_ M m m VIO_Z_S Trace width >= mil VG_POWER_OWN VN_.V_HWM VIO_Z VG will power down when RT no insert VG_P is generated from FH VG_POWER_OWN R.K_ VLW U/.V_ R K_ FH_VG_PWR_EN Q MENE.U/V_ V VS FH_VN L PYT-Y-N(,).V Q O Q O VN ML L PYT-Y-N(,).U/.V_ if support US. wake up should be change pull hi to S power FH_VN R m Max VS This circuit is for switch and UMI analog power L R PYT-Y-N(,).U/.V_.U/.V_ m Max FH_VN R FH_VPL ML *_/S.U/.V_ FH_VN ML PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom Hudson-M POWER/GN ate: Friday, November, Sheet of

10 STRPS PINS OVERLP OMMON PS WHERE POSLE FOR UL-OP RESTORS. EUG STRPS V VS VS VS PI_LK PI_LK PI_LK LP_LK PI_LK PI_LK PI_LK LP_LK R K/F_ R K/F_ R *K/F_ R K/F_ PI_ PI_ PI_ PI_ PI_ FH has K Internal Pull Up for PI_[:] PI_ PI_ PI_ PI_ PI_ TP TP TP TP TP remove reserve pull low resistor reserve test point only. LP_LK LP_LK E_PWM E_PWM LK_RT LK_RT PI_ PI_ PI_ PI_ PI_ R *K_ R K/F_ R K/F_ R K/F_ R.K_ R *.K_ PULL HIGH USE PI PLL ISLE IL UTORUN USE F PLL USE EFULT PIE STRPS ISLE PI MEM OOT EFULT EFULT EFULT EFULT EFULT REQUIRE STRPS PULL LOW YPSS PI PLL ENLE IL UTORUN YPSS F PLL USE EEPROM PIE STRPS ENLE PI MEM OOT PI_LK PI_LK PI_LK LP_LK LP_LK E_PWM LK_RT PULL HIGH LLOW PIE Gen EFULT USE EUG STRP non_fusion LOK MOE M internal E ENLE LKGEN ENLE EFULT LP ROM EFULT S PLUS MOE ENLE PULL LOW FORE PIE Gen IGNORE EUG STRP EFULT FUON LOK MOE EFULT E ISLE EFULT LKGEN ISLE SPI ROM S PLUS MOE ISLE EFULT FH PWRG V V PU_VRM_PG,, EPWROK T *.U/.V_ R K/F_ * U *UPGGW FH_PWRG R _ PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom Hudson-M STRP/PWRG ate: Friday, November, Sheet of

11 NX Power Up Sequence.V R *_/S m TRVIS.V.U/.V_.U/V_.U/.V_.U/V_.U/V_ TRVIS.V TRVIS.V TRVIS.V V R *_/S m TRVIS_RST#.U/.V_.U/.V_.U/V_.U/V_ ms >=ms TRVIS.V TRVIS.V TRVIS.V TRVIS.V TRVIS.V M/F_ R U m m m m PU_LPWM, LN_PIE_RST# GPIO_ : efine VR_L & L_EN & IGON H/W or S/W control power up timming Pull Hi for H/W mode ---chip have defined power up timing Pull Low for S/W mode -- PU through PRX port to program it V INT_eP_UXP INT_eP_UXN PWM_VJ R R Q MMT--F R TRVIS.V GPIO_ & GPIO_ can let it to N from vendor review POWER_ON_RESET TRVIS_RST# LK_SEL: Pull Hi for MHZ clk source input Pull Low for MHZ crystal input LK_NX_N LK_NX_N LK_NX_P LK_NX_P *M/F_ TP NX_eP_UXP NX_eP_UXN *M/F_ TP INT_eP_TXP.V V INT_eP_TXP INT_eP_TXN INT_eP_TXN INT_eP_TXP INT_eP_TXP R R INT_eP_TXN INT_eP_TXN.k_ K/F_ NX_PWM PV change for brightness issue *_/S R R R *_ TP TP TP TP K/F_ K/F_ PRX_HP POR RESET_L NX_TO NX_TI TO NX_TMS T NX_TK TMS TK GPIO_ GPIO_ GPIO_ LK_SEL LK_SEL OS_IN/MHZ_P OS_OUT/MHZ_N PRX_UX_P PRX_UX_N PRX_LN_P PRX_LN_N PRX_LN_P PRX_LN_N PU_VRY_L PRX_HP PRX_HP : NX It will transfer to Hi when power enable V V V V V V V V V V V NLOGIX NX VSS VSS VSS GN TEST_EN V LVS_LKU_P LVS_LKU_N LVS_U_P LVS_U_N LVS_U_P LVS_U_N LVS_U_P LVS_U_N LVS_U_P LVS_U_N LVS_LKL_P LVS_LKL_N LVS_L_P LVS_L_N LVS_L_P LVS_L_N LVS_L_P LVS_L_N LVS_L_P LVS_L_N R_IS _T _LK VR_L L_EN IGON FG_SL FG_S TXULKOUT TXULKOUT- TXLOUT TXLOUT- TXLOUT TXLOUT- TXLOUT TXLOUT- TXUOUT TXUOUT- TXUOUT TXUOUT- TXUOUT TXUOUT- TXLLKOUT TXLLKOUT- TRVIS T TRVIS LK VJ R LVS_LON ISP_ON FG_SL R FG_S R K/F_ That is for debug only,can let it to N TXULKOUT TXULKOUT- TXUOUT TXUOUT- TXUOUT TXUOUT- TXUOUT TXUOUT- *.K_ *.K_ TXLLKOUT TXLLKOUT- TXLOUT TXLOUT- TXLOUT TXLOUT- TXLOUT TXLOUT- PST_PWM LVS_LON ISP_ON TRVIS.V EIT EILK EIT EILK remove level shift TRVIS T TRVIS LK R_IS V R K_ TEST_EN : internal pull low :scan test mode :normal mode R K/F_ P/V_ R K/F_ FH_LVS_HP FH_LVS_HP R _ PRX_HP R K/F_ PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom NX ate: Friday, November, Sheet of

12 M M M M M M M M M M M M M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S VREF_Q VREF_ M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN VREF_Q_L VREF_Q M M M M M M M M M M M M M M M M M M M [:] M S# M S# M S# M S# M S# M LKP M LKN M LKP M LKN M KE M KE M S# M RS# M WE# M M[:] M OT M OT M Q[..] GLK_SM, GT_SM, V,,,,,,,,,,,,,,,,,,,,,,,.VSUS,,,,,,,.V_R_VTT, M RST# M EVENT# M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN R_VTTREF,,.VSUS V.V_R_VTT.VSUS VREF_Q VS.VSUS VREF_Q.VSUS VREF_ VREF_ VREF_Q V.VSUS VREF_.V_R_VTT Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R R IMM- ustom Friday, November, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R R IMM- ustom Friday, November, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R R IMM- ustom Friday, November, for WiMX for WiMX Reserved for M suggest H.mm Place these aps near So-imm. EMI EMI, change to P to meet ref design *P/V_ *P/V_ * * U/.VS_ U/.VS_ U/.VS_ U/.VS_ *.U/V_ *.U/V_ P/V_ P/V_ R K/F_ R K/F_ P/V_ P/V_ P/V_ P/V_ *U/.V_ *U/.V_ U/.V_ U/.V_ - U *OPN/K - U *OPN/K R *K_ R *K_ *.U/V_ *.U/V_ *U/.V_ *U/.V_ *P/V_ *P/V_ R *_/S R *_/S U/.VS_ U/.VS_ P/V_ P/V_ P/V_ P/V_ *P/V_ *P/V_ *.U/.V_ *.U/.V_ U/.V_ U/.V_ P/V_ P/V_ R *_/S R *_/S * * R *_ R *_ R _ R _ R *_ R *_ P R SRM SO-IMM (P) JIM R-IMM P R SRM SO-IMM (P) JIM R-IMM V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT VSS VSS U/.V_ U/.V_ R *_ R *_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ U/.VS_ U/.VS_ *P/V_ *P/V_ R K/F_ R K/F_ P R SRM SO-IMM (P) JIM R-IMM P R SRM SO-IMM (P) JIM R-IMM /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q R *K/F_ R *K/F_ U/.VS_ U/.VS_ R *K_ R *K_ P/V_ P/V_ U/.VS_ U/.VS_ P/V_ P/V_ U/.VS_ U/.VS_ P/V_ P/V_ U/.V_ U/.V_.U/.V_.U/.V_

13 M IMM_S M M M Q M Q M Q M Q M Q M M M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M Q M M M M Q M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M M M Q M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M M Q M M Q M Q M Q M Q M M M M Q M M M M M M Q IMM_S M M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSP M QSN M QSN VREF_Q VREF_ M [:] M S# M S# M S# M S# M S# M LKP M LKN M LKP M LKN M KE M KE M S# M RS# M WE# M M[:] M OT M OT M Q[..] GLK_SM, GT_SM, V,,,,,,,,,,,,,,,,,,,,,,,.VSUS,,,,,,,.V_R_VTT, M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M RST# M EVENT# R_VTTREF,,.VSUS V.V_R_VTT V VREF_Q.VSUS.V_R_VTT VREF_ VREF_Q.VSUS VREF_ VREF_ V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R R IMM- ustom Friday, November, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R R IMM- ustom Friday, November, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R R IMM- ustom Friday, November, Place these aps near So-imm. EMI request H.mm EMI, change to P to meet ref design U/.VS_ U/.VS_ U/.VS_ U/.VS_ P R SRM SO-IMM (P) JIM R-IMM P R SRM SO-IMM (P) JIM R-IMM /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q R *K_ R *K_ U/.VS_ U/.VS_ *.U/V_ *.U/V_ R *_/S R *_/S.U/.V_.U/.V_ P/V_ P/V_ U/.VS_ U/.VS_ P R SRM SO-IMM (P) JIM R-IMM P R SRM SO-IMM (P) JIM R-IMM V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT VSS VSS *U/.V_ *U/.V_ *.U/V_ *.U/V_ U/.VS_ U/.VS_ U/.V_ U/.V_ U/.VS_ U/.VS_ R *K_ R *K_ P/V_ P/V_ U/.VS_ U/.VS_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ U/.V_ U/.V_ * * P/V_ P/V_ P/V_ P/V_ U/.V_ U/.V_ R.K_ R.K_ U/.V_ U/.V_ U/.VS_ U/.VS_ R *_/S R *_/S

14 U PRT F PEG_TXP PEG_TXN Y PIE_RXP PIE_RXN PIE_TXP PIE_TXN Y Y _PEG_RXP _PEG_RXN PEG_RXP PEG_RXN PEG_TXP PEG_TXN Y W PIE_RXP PIE_RXN PIE_TXP PIE_TXN W W _PEG_RXP _PEG_RXN PEG_RXP PEG_RXN PEG_TXP PEG_TXN W V PIE_RXP PIE_RXN PIE_TXP PIE_TXN U U _PEG_RXP _PEG_RXN PEG_RXP PEG_RXN PEG_TXP PEG_TXN V U PIE_RXP PIE_RXN PIE_TXP PIE_TXN U U _PEG_RXP _PEG_RXN PEG_RXP PEG_RXN PEG_TXP PEG_TXN U T PIE_RXP PIE_RXN PIE_TXP PIE_TXN T T _PEG_RXP _PEG_RXN PEG_RXP PEG_RXN PEG_TXP PEG_TXN T R PIE_RXP PIE_RXN PIE_TXP PIE_TXN T T _PEG_RXP _PEG_RXN PEG_RXP PEG_RXN PEG_TXP PEG_TXN R P PIE_RXP PIE_RXN PIE_TXP PIE_TXN P P _PEG_RXP _PEG_RXN PEG_RXP PEG_RXN PEG_TXP PEG_TXN P N PIE_RXP PIE_RXN PIE_TXP PIE_TXN P P _PEG_RXP _PEG_RXN PEG_RXP PEG_RXN N M PIE_RXP PIE_RXN PIE_TXP PIE_TXN N N M L L K K J PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PI EXPRESS INTERFE PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN N N L L L L J H PIE_RXP PIE_RXN PIE_TXP PIE_TXN K K H G PIE_RXP PIE_RXN PIE_TXP PIE_TXN J J G F F E PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN K K H H helsea Only o not install For Thames R Ra *.K/F_.V_VG LK_VG_P LK_VG_N LK_VG_P LK_VG_N K/F_ R H TEST_PG PIE_LR_RX Y PIE_LRN R K/F_ PEGX_RST# PERST LOK PIE_REFLKP PIE_REFLKN LIRTION PIE_LR_TX Y PIE_LRP o not install for helsea Install for Thames ONLY Rb R.K/F_ Rc Install k for Thames.V_VG Thames XT_M helsea Thames V Ra.K n/a Rb n/a.k GPU_RST# VG_RST R _ U MVHGFTG GPU_HIN_RST# PEGX_RST# R K_ Rc K K,,,.V_VG.V_VG,,,,.V_VG.V_VG PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom helsea_pie_interface ate: Monday, November, Sheet of

15 MEM_I[:] Vendor Type Vendor P/N Thames-XT L M H V_ELY V_ELY Hynix- die Micron- G die Samsung- G die Hynix- die Micron- die Samsung- die GPIO GPIO GPIO LKREQb GPIO GPU_TRST GPU_TI GPU_TMS GPU_TK GPIO TEMP_FIL GFX_ORE_NTRL GFX_ORE_NTRL GFX_ORE_NTRL Reserve for Power Play Mx *, Mhz Mx *, Mhz Mx *, Mhz Mx *, Mhz Mx *, Mhz Mx *, Mhz GPIO PWRNTL PWRNTL PWRNTL R R R R R R R R *K/F_ *K/F_ K/F_ K/F_ K/F_ K/F_ *.K/F_ K/F_ R R R R *K/F_ VG ORE.V.V.V.V.V.V.V_VG GPIO(ROMS#) -k external pull up is required if an external IOS ROM chip is used. Must be unconnected if no external IOS ROM chip is used *.K/F_ *.K/F_ *.K/F_ HTQGFR- MTJMJT-G:G KWGG- HTQGFR- MTJMH-G: KWG-H V_ELY GPUT_LK GPUT_T.V_VG V_ELY ccess to SMus ans S/SL is mandatory on all designs dd test points on SMus and S/SL for debug, update P/N for EO issue L R R TIU(,.) U/.V_.K_.K_ GPIO GPIO GPIO GPIO GPIO GFX_ORE_NTRL GFX_ORE_NTRL VG_LERT TP GFX_ORE_NTRL GPIO GPIO GPIO GPIO GPIO GPU TT.V_TSV GENERI.V_VG TP.V(m TSV) GENLK_LK GENLK_VSYN GPIO, GPIO are N on Thames R R U/.V_ /F_ /F_ R R TP R R R R Memory I.K_.K_ TP TP PX_EN R GENERI.V_VREFG V_ELY TP TP TP TP TP TP TP K/F_ K/F_ *K/F_ *K/F_ *_ GPIO GENLK_LK GENLK_VSYN MEM_I MEM_I MEM_I MEM_I GPUT_LK GPUT_T GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO HMI_HP GFX_ORE_NTRL GFX_ORE_NTRL VG_LERT HP TEMP_FIL GFX_ORE_NTRL GPIO GPIO GPIO LKREQb R R TESTEN GPU_TRST GPU_TI GPU_TK GPU_TMS GPU_TO GPIO.V_TSV *.K/F_ K/F_ J K R U P W R R U U W P W U R W U T V N V T R W U P V T R W U P J H K J H H N H J K J H J K L M M M K G N M L J K N G G J K J K J H H K H L M N K L M F G K L J J U PRT F MUTI GFX GENLK_LK GENLK_VSYN SWPLOK P SWPLOK VPNTL_MVP_ VPNTL_MVP_ VPNTL_ VPNTL_ VPNTL_ VPLK VPT_ VPT_ P VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ P VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ P SMLK SMus SMT SL I S GENERL PURPOSE I/O GPIO_ GPIO_ GPIO_ GPIO TT GPIO_ GPIO LON GPIO ROMSO GPIO ROM GPIO ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL_ GPIO_ GPIO THERML_INT GPIO HP GPIO TF GPIO PWRNTL_ GPIO_ GPIO ROMS LKREQ GPIO_ GPIO_ GENERI GENERI GENERI GENERI GENERIE_HP GENERIF_HP GENERIG_HP E_ HP MLPS VREFG O PX_EN EUG /UX TESTEN JTG_TRST JTG_TI JTG_TK JTG_TMS JTG_TO THERML PLUS MINUS GPIO FO TS_ TSV TSVSS Thames XT_M TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN R VSSN# G VSSN# VSSN# HSYN VSYN RSET V VSSQ VI VS N# N# N# N# N# N# N# N# N# N_TSVSSQ PS_ PS_ PS_ PS_ LK T UXP UXN LK T UXP UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN VGLK VGT U V T R U V T R R T V U R T T U U V T R U V T R U T T R U V T R E F E E V U F G F M G M N M L M L N M L M L M N M K K J J HSYN_OM_R VSYN_OM_R V Reserve for M debug only R.V_V_Q V GPU_HSYN_OM GPU_VSYN_OM.V_V_Q.V_VG, change to short pad Thames INSTLL, do not install for helsea PS_ should be tied to GN on Thames R _ R _ TP TP TP TP TP TP TP /F_ L L *_/S *_/S nalog Power V m *U/.VS_ igital Power. VI m *U/.VS_, change to NI U/.V_ U/.V_,,,,.V_V_Q,,,,, V.V_VG.V_VG V_ELY.V_VG.V_VG V_ELY PIE_VSS E PIE_VSS F PIE_VSS F PIE_VSS G PIE_VSS G PIE_VSS H PIE_VSS H PIE_VSS H PIE_VSS J PIE_VSS J PIE_VSS K PIE_VSS K PIE_VSS K PIE_VSS L PIE_VSS L PIE_VSS M PIE_VSS M PIE_VSS N PIE_VSS N PIE_VSS P PIE_VSS P PIE_VSS P PIE_VSS R PIE_VSS T PIE_VSS T PIE_VSS T PIE_VSS U PIE_VSS U PIE_VSS V PIE_VSS V PIE_VSS W PIE_VSS W PIE_VSS Y PIE_VSS Y PIE_VSS F GN F GN F GN F GN F GN F GN F GN F GN F GN F GN F GN F GN G GN G GN H GN J GN J GN J GN J GN K GN K GN L GN L GN L GN L GN L GN L GN M GN M GN M GN N GN N GN N GN N GN N GN N GN N GN R GN R GN R GN R GN R GN R GN R GN R GN T GN T GN T GN T GN T GN T GN T GN U GN U GN U GN U GN U GN U GN U GN U GN V GN V GN V GN V GN V GN V GN W GN W GN Y GN Y GN Y GN Y GN Y GN Y GN UF PRT F GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN E GN E GN F GN F GN F GN GN F GN G GN G GN G GN G GN G GN G GN H GN J GN J GN J GN J GN J GN K GN K GN K GN L GN L GN L GN L GN L GN L GN L GN L GN L GN L GN M GN M GN M GN N GN N GN N GN N GN N GN P GN P GN P GN R GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN E GN E GN F GN F VSS_MEH VSS_MEH W VSS_MEH W Thames XT_M PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom helsea_main & GN Friday, November, ate: Sheet of

16 .V_VG LMPGSN/_ L.V_PLL_PV U/.V_ U/.V_ isplay Phase Lock Loop Power PLL_PV m.v_pll_pv Memory Type R GR -MHz (± ppm) crystal connected to XTLIN/XTLOUT, or -MHz (. V) oscillator connected to XTLIN. -MHz (. V) oscillator connected to XO_IN, and -MHz (. V) oscillator connected to XO_IN. (y default, this clock should not be spread since internal spreading is used.) UI PRT F, follow Thames design.v_pll_v PLL_V m M PLL_PV XTLIN V EVG-XTLI P/V_.V_VG L LMPGSN/_.V_PLL_V.V(m PLL_V) U/.V_ U/.V_ PLL_PVSS.V_MPLL_PV MPLL_PV m LMPGSN/_.V_VG.V_MPLL_PV L U/.V_ U/.V_.V_SPLL_PV SPLL_PV m LMSN(,M) L.V_VG.V_SPLL_PV N N H H M N PLL_V PLL_PVSS MPLL_PV MPLL_PV SPLL_PV SPLL_V PLLS/XTL XTLOUT XO_IN XO_IN U W W EVG-XTLO R M_ Y MHZ P/V_ R _ U/.V_ U/.V_ N SPLL_PVSS F F N_XTL_PV N_XTL_PVSS LKTEST LKTEST K LKTEST L LKTEST.V_SPLL_V SPLL_V m.v_vg L LMPGSN/_.V_SPLL_V.V(m PLL_V) U/.V_ U/.V_ SPLL_PVSS Thames XT_M * ebug only, for clock observation, if not needed, NI R *./F_ * R *./F_,,,,,,.V_VG.V_VG.V_VG.V_VG route ohms single-ended/ ohms diff and keep short PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom helsea_xtl ate: Monday, November, Sheet of

17 UG PRT F LVS ONTROL VRY_L IGON K J ONFIGURTION STRPS -- SEE EH TOOK FOR STRP ETILS LLOW FOR PULLUP PS FOR THESE STRPS N IF THESE GPIOS RE USE, THEY MUST NOT ONFLIT URING RESET TXLK_UP_PFP TXLK_UN_PFN K L STRPS MLPS GPIO PIN ESRIPTION OF EFULT SETTINGS efault Setting TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP_PFP TXOUT_UN_PFN J K H J G H MLPS_ISLE TX_PWRS_EN N PS_[] GPIO FO GPIO Enable MLPS, N for Thames/Whistler/Seymour : Enable MLPS, disable GPIO PINSTRP : isable MLPS, enable GPIO PINSTRP Transmitter Power Savings Enable : % Tx output swing : Full Tx output swing X X LVTMP TXOUT_UP TXOUT_UN TXLK_LP_PEP TXLK_LN_PEN TXOUT_LP_PEP TXOUT_LN_PEN F G P R W U TX_EEMPH_EN IF_GEN_EN_ IF_VG IS PS_[] PS_[] PS_[] GPIO GPIO GPIO PIE Transmitter e-emphasis Enable : Tx de-emphasis disabled : Tx de-emphasis enabled PIE Gen Enable (NOTE: RESERVE for Thames/Whistler/Seymour) : GEN not supported at power-on : GEN supported at power-on VG ontrol : VG controller capacity enabled : VG controller capacity disabled (for multi-gpu) X TXOUT_LP_PEP TXOUT_LN_PEN R U ROMIFG[:] PS_[..] GPIO[:] Serial ROM type or Memory perture Size Select TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP TXOUT_LN P R N P If GPIO =, defines memory aperture size If GPIO =, defines ROM type - Kbit MP (ST) Mbit MP (ST) - Mbit MP (ST) Mbit MP (ST) - Mbit MP (ST) - Kbit PmLV (hingis) - Mbit PmLV (hingis) XXX GPIO GPIO GPIO Thames XT_M, default setting should be PU from M SH review result GPIO GPIO GPIO R R R K_ K_ *K_ V_ELY IOS_ROM_EN U[] U[] E_IS PS_[] N N PS_[] GPIO HSYN VSYN GENLK_VSYN Enable external IOS ROM device : isabled : Enabled - No audio function udio for P only - udio for P and HMI if dongle is detected - udio for both P and HMI HMI must only be enabled on systems that are legally entitled. It is the responsibility of the system designer to ensure that the system is entitled to support this feature. Enable E function. Reserved for Thames/Whistler/Seymour : isabled : Enabled X XX X GPIO GPIO R *K_ GPIO GPIO R *K_ NOTE: LLOW FOR PULLUP PS FOR THE RESERVE STRPS UT O NOT INSTLL RESTOR IF THESE GPIOS RE USEE, THEY MUST KEEP LOW N NOT ONFLIT URING RESET GPIO GPIO GPIO GPIO GPIO GPIO R R R *K_ K_ *K_ RESERVE RESERVE RESERVE RESERVE PS_[] PS_[] N N GENLK_LK GPIO GPIO GENERI Reserved Reserved Reserved Reserved (for Thames/Whistler/Seymour only) GENLK_VSYN GPU_HSYN_OM GPU_VSYN_OM GENLK_LK GPIO GPIO R R R R R *K_ *K_ *K_ *K_ *K_ U_PORT_ONN_PINSTRP[] U_PORT_ONN_PINSTRP[] U_PORT_ONN_PINSTRP[] PS_[] PS_[] PS_[] N N N STRPS TO INITE THE NUMER OF UIO PLE ISPLY OUTPUTS = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = all endpoints are usable XXX GENERI R *K_ GPIO GPIO R *K_ GPIO GPIO R Memory perture size K_ Power Up/own Sequence GPIO IOSROM M M M M M G G G GPIO GPIO GPIO ROMIFG ROMIFG ROMIFG It is a shared pin strap with ONFIG[:] if IOS_ROM_EN is set to. VG_ORE VG_ORE.V_VG.V_elay.V_VG.V_VG V VI VR VR VR V_T ms ms PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom helsea_lvs / STRP Friday, November, ate: Sheet of

18 .V_VG I/O power for the memory interface..v_vg PX_MOE PX_EN GR MHz U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.VS_ U/.VS_ U/.VS_ *U/.VS_ *U/.VS_ *U/.VS_ *U/.VS_ *U/.VS_ *U/.VS_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.VS_ U/.VS_ U/.VS_ Reserve for rop *U/.VS_ *U/.VS_ *u_.v_ L *_/S *U/.VS_ U/.V_ U/.V_ U/.V_ V_ELY V_VG VR m L *_/S, change to short pad *U/.VS_ U/.V_ U/.V_ U/.V_ VR VR m L *_/S *U/.VS_ *U/.VS_ U/.V_ U/.V_, change to NI ual Q NW--F *u_.v_ MEM I/O VR VR F VR G VR J VR K VR L VR G VR G VR G VR G VR G VR G VR G VR H VR J VR J VR K VR K VR K VR L VR L VR L VR L VR L VR L VR M VR N VR P VR R VR U VR U VR Y VR Y VR LEVEL TRNSLTION F V_T F V_T G V_T G V_T I/O F VR F VR G VR G VR VP VR F VR F VR F VR F VR G VR G VR G VR VOLTGE SENESE F F_V G F_VI H F_GN UE PRT F Thames XT_M PIE O ORE ISOLTE ORE I/O N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_IF_V N_IF_V PIE_PV PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V PIE_V IF_V IF_V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI VI.V_VG helsea uninstall helsea uninstall PIe I/O power. Thames install, Thames install PIE_VR total m PIE_VR m Rc L LMSN(,M) PIE_VR U/.V_ U/.V_ U/.V_ U/.VS_ U/.VS_ Rd W L Y LMSN(,M) V L IF_V W *LMSN(,M) PIe igital Power Supply.V_VG PIE_V (GEN.).V_VG G PIE_V (GEN.) G H H J U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ J.V_VG L M N R T IF_V U/.V_ U/.V_ U/.V_ U/.V_ U/.VS_ U/.VS_ U Ra R *_ Rb N R *_ VG_ORE Ra Rb Rc Rd T helsea-non O install na na na helsea-o install na na na, change to size Thames-non O na install install install VG_ORE Thames-O na na install install U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ F U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ F F G G H H H M U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ N R R R R T T T T U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ U U, add for voltage drop U U U V V V V U/.VS_ U/.VS_ U/.VS_ U/.VS_ V Y Y Y Y Y Y VI VG_ORE L UPT-Y-N(,M,)_ M U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ M M M N N N N N U/.VS_ U/.VS_ U/.VS_ U/.V_ U/.V_ R R R T T V.V_VG,,,.V_VG Y.V_VG,,,.V_VG.V_VG,,,.V_VG V_VG, V_VG VG_ORE VG_ORE u_.v_ PX_MOE R *_ PX_MOE Support O Mode PX_MOE PX_EN R _ R.K/F_ V R *K_ ual Q NW--F R K/F_ V, Q,Q change to dual type MOS Q ual Q,,,, NW--F ual Q NW--F GPU_PWROK PX_MOE U V O_EN MVHGFTG V Note. R K_ Q NW--F ual V R K_ Q PX_EN## PX_EN# NW--F ual.v_vg VG_ORE, Q,Q change to dual type MOS Q PX_EN# PX_EN## Q O. No O Support :IF_V shorts with V (Install Ra) Q O Q O Q O IF_V U/.VS_ U/.V_ U/.V_ U/.VS_,, EPWROK, Q,Q change to dual type MOS Q PX_EN =, for Normal Operation PX_EN =, for O MOE. O Support: Refer to the O reference schematics/pplication note for detail about IF_V Rail if O is Supported (Uninstall Ra) PROJET : R Quanta omputer Inc. Size ocument Number Rev ustom helsea_power & O Monday, November, ate: Sheet of