94 SIMATIC (END) (END) Micro/WIN 32 (STOP) (STOP) CPU RUN STOP STOP CPU RUN STOP
(WDR) (Watchdog Reset) (WDR) CPU WDR WDR ( ) I/O ( I/O ) SM (SM0 SM5 SM29 ) 25 0 ms 00 ms STOP 300ms 300ms WDR S7-200 CPU STOP 4 CPU STOP
Stop, End, and WDR Example LAD STL SM50 5 M56 78 I00 STOP WDR END LD SM50 I/O CPU STOP STOP 5 LD M56 WDR M56 on WDR 78 LD I00 END I00 on FBD SM50 STOP I/O CPU STOP 5 M56 78 WDR M56 on WDR I00 END 5 STOP END WDR LAD I00 on FBD STL
(JMP) (n) (LBL) (n) n: 0 255 WORD LAD STL 4 SM02 / 33 4 LBL 4 JMP LDN SM02 JMP 4 LBL4 JMP LBL 4 LBL 4 33 SM02 52 JMP LBL LAD 4 JMP 4 LBL FBD STL FBD LBL4 JMP LBL
(CALL) (n) Edit>Insert> Subroutine (CRET) ( ) 9 55 ENO = 0 SM43 ( ) 0008 ( ) Micro/WIN32 8 ( ) ( 9-53) ( 8 ) 6 (IN) (IN_OUT) (OUT) IN ( VB0) ( *AC) ( 6#234) (VB00) IN-OUT: ( 6#234) ( &VB00) / OUT: ( 6#234) ( &VB00) TEMP:
(IN, IN-OUT<OUT) L00 LB LB20 LD3 LW7 LD9 EN IN IN2 IN3 IN4 IN/OUT OUT Name Var Type Data Type Comment IN IN IN IN IN IN/OUT OUT TEMP BOOL BOOL BYTE BOOL DWORD WORD DWORD STEP 7 Micro/WIN 32 54 (EN) IN - 54 IN2-2 4-2 4-4 IEEE LAD STL I00 I0 VB0 I0 &VB00 *AC EN SBR IN IN2 IN3 IN4 IN/OUT OUT VD200 LD I00 I00 CALL 0, I0, I0, VB0, VB0, I0, I0, &VB00, *AC, *AC, VD200 VD200 53 STEP 7-Micro/WIN 32 54 LAD STL 54 ( IN4 &VB00) ( ) 2345 DW#2345 ( 9 53)
L0 8 Lx0 Lx7 (LBx LWx LDx), / CALL CALL 2 EN0=0 SM43 ( ) 0008 ( ) MAIN SM0 SUBROUTINE 0 LAD SBR0 EN SBR0 STL LD SM0 CALL 0 0 6 M43 RET 0 0 (RET) 6 STEP 7 Micro/Win 32 LD M43 M3 CRET MAIN FBD SM0 SBR0 EN SUBROUTINE 0 M43 RET 55 LAD STL FBD
(For, Next ) FOR NEXT FOR NEXT FOR FOR NEXT FOR (INDX) (INIT) (FINAL) NEXT (INIT) (FINAL) 0 (INDX) 0 FOR NEXT 0 For: ENO = 0 SM43 ( ) 0006 ( ) / INDX VW, IW, QW, MW, SW, SMW, LW, T, C, AC, *VD, *AC, *LD INT INIT VW, IW, QW, MW, SW, SMW, T, C, AC, LW, AIW,, *VD, INT *AC, *LD FINAL VW, IW, QW, MW, SW, SMW, LW, T, C, AC, AIW,, *VD, *AC, *LD INT FOR/NEXT FOR/NEXT FOR/NEXT ( ) FOR/NEXT FOR NEXT FOR NEXT FOR NEXT ( FOR NEXT FOR NEXT ) 8
For/Next I20 FOR EN ENO VW00 INDX 00 INIT FINAL 0 I2 FOR EN VW225 2 5 INDX INIT FINAL ENO NEXT LAD 2 STL LD I20 I20 FOR VW00,, 00 00 I2 2 2 LD I2 FOR VW225,, 2 NEXT NEXT 20 NEXT FBD I20 VW00 00 FOR EN ENO INDX INIT FINAL 0 I2 VW225 2 5 FOR EN ENO INDX INIT FINAL NEXT 20 NEXT 56 FOR/NEXT LAD FBD STL
L () n= n= (S ) (S ) / n S BOOL L S S LAD 57 L S
L Sxy S S ivs iv0 iv iv2 iv3 iv4 iv5 iv6 iv7 iv8 57 L S S Sxy Sxy iv iv2 iv3 iv4 iv5 iv6 iv7 iv8 L L S S0 JMP LBL FOR NEXT END
9 58 SM0 S0 ( ) 2 T37 2 2 (S02) (S0) LAD STL SM0 2 3 SM00 4 T37 5 S0 202 0 S0 S Q04 S Q05 R 2 T37 TON IN PT S02 LD SM0 LD S S0, SM0 S S0, 2 L S0 23 L LD SM00 S0 S Q04, R Q05, 3 2 LD TON T37, SM0 20 S Q04, R Q05, 2 TON T37, 20 2 4 2 2 LD LD T37 T37 S02 S02 5 5 58 () ( )
LAD STL 6 S02 2 6 L S02 7 SM00 Q02 S T38 IN TON 7 3 LD SM00 S Q02, Q02, TON T38, T38, 250 250 25 250 PT 8 T38 9 S03 8 25 3 LD T38 T38 S03 S03 k 9 2 FBD S0 SM0 EN S N 2 S0 3 SM00 AND EN Q04 S SM00 N Q05 EN R 2 N T37 IN TON 4 T37 S02 20 2 PT 2 2 2 58 () ( )
FBD 5 6 S02 T 2 7 SM00 AND EN Q02 S 3 SM00 N T38 IN TON 25 250 PT 8 T38 9 S03 T 25 3 2 58 () ( ) 2 9-59 L M N 59
60 LAD STL S34 L L S34 M23 I2 S35 S65 M N L N LD M23 A I2 S35 S65 L FBD S34 M23 I2 AND S35 S65 60 9-6 L M N 6
L L' M M' L' M' N 9-62 LAD STL S34 L L S34 V005 S35 L' LD V005 S35 L S64 M L S64 C50 S65 M' M LD C50 S65 S35 S65 S50 S S35 R N L' LD S35 A S65 S S50, R S35, R S65, S65 R 62 M'
FBD S34 L V005 S35 L' L S64 M C50 S65 M' M S35 AND EN S50 S N S65 N S35 EN R N L' S65 EN R M' 62 ( ) N
9-63 L M N 9-63 9 64 LAD STL S34 L L S34 M23 I3 3 3 S35 S65 M N LD M23 S35 LD I33 S65 64 L rk E
FBD S34 L M23 S35 M I33 S65 N L 64 ( ) ENO ENO LAD FBD ENO ENO ENO STL EN STL ENO ENO LAD FBD STL ENO And ENO (AENO) AENO ENO AENO STL AENO ENO