untitled

Transcription

1

2 CIP /.2002 ISBN TP CIP (2002) / ISBN /TP

3 DOS Windows OS/2 Macintosh Unix Linux PC 12 CD-ROM ( thjd@thjd.com.cn) %

4 2002 8

5

6 IV DMA

7 V

8

9 2 3 CPU CPU a b 2 CPU CPU CPU 4 4 4

10 Word CAD

11 SQL 2

12 PC CPU 3 CPU cache

13 ALU 5 Flynn 4 SISD SIMD MISDMIMD CPU T cpu Tcpu = I n CPI T c I n CPI T c

14 1 7 CPI CPI n i= 1 CPI = CPIi Ii I i i CPI i i n MIPS IN MIPS = 6 TE 10 = I N IN I N CPI Tc 10 6 Rc = CPI 10 T E =T cpu CPU MIPS CPI MFLOPS FN 6 E I MFLOPS = T 10 I FN MFLOPS MFLOPS MFLOPS 1 CPU CPU 2 3 TPS 3 1 6

15 8 2 SPEC SPEC95 3 A m = = = = = n i n n i i i m T T T n T n R n A ) ( Λ G m n n n n n n i i n n i i m R R R T R G ) 1 ( ) ( = = = = = Λ H m n n i i n i i m T T T n T n R n H = = = = = Λ A m = = = = n i n i i i i i m T w w R A 1 1 G m wn n w w n i Wi i m R R R R G = = = Λ H m n n n i i i n i i i m w T w T w T w T R w H = = = = = Λ SPEC icomp 4 S p e e e e o r f f T T S + = = 1 1 p f e 0 f e 1 r e 5

16 1 9 1fault error failure MTTF MTBF MTTR 1.2 ALU CPU D CPU CPU ALU ALU

17 CPU

18 1 11 ROM RAM SRAM DRAM CPI MIPS MFLOPS SISD SIMD (PE) MISD MIMD CPU SPEC

19 12 0 stuck-at-zero 1 stuck-at-one 1 2 1MB KB RAM

20 CPU A 1 B 2 A B 10 6 MIPS MIPS SRAM DRAM

21 BASIC C++ Java CPU a) b) c) d) 2 a) b) c) d) 3 a) b) c) d) 4 a) b) c) d)

22 a) b) c) d) 6 a) b) c) d) 7 a) b) c) CPU d) 8 a) b) c) 32 d) 9 a) b) c) d) 10 a) b) c) d) CAD 11 a) b) c) d) 12 a) b)

23 16 c) d) 13 a) b) c) d) 14 a) b) c) d) 15 a) b) c) d) 16 a) b) c) d) 17 a) b) c) d) 18 a) b) c) d) 19 a) b) PC c) d) 20 Benchmark a) b) c)

24 1 17 d) 21 a) b) c) d) 22 a) b) c) d) 23 a) MIPS MFLOPS b) C c) d) 24 a) b) c) d) 25 a) b) c) d) 26 a) 32 b) c) d) 27 i R i w i 1 1 n w R n n n w Wi i i i R i a) i= 1 b) i= 1 i= 1 R w R i i i i= 1 c) d) 28 a) b) MTTF c) MTBF d) MTTR 29

25 18 a) b) MTTF c) MTBF d) MTTR 1 c 2 b 3 a 4 a 5 b 6 c 7 b 8 c 9 d 10 a 11 b 12 c 13 a 14 d 15 c 16 d 17 c 18 a 19 b 20 a 21 a 22 c 23 c 24 d 25 a 26 a 27 b 28 b 29 c 1 CPU CPU CPU IO CPU 5

26 Flynn Flynn 7 (1) (2) PC (3) (4) (5) 8 9 TPS 10

27 (1) X 3 (2) Y X Y Z B B (1) 1-1 B1 Y X B2 Y X B1 Z X B2 Z X X A m Y Z X 25%3 1-2 X X Y Z B B A m G m (2) Y 1-3 A m X Y 25% Z 3 A m 1-3 Y X Y Z B B A m G m

28 MHz CPI 1 60% cache 2 18% 4 12% cache 8 10% CPI MIPS CPI CPI = 1 60% % % % = 2.24 MIPS = 40/2.24=17.9 T cpu = I n CPI T c = I n CPI/R c = I n 2.24/( ) = I n ( ) 3 40MHz CPI MIPS = % 32% 15% 8% CPI=1 45% % % +2 8% = 1.55 MIPS = 40/1.55 = 25.8 = /( )= ( ) 4 15MHz 10MIPS 1 (1) CPI (2) 30MHz

29 % 1 5% 2 (1) CPI MIPS CPI = /( )=1.5 (2) 1 CPI CPI= (2 1) (2 1)=1.9 MIPS MIPS = R c /(CPI 10 6 )= /( )= Load/Store / CPI CPI CPI 43% 1 Load 21% 2 Store 12% 2 24% 2 (1) CPI (2) M 25% Load - CPI 2 CPI 3 CPI (1) CPI CPI = 43% % % % 2 = 1.57 (2) 75% 43% 75%=32.25% 25% 43% 25%=10.75% Load 21% 43% 25%=10.25% Store 12% 24% Load %=89.25% 32.25%/89.25%=36.13% CPI %/89.25%=12.04% CPI 2

30 1 23 Load 10.25%/89.25%=11.48% CPI 2 Store 12%/89.25%=13.45% CPI 2 24%/89.25%=26.89% CPI 3 CPI CPI = 36.13% 1 + (12.04%+11.48%+13.45%) % 3 = CPI CPU 6 25% CPI 4.0 CPI % CPI 20 CPI CPI 2 CPI 3 CPI (4 25%) + ( %) = 2.0 CPI 2.0 1% (20 2 ) = /1.82 = 1.10 CPI (3 25%) + ( %) = /1.75 = Amdahl 1 5 = f e 1 f + e 20 f e =16/19= % 8 40% 20% 2 4

31 24 Amdahl / / /( /2+0.20/4) = 1/0.65 = a n xmips (1) n a x MIPS (2) n=16, x=4 MIPS 40MIPS a (1) MIPS xs p S p MIPS =x/(1 a + a /n) (2) 40=4/(1 a + a /16) a = % 40% 20% 5% 5% 100MHz (1) (2) 1 (3) (2) 1 (1) A m = (1 30% + 1/1.5 40% + 1/2.0 20% + 1/10.0 5% + 1/4.0 5%) 100 = (MIPS) G m = = (MIPS) H m = = 100 = 50 (MIPS) ( ) 2 MIPS n 1 1 CPI = CPIi Ii = ( ) = 2 I 100 n i=

32 1 25 R 6 c MIPS = = =50(MIPS) 6 6 CPI (2) 1 A m = (1 30% + 2/1.5 40% + 1/2.0 20% + 1/10.0 5% + 1/4.0 5%) 100 = (MIPS) G m = = (MIPS) H m =100/(2 0.3) = 100/1.7 = (MIPS) (3) (2) 1 A m = (1 30% + 2/1.5 40% + 1/2.0 20% + 1/20.0 5% + 1/4.0 5%) 100 = (MIPS) G m = = (MIPS) H m =1/ = (MIPS) 11 SUN SPARC2 SPEC SPEC (MFLOPS) (MFLOPS) GCC 10.7 Li 9.0 Espresso 8.9 Eqntott 9.7 Spice2g6 8.3 Matrix Doduc 5.0 FPPPP 7.8 NASA Tomcatv 5.6 A m = ( )/10 = 8.48 G m = = H m = = ( ) (1) (2) 2 (3) 20

33 26 (4) 70% 10% (1) f e Amdahl 1 Sp = 19 1 fe 20 f e S p f e S p f e S p SP S P Sp f e 1-1 (2) S p =2 1 2 = 19 1 fe f e = = = 52.69% (3) S p = f e = = = 94.73% (4) f e =0.7 1 S p = = % =3.29

34 = r e = r e f e 1 20 f e = ( 1 ) = f e ' f e = T T 25% (1) a (2) (3) (2) a (1) T Amdahl 0.25T 9 S p =(0.75T T)/T=3 Amdahl S p = 1/(1 a+a/9)=3 (2) 9 2=18 Amdahl S p = 1/(1 a+a/18)=18/( )=3.79 (3) Amdahl 3.79 = 1/(1 a'+a'/9) a' = R v 10MFLOPS R s 1MFLOPS a

35 28 (1) R a (2) R a 7.5MFLOPS a (1) 10MFLOPS/1MFLOPS=10 Amdahl S p = 1/(1 a +a /10) =10/(10 9a) R a = S p 1MFLOPS = 10/(10 9a) MFLOPS (2) R a =7.5MFLOPS 10/(10 9a)=7.5 a= icomp 4 Whestone Cint92 Cfp92 ZD Bench PC 16 70% 32 30% CPU ZD Bench CPU 52% Whestone 2% ZD Bench CPU 1% 16 ZD Bench CPU 10% 16 ZD Bench CPU 5% 32 Cint92 15% 32 Cfp92 5% 32 Cint92 5% 32 Cint92 5% (1) icomp ZD Bench 68% Cint92 25% 16 Whestone 2% Cfp92 5%

36 1 29 ZDBench 0.68 Whetstone icomp = 100 ( ) ( ) Base ZDBench Base Whetstone Cint Cfp ( ) ( ) Base Cint92 Base Cfp92 (2) CPU Base ZD Bench = Base Whestone = Base Cint92 = Base Cfp92 = 0.45 i486dx2-66 ZD Bench= Whestone= Cint92=32.44 Cfp92=16.07 icomp icomp = 100 ( ) ( ) ( ) ( ) = MTTF 10 6 h 10h? λ=1/mttf=10 6 R(10) = e = n (1) i R i (2) i λ i (1) n = 1 2L n = i= 1 R R R R R (2) n R = i= 1 λ e i t n 1 + λ2 + + λn = λi i= 1 λ = λ Λ i

37 MTBF = = λ λ + λ + Λ λ n 18 n (1) i R i (2) λ i (1) R = 1 (1 R )(1 R ) L (1 R ) n i= 1 i= = 1 (1 R ) n i = 1 (1 e ) i λ t (2) λ i λi R = 1 (1 e t ) n n 19 S 1 S 2 S 1 2 S 2 3 R S (1 R) 2 S (1 R) 3 R S =[1 (1 R) 3 ][1 (1 R) 2 ]=6R 2 9R 3 +5R 4 R /h (1) 1 300h (2) 3 300h (3) 2 150h (1) λ=0.005 R(300)=e =e 1.5 = (2) λ= =0.015 R(300)=e =e 4.5 = (3) λ =0.005 R(150)=1 (1 e ) 2 =1 (1 e 0.75 ) 2 =1 ( ) 2 =

38 3 Cache SRAM DRAM SRAM 6 DRAM SRAM DRAM 2 WE* CS* CE* OEDRAM DRAM RAS* CAS* RAS* 6 DRAM SRAM DRAM 7 (FPM DRAM)

39 3 67 EDO DRAM EDRAM SDRAM Rambus RDRAM 2 ROM ROM 0 1 PROM EPROM ROM EEPROM ROM CPU CS* CE* CS* CE CS TTL

40 CPU / Cache Cache CPU CPU

41 CPU Cache Cache Cache Cache CPU Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache LRU Cache Cache Cache Cache Cache Cache Cache Cache 2 Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache n Cache n n

42 70 Cache Cache Cache n Cache Cache n=1 3 Cache Cache Cache Cache Cache 1 Cache Cache Cache Cache Cache Cache = + + Cache = + 2 Cache Cache Cache Cache = Cache Cache Cache Cache Cache 4 Cache Cache Cache 1 LRU 2 FIFO Cache Cache 3 Cache 5 Cache Cache Cache Cache Cache

43 3 71 Cache Cache Cache Cache CPU Cache Cache Cache Cache 6 Cache 1 Cache Cache Cache 2 Cache Cache Cache Cache Cache Cache Cache 3 Cache Cache H c Cache T c T m T b Cache T a = H c T c + (1-H c )T m = T c + (1-H c )(T m -T c ) Cache T a = T c + (1-H c )T m 4 Cache T a = T c + (1-H c )T b Cache T c1 Cache T c2 Cache T m1 Cache T m2 Cache H c1 Cache H c2 Cache T a = T c1 + (1 H c1 )T m1 T m1 = T c2 + (1 H c2 )T m2 T a = T c1 + (1 H c1 )(T c2 + (1 H c2 )T m2 ) = T c1 + (1 H c1 )T c2 + (1 H c1 ) (1 H c2 )T m2 (1 H c2 ) Cache (1 H c2 ) (1 H c2 ) Cache 7 Cache Cache Cache Cache 1 3-1

44 72 Y? N Y? N Y? N Y? N cache cache a b 3-1 T a = T c + (1-H c )T b + W b (1-H c )T b = T c + (1-H c )(1+W b )T b Cache T c Cache Tb (1-Hc) (1-Hc)Tb Cache Tb W b (1 H c ) W b (1 H c )T b Cache Y? N Y? N Y? N cache cache a b 3-2

45 3 73 T a = T c + (1-W)(1-H c )T b + W b (1-W)(1-H c )T b + W(1-H c )(T m -T c ) = T c + (1+W b )(1-W)(1-H c )T b + W(1-H c )(T m -T c ) Y N Y N?? cache cache a b 3-3 T a = T c + (1-H c )T b + W(T m - T c ) Y? N Y? N cache cache a b 3-4 T a = T c + (1-W)(1-H c )T b + W(T m - T c ) 8 Cache 1 Cache 3 Compulsory miss

46 74 Cache Cache Capacity miss Cache Cache Conflict miss Cache Cache Cache 2 Cache Cache Cache Cache Cache Cache Victim Cache Cache Cache Cache Cache 3 Cache Cache CPU CPU Cache Cache Cache CPU Cache Cache 4 Cache Cache Cache Cache Cache Cache Cache

47 LRU CPU (TLB) Cache 2 1 Cache 2

48 Cache 1 Cache Cache Cache Cache Cache 3-5 VPN MEM PPN Disp TLB Disp cache a Cache MEM VPN Disp TLB cache PPN tag Data C O M P b Cache 3-5 Cache CPU Cache Cache 2 Cache Cache 3-6 a b

49 3 77 VPN cache Disp a Cache VPN Disp TLB cache PPN Disp Data C O M P b Cache 3-6 Cache Cache RAM ROM SRAM DRAM EDO DRAM PROM ROM EPROM ROM

50 78 EEPROM SDRAM EEPROM Cache Cache CPU Cache Cache Cache Cache CPU Cache Cache Cache Cache Cache Cache (miss -penalty) CPU 90% 10% 10% 90% Cache Cache Cache Cache Cache LRU Cache Cache Cache Cache Cache Cache Cache Cache -Cache Cache Cache

51 3 79 ROM ROM ROM ROM ROM 10 PROM SRAM M 8 DRAM

52 CPU Cache Cache 27 Cache Cache 28 Cache 128 i 29 Cache Cache 30 n Cache M n 1 Cache n M Cache 31 Cache 3 32 C Cache M Cache 35 Cache Cache Cache 37 -Cache Cache 38 CPU

53 RAM ROM 2 SRAM DRAM T C 8 RAS* CAS* 9 ROM PROM EPROM EEPROM FF FFFFFF Cache i mod M

54 a) RAM b) CS* c) d) 2 a) b) c) d) 3 a) EPROM b) c) CPU d) 4 SRAM a) 20 b) 22 c) 25 d) 30 5 RAM a) b) c) d) 6 a) b) c) SRAM d) ROM 7 a) b) c) d) 8

55 3 83 a) b) Cache c) Cache Cache d)- 9 1K 8 a) 1024 b) 64 c) 32 d) MB 0 a) b) c) d) a) b) c) d) 12 a) b) c) d) 13 Cache a) b) c) d) 14 Cache Cache a) b) c) d) 15 Cache Cache a) b) c) d) 16 Cache a) b) c) d) Cache 17 Cache Cache Cache a) b) c) d) 18 Cache Cache Cache a) b) c) d) 19 a) I/O b) c)

56 84 d) 20 a) b) c) d) 21 a) b) c) Cache d) LRU FIFO 22 a) b) c) d) 23 a) b) c) d) 24 a) b) c) d) 25 a) b) c) d) 26 a) b) c) d) IEEE a) b) c) d) 28 a) CPU b) RAM ROM c) d) 20 1MB

57 Cache a) b) c) Cache d) 30 a) b) c) d) 1 a 2 d 3 a 4 a 5 b 6 c 7 a 8 b 9 b 10 a 11 a 12 b 13 a 14 a 15 d 16 a 17 a 18 c 19 c 20 a 21 a 22 b 23 a 24 b 25 d 26 a 27 b 28 c 29 b 30 b 1 Cache Cache Cache Cache Cache LRU FIFO 2 ROM RAM EEPROM RAM 3 ROM ROM SRAM 4

58 86 5 Cache? Cache Cache a b a b (1) 2K 16 (2) 64K 8 (3) 16M 32 (4) 4G 4 (1) (2) 16 8 (3) (4) K 8 16KB A15~A0 16KB 4 4K 8 12 A11~A0 16K= A13 A13 A12 CS0= A13 *A12 CS1= A13 *A12120 CS2=A13* A12 CS3=A13*A12

59 K 8 8K 16 CPU R/W* A15~A0 CS* WE* CPU (8K/4K) (16/8)=4 ( ) CPU 3-7 A13 A13~A1 R/W* CPU A12~A1 we* A cs we* A cs 4K 8 4K 8 D D we* A cs we* A cs 4K 8 4K 8 D D D7~D0 D15~D8 D7~D0 D15~D8 D15~D CPU SRAM A9~A1 AS# WE# D15~D0 A9~A7 A6~A1 3-8 A9~A1 AS# A9-7 3:8 A6~A1 WE# CPU we* A ce 64x1x16 D we* A ce 64x1x16 D we* A ce 64x1x16 D D 15-0 D 15-0 D 15-0 D RAM 512 ROM RAM ROM RAM CS* WE* ROM CS*

60 88 CPU A15~A0 D7~D0 RW* CPU 4 RAM 1 ROM RAM ROM RAM1 0000~007F x x x x x x x RAM2 0080~00FF x x x x x x x RAM3 0100~017F x x x x x x x RAM4 0180~01FF x x x x x x x ROM 0200~03FF 1 x x x x x x x x x x 1KB 10 CPU RAM =128 ROM =512 CPU Mb DRAM 32MB (1) 4M 32 (2) DRAM (3) DRAM (4) CPU (1) 4M 32 16MB 2 (2) 4/4 32/1 = 32 (3) m n M N M N m n 64

61 3 89 (4) 32M = CPU A15~10 A9 A8 A7 A6~A0 R/W# Data 2: RAM1 CS WE* A D D0~D7 RAM2 CS WE* A D RAM3 CS WE* A D RAM4 CS WE* A D A8,A7 CS A ROM D CPU 7 1K 8 SRAM 2K 32 CPU CPU MREQ# R/W# SRAM 1K 2K SRAM K/1K 32/8 = 8 SRAM 4 2 2K= K 32=2 13 KB CPU A12 CPU MREQ# R/W# CPU K 8 2 1K 8 ROM 2 2K 4 RAM

62 90 CPU RAM ROM RAM CS# WE# CPU A11~A0 8 D7~D0 R/W# MREQ# ROM 10 2 ROM RAM 11 2 RAM ROM CPU RAM ROM 3-11 ROM A9~A0 RAM A10~A0 A11 A10 2:4 sel0~sel3 sel0 sel1 ROM sel2 sel3 RAM R/W# RAM WE* A 12-2 A 12 A 11-2 CPU CE A CE A CE A CE A CE A CE A CE A CE A 1Kx8 1Kx8 1Kx8 1Kx8 1Kx8 1Kx8 1Kx8 1Kx8 WE# D WE# D WE# WE# D WE# D WE# D WE# D WE# D R/W# D31 ~D 0 D 7-0 D 15-8 D D D 7-0 D 15-8 D D CPU MREQ# A11~A0 R/W# OE# sel0 A11~A10 ROM A OE 2:4 sel1 RAM ROM A OE WE* A CE sel2sel3 WE* A CE CPU 1K 8 D 1K 8 D 2K 4 D 2K 4 D D7~D0 D7~D0 D7~D0 D7~D4 D3~D CPU RAM ROM SRAM BE1 BE0

63 3 91 WE1 WE0 A9~A7 A6~A A9~A7 A9~A1 WE1 WE0 3:8 A6~A1 BE0 BE1 D15~D0 we A ce D7~D0 we A ce D15~D8 we A ce we A ce we A ce we A ce CPU BE0 BE1 WE0 WE1 CPU / B/W# A0 R/W# FFF 16 ROM FFF FFFF 16 RAM RAM CS# WE# CPU A15~A0 8 D7~D0 R/W# MREQ# RAM ROM 8K 1 CPU 2 16 =64KB ROM 2 14 =16KB 8KB RAM =40KB 8KB 64KB 8 8KB Y0 Y1 ROM ROM FFF 16 A15~A13 000~001 Y3 Y7 5 RAM RAM 3FFF 16 FFFF 16 A15~A13 011~111 romsel0 = A15 *A14*A13*MREQ# romsel1 = A15 *A14*A13* MREQ# ramsel0 = A15 *A14*A13* MREQ# ramsel1 = A15* A14 *A13*MREQ# ramsel2 = A15* A14 *A13* MREQ# ramsel3 = A15*A14* A13 *MREQ#

64 92 ramsel4 = A15*A14*A13* MREQ# romsel0 romsel1 ramsel0 ~ ramsel4 MREQ# Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 3:8 OE s2 s1 s0 A 15 A 14 A KB 8 8K 1 13 A12~A ROM SRAM R/W# MREQ# A 15 ~A 13 OE# romsel0 3-8 romsel1 ramsel0 ramsel4 A 15 ~A 0 A 12 ~A 0 R/W# CPU ROM A CE 8K 1 8 D ROM A CE 8K 1 8 D WE A CE 8K 1 8 D RAM WE A CE 8K 1 8 D RAM D 7 ~D RAM ROM 2K RAM 4K ROM KB 2 00 RAM ROM 11 (1) RAM ROM (2) (3) 16 RAM ROM (1) 2KB/256 = 8 8 RAM 4KB/1024B = 4 4 ROM (2) 3-15

65 K 4K 6K RAM ROM ROM IO KB RAM 4K ROM 16 (3) RAM FF 16 ROM FF 16 1FF0 16 1FFF (1) 4 (2) 4 (1) /4 4 (2) (1) (2) (3) (1) 8 8 (2) (3)

66 A[16] CPU 1/ A[0] A[4] A[8] A[12] 1 A[1] A[5] A[9] A[13] 2 A[2] A[6] A[10] A[14] 3 A[3] A[7] A[11] A[15] / / /4 = Cache 16 3 (1) 1 (2) (3) 8 (1) Cache ( ) (2) Cache 1% Cache (1) = = /4 4 16/ = =22

67 3 95 (2) = = = K 16 Cache 1K 4 (1) Cache (2) Cache (1) 64K 16 64K = K = 2 10 Cache 10 Cache 16 10=6 4 = =8 (2) 2 8 =256 Cache MB 32 Cache 512 (1) Cache 1 (2) Cache 8 (3) Cache 1 4 1MB =18 Cache 512 Cache (1) Cache (2) Cache 0 8 3

68 (3) Cache K (1) Cache (2) Cache (1) Cache 4096 Cache 12 64K Cache Cache 0 Cache Cache (2) 16K Cache KB Cache 32 Cache 4 32

69 3 97 (1) Cache (2) ABCDE8F8 Cache (1) 3-20 Cache 16KB Cache Intel Cache 0 Cache Cache cahce (2) ABCDE8F8 16 = Cache = = = Cache- 8 Cache 4 (1) 0, 1, 2, 5, 4, 6, 4, 7, 1, 2, 4, 1, 3, 7, 2 Cache Cache (2) (3) Cache (1) Cache 3-2

70 Cache Cache Cache h h h h 3-21 Cache 3 (2) (3) h = 4/15 = Cache 4 Cache 16 Cache Cache Cache Cache 3-22 Cache n n n y n n y n n y n n y y n y 3-22 Cache

71 3 99 Cache Cache 22 LRU? LRU Cache 0 1 Cache 0 1 B (B (B 1)) / 2 i i 1 i Cache (1) Cache (2) (1) 4096= Cache 64=2 6 Cache 6 128= =19 Cache 6+7= (2) =6 6 2=

72 KB 4 Cache 32 Cache 4 32 (1) Cache (2) ABCDE8F8 Cache ABCDE8F8= (1) 3-24 Cache 16KB Cache 14 Cache (2) Cache Cache Cache Cahce (2) Cache = Intel Cache 8KB LRU B0 B1 B2 Cache (1) Cache 3-25 Cache 8KB Cache 13 Cache Intel (2) Cache Cache B0, B1 B2 Cache V Cache

73 Cache Cache B0 B1 B2 V Cache 26 Cache K 32 Cache Cache 4096 Cache K Cache Cache Cache Cache

74 Cache- 8 (0~7) Cache 4 (0~3) 2 (LRU) (1) Cache (2) Cache (3) Cache Cache (4) (3) (5) (3) Cache (1) Cache 1 4 Cache Cache Cache 3-27 Cache (2) 0 1 Cache Cache Cache Cache Cache Cache

75 3 103 (3) Cache h m m h m m m m h m m 3-29 Cache (4) 6, 7, 9, 10, 11, 12, 14, 15 (5) Cache 3 Cache h = 3/15 = Cache 5 Cache 90% Cache T a =0.10 T m T m /5 =0.28 T m 1/0.28= Sp = = = VAX-11/780 Cache 8.5 Cache 6 11% 3 Cache Cache? Cache = = Cache 10.48/8.5 1 = 24% Cache Cache 3 3 Cache Cache 3 30 CPU Cache 1.5 RISC?? = /1.5 1 = 132%

76 104 CPI Cache 31 4 Cache Cache 40ns 90% 80% 400 Cache 4 (1) (1+0.8) 4=7.2 4M 4M 7.2=28.8 MB/s (2) Cache 90% 10% 2.88MB/s 32 Cache Cache Cache 1 50 Cache 0.64% Cache 6.47% 75% Cache Cache (75% 0.64%) + (25% 6.47%) = 2.10% 75% (1+0.64% 50) + 25% (1+6.47% 50) =75% % = Cache 40 Cache 20 Cache Cache 40/1000=4% Cache 20/40=50% Cache 20/1000=2% 34 Cache CPI 2.0 STORE LOAD 40% 25 2% Cache Cache

77 3 105 Cache CPI Cache CPI S p = (2+40% 2% 25)/2=1.1 Cache Cache (1) Cache1: 1 (2) Cache2: 4 (3) Cache3: 4 (1) Cache1: 4% 8% (2) Cache2: 2% 5% (3) Cache3: 2% 4% Cache 6 Cache (1) Cache1 Cache T 1 = (4% %) (6+1) = =0.56 (2) Cache2 Cache T 2 = (2 % %) (6+4) =0.45 (3) Cache3 Cache T 3 = (2% %) (6+4) =0.4 Cache1 Cache Cache 20 (1) 0.05 (2) Cache 0.03 Cache 1.2 (3) Cache (1) T a = = 20 (2) T a = = = 18 (3) T a = = Cache 1 (32 ) 1 Cache 15% 1.2 Cache 2 Cache 8

78 106 (1) (2) 2 10% (3) (2) 2 (4) (2) 64 (1) = 3.44 (2) = 3.92 (3) (8+1) = 3.08 (4) = K 16 4K Cache Cache 4 4 LRU Cache Cache Cache 10 Cache Cache Cache = Cache Cache Cache (10 1) 64 2 = 2240 H = = Tm 1 1 Sp = = = HT ( 1 ) c 1 c + H T T m H + (1 H ) T 10 = m (1) Cache (2) Cache Cache = 43520T m 1088T b T b + ( ) 9 T c T

79 3 107 T b =T m =10T c = 6368T m S p = 43520/6368 = Cache 1 T a =T c +(1 H c )T b +(1 H c )T b T a =T c +(1 W)(1 H c )T b +(1 W)(1 H c )T b +W(1 H c )(T m T c ) K 1MW 128 = = K = =24 1M = = CPU (1)

80 108 (2) (3) (1) (2) (3) = = = (1)

81 3 109 (2) 1) 0 2) ) ) ) ) ) 4096 (1) (2) 1) ) 3 3) ) ) ) 7 7) , 0, 2, 2, 1, 7, 6, 7, 0, 1, 2, 0, 3, 0, 4, 5, 1, 5, 2, 4, 5, 6, 7, 6, 7, 2, 4, 2, 7, 3 LRU * *1 1* * * 1* * * 4* 4* * 0* * * * * * 2* * 0* * * 7* * * 1* * 6* 6* 3 n n n y y n n y n y n y n y n n n y n y y n n y y n n y y n =13/30=43.3%

82 NOP CLR INC R1 ADD R1, R2 ADD R1, R2, R3 3 4 (PC) PC CPU

83 PC 1 PC 4-1 load 4-1 load 1 2 load adr ac mem[adr] LD ADR AC M[ADR] load (adr) ac mem[mem[adr]] AC M[M[ADR]] load adr(pc) ac mem[pc+adr] LD $ADR AC M[PC+ADR] load #n ac n LD #NBR AC NBR load adr(rn) ac mem[adr+rn] LDADR(X) AC M[ADR+XR] load rn ac rn LD Rn AC Rn load (rn) ac mem[rn] LD (R1) AC M[R1] adr (adr) adr Rn $ PC

84 112 # 2 3 Little Endian Big Endian =

85 = CISC CPU V Z N C ALU 1 C 1 ALU 0 C 0 ALU () 1 N 1 ALU 0 N 0 ALU 0 Z 1 Z 0 0 Z=1 0 Z=0 ALU V 1 ALU V 0 (PSW) 2 LOAD STORE STORE R1,mem STORE mem,r1 3 PUSH POP

86 114 3 PUSH POP CISC RISC 1 CISC 2 RISC -

87 RISC- CISC PC PC

88 PC x= y= n=5 x y Z= V= N= RISC ( ) CPU (PC+1) PC 2003H 2008H 2008H 2001H

89 a) b) c) d) 2 a) b) c) d) 3 a) b) c) d) a) b) c) d) a) b) c) d) 6 a)

90 118 b) c) d) 7 16 PC a) 1 b) 2 c) 4 d) PC a) 3000 b) 3001 c) 3002 d) a) b) c) d) 10 a) b) c) d) 11 a) b) c) d) 12 a) b) c) d) 13 Load a) b) c) d) 14 STORE a) b) c) d) 15 a) PC b) c) PC

91 4 119 d) PC 16 a) PC b) c) PC d) PC 17 a) PC b) c) PC d) PC 18 a) PC b) PC PC c) PC d) PC PC 19 a) PC b) c) d) 20 a) b) c) 1 d) 21 a) b) c) d) 22 LOAD a) b) c) d) 23 a) b) c) d) 24 a) b) c) d) 25 a) b) c) d) 26 a) b) c) d) 27 a) b) c) d) 28

92 120 a) b) c) d) DRAM 29 a) RAM b) c) d) 30 a) b) RISC c) Cache d) RAS* 31 a) RISC LOAD/STORE b) c) EPROM d) PC a) 150 b) 151 c) 152 d) a) b) c) d) PC 1 a) b) c) d) a) b) c) d) 36 a) b) c) I/O d) 37 LOAD R1,A LOAD R2,B ADD R3,R1,R2 STROE C,R3 a) b) - c) - d) -

93 c 2 b 3 b 4 b 5 c 6 d 7 b 8 c 9 c 10 c 11 b 12 d 13 a 14 b 15 a 16 c 17 d 18 b 19 a 20 c 21 a 22 b 23 d 24 c 25 d 26 c 27 b 28 b 29 c 30 c 31 a 32 d 33 d 34 c 35 c 36 d 37 b 1? 2 C 3 LIFO FIFO RISC 0 5 NOP PC

94 122 CPU NOP = = 24K 2 9 T1 30% T2 24% T3 6% T4 7% T5 7% T6 2% T7 3% T8 20% T9 1% (1) (2) (1) I1 10 I2 00 I I I I I I8 01 I ( ) + 4 ( ) ( )=2.57 (2) I1 00 I2 01 I8 10 I

95 4 123 I I I I I (( ) +5 ( )= A B 32 A (1) B (2) (1) (2) ( )/(60+32) = 7.04 B A B A A , 0.20, 0.11, 0.09, 0.08, 0.07, 0.04, 0.03, 0.02, = = T 1 20% T 2 12% T 3 11% T 4 15% T 5 8% T 6 3% T 7 2% T 8 18% T 9 10% T 10 1% (1) 10 (2) 3.20 (1) 4-1

96 (1) I1 I8 I4 I2 I3 I9 I5 I6 I7 I = ( ) ( ) = = = 3.03 (2) (2) I1 I8 I4 I2 I3 I9 I5 I6 I7 I =3 ( )+4 ( ) = = (2) I1 I8 I4 I2 I3 I9 I5 I6 I7 I

97 4 125 =3 ( )+5 ( ) = = M N L N=((2 4 M) 2 6 L) 2 6 L=(2 4 M) 2 6 N M N L L=((2 4 M) 2 4 N) (1) load #20 (2) load 20 (3) load (20) (4) load #30 (5) load 30 (6) load (30) (1) 20 (2) 40 (3) 60 (4) 30 (5) 50 (6) 70 9 R PC 4000

98 126 (1) R (2) (R) (3) 1000 (4) (1000) (5) 2000(PC) (6) #2000 (1) 1000 (2) 2000 (3) 2000 (4) 3000 (5) 3000 (6) W W+1 Y Z X Z (1) (2) (3) (4) 4-2 X W W+1 Z OP Y A (1) Z W+1 Z Z=Y (2) Z Y Z = (Y) (3) PC PC W+2 Y Z=W+Y+2 (4) Y Z=X+Y 11 LOAD AC PC 200 R1 400 XR

99 4 127 PC load 500 M R XR AC AC (1) (2) (3) (4) (5) (6) (R1) (7) (R1) (1) 500 AC 800 (2) 500 AC 201 (3) (4) = PC 202 (5) XR+500= = (6) R1 400 AC (7) R1 400 AC (1) PC (2) (3)

100 128 (4) (1) PC (2) = 254 (3) 254 < (4) R1 200 (1) (2) (3) (4) (R1) (5) R1 (1) 400 (2) 301 (3) PC PC =702 (4) R1 R1 200 (5) R = CPU OP M D R D M S R S OP 4 M S, M D 3 R S, R D 3 (1) 16 (2) CPU 16 (3) 16 (1) (2) CPU 16 4

101 OP M D R D M S R S OP M D R D M S R S (3) OP M D R D M S R S SP PC SP (1) (2) (3) (1) PC SP PC= SP= (2) PC SP = PC= SP=FF (3) PC SP 1 PC= SP= PC Rx (1)

102 130 (2) (3) EA (1) =32 (2) = =64K PC 8 PC 256 (3) A EA=PC EA=A EA=(A) EA=Rx+A EA=PC+A ~63 16 (1) 3 (2) 6 (3) 8 (4) 12 (5) log 2 128=7 64~ (1) (2) (3) ~ ~

103 OP OP OP 9 7 OP 16 OP 4-4 (4) ~ ~ (5) ~ AB AB AB C char str[]= abcde ; int i=0x ; str 5 6 i a b c d e \

104 C ( ) (1) struct { double i; // 0x } S1; (2) struct { int i; // 0x int j; // 0x } S2; (3) struct { short i; // 0x1112 short j; // 0x1314 short k; // 0x1516 short l; // 0x1718 } S3; (1) (2) (3) (1) 64 (2) 3 (3) 16 (4) / (LOAD/SRORE) (5) 64KB /

105 4 133 (1) 64 8 (2) KB 16 (3) (4) / (LOAD/SRORE) (5) PC C5H???? E2 16 C=1 C4 16 C= C=0 C CPU A B A B C N V Z A B B 1 A A B A B C=1 N=1 1 V=0 1 Z=0 0

106 A B A B A<B C=1 C Z A B C Z A B A B C=0 Z=0 A B C=1 Z=1 A B C=0 A B Z=1 A B C=1 A B Z=0 (1) A B 0 C=0 Z=0 (2) A B 0 Z=1 C=0 (3) A B 0 C=1 C=1 (4) A B C=1 0 Z=1 C=1 Z=1 (5) A B 0 Z=1 Z=1 (6) A B A=B Z=0 25 A B A B S Z V A B A B A B (S V)=0 Z=0 A B (S V)=1 Z=1 A B (S V)=0 A B Z=1 A B (S V)=1 A B Z=0 (1) A B A B (V=0) (S=0 S ) = =0.001 (AB ) = =0.001 (AB ) = =0.110 (AB ) (V=1) (S=1) = =1.010 (AB ) 0 Z=0 S V=0 Z=0 (2) A B A B (V=0) (S=1)

107 = =1.111 (AB ) = =1.111 (AB ) = =1.010 (AB ) (V=1) (S=0) = =0.110 (AB ) S V=1 (3) A B A<B (S V)=0 (4) A B A>B (S V)=1 Z=1 (5) A B 0 Z=1 Z=1 (6) A B A B Z=0 26 N V Z C (1) (2) (3) (4) (1) C + Z 1 A B A B>0(C=0) 0(Z=0) C+Z=0 (2) C+Z 1 A B A B<=0 (C=1) 0(Z=1) C+Z=1 (3) N V A B A<B A B (V=0) (N=1) (V=1) (N=0) N V= = =1.111 (AB ) = =1.111 (AB ) = =1.010 (AB ) = =0.110 (AB ) (4) N V N V 1 27 [a b+c+d e+f f] b+c+d a b c d e f push a push b mult push c add push d

108 136 push e mult add push f push f mult add push b mult push c add push d add 28M-M R-R A=B+C PUSH POP M-M 3 R-R 3 LOAD STORE M-M R-R LOAD B PUSH B ADD A,B,C LOAD R1,B ADD C PUSH C LOAD R2,C STORE A ADD ADD R3,R1,R2 POP A STORE A,R A=B+C; B=A+C; D=A B

109 M-M R-R M-M R-R LOAD B PUSH B ADD A,B,C LOAD R1,B ADD C PUSH C ADD B,A,C LOAD R2,C STORE A ADD SUB D,A,B ADD R3,R1,R2 ADD C POP A STORE A,R3 STORE B PUSH A ADD R1,R2,R3 LOAD A SUB B PUSH C ADD STORE B,R1 SUB R4,R3,R1 STORE D POP B STORE D,R4 PUSH A PUSH B SUB POP D M-M R-R F = (A B)/(C+D*E) A B C D E F a b c d e f 4-11

110 M-M R-R push a push b sub push c load d mult e add c store f mult t1,d,e add t1,t1,c sub t2,a,b div f,t2,t1 load r1,a load r2,b sub r3,r1,r2 load r1,d push d load a load r2,e push e sub b mult r2,r1,r2 mult add div pop f div f store f load r1,c add r2,r2,r1 div r1,r3,r2 store r1,f

111 5 CPU CPU CPU CPU CPU CPU CPU 2 CPU CISC 1 IR 2 PC 3 DR 4 AR 5 SR RISC

112 140 3 CPU CPU CPU PC IR 2 CPU 1 2 CPU CPU CPU add r1, r2, r3 r2 r3 CPU r2 Y r3 Y add r1, r2, r3 r1

113 T1 T2 T1 5 8 END T1 INS1 T1 INS1 + T1 INS2 + = T1 INS1 + INS2 + C

114 142 C = T1 INS1 + INS2 + + T2 INS1 + INS T1 T IRout IR

115 5 143 n n n 3 ROM ROM RAM sequencer 4 1 µpc 1 µpc BCF BAF 2

116 PLA PAL PLA D GAL PAL D 2 CAD 5.2

117 5 145 ROM 1 2 CPU CPU CPU

118 K (SP) 1 CPU a) b) c) d) 2 a) b) c) d) 3 a) b) c) d) 4 a) b) c) d) PC 5 CPU a) b) c) d)

119 a) b) c) d) 7 a) PC b) PC c) d) PC 8 a) b) c) d) 9 a) b) c) d) 10 a) b) c) CPU PC d) a) b) c) d) 12 a) b) c) d) 13 a) b) c) d) CPU 14 a) b)

120 148 c) d) 15 a) b) c) b) 16 a) b) c) d) 17 a) b) c) d) 18 RAM a) b) c) d) 19 a) b) c) d) 20 a) b) c) d) 21 a) b) c) d) 22 a) b) c) d)

121 a) b) c) d) 24 a) b) PC c) d) 25 a) b) PC c) d) 1 d 2 c 3 b 4 b 5 b 6 b 7 a 8 d 9 a 10 d 11 b 12 b 13 a 14 b 15 a 16 b 17 b 18 b 19 a 20 a 21 a 22 c 23 b 24 d 25 a 1 (1) (2) (3) (4) CPU (IR)(PC)(DR) (AR)(SR) 2

122 ROM EPROM RAM 7 8 n n n n n n n 2 n 1

123 ROM ROM 16 ROM ROM 8GB 32 ROM ROM 11 ROM D CAD (1) AR AR, AR 0 (2) R1 R2, R1 R3 (3) PC AR, PC PC+1 (1) AR (2) (3) PC PC IR PC MAR MDR ALU Y

124 152 ALU ALU Z 2 CPU (1) R2 Memory[MAR] (2) Memory[MAR] R3 (3) R5 Memory[R5] (1) MAR R2 MAR, read DBUS MDR R2 (2) R2 MAR MAR R2 MDR, write (3) R5 R5 R5 MAR, read DBUS MDR R5 3 MOVE R1,R2 R1 R2 PC MAR PC MAR PC 1 PC PC+1 PC MDR IR DBUS MDR IR R1 R2 4 MOVE mem1,mem2 mem1 mem2 PC MAR PC MAR PC 1 PC PC+1 PC MDR IR DBUS MDR IR IR(mem1) MAR

125 5 153 DBUS MDR IR(mem2) MAR 5 MOVE mem1 (mem2) mem1 mem2 PC MAR PC MAR PC 1 PC PC+1 PC MDR IR DBUS MDR IR IR(mem1) MAR Y DBUS MDR Y IR(mem2) MAR DBUS MDR MAR Y+0 Z Y MDR 6 CPU (1) ADD R1,(mem) (2) STORE (mem),r1 (1) R1 R1 PC MAR, PC+1 PC DBUS MDR MDR IR IR() MAR, DBUS MDR MDR MAR, DBUS MDR MDR Y

126 154 R1+Y Z Z R1 (2) R1 PC MAR, PC+1 PC DBUS MDR MDR IR IRMAR, DBUS MDR MDR MAR R1 MDR, R2 7 MIPS j MIPS [1] PC 4 (1) IR = Memory[PC] PC = PC + 4 (2) PC = IR[25 0] << 2 8 CPU 3 (1) ADD R1,R2 ; R1+R2 R1 (2) ADD R1,(R2) ; R1+(R2) R1 (3) ADD R1,(mem) ; R1+(mem) R1 PC MAR, PC+1 PC DBUS MDR IR R2 Y R1 + Y Z Z R1 PC MAR,

127 5 155 PC+1 PC DBUS MDR IR R2 MAR, DBUS MDR MDR Y R1 + Y Z Z R1 PC MAR, PC+1 PC DBUS MDR IR IR(mem) MAR, DBUS MDR MDR MAR, DBUS MDR MDR Y R1 + Y Z Z R PC MAR PC + 1 PC DBUS MDR R2 Y MDR IR R2 MAR IR(mem) MAR DBUS MDR MDR MAR DBUS MDR MDR Y R1 +Y Z Z R

128 CPU PC MAR PC + 1 PC DBUS MDR R2 Y MDR IR R2 MAR IR(mem) MAR DBUS MDR MDR MAR DBUS MDR MDR Y add sub mult div R1 +Y Z R1 Y Z R1 Y Z R1 Y Z Z R CPU 3 9 ADD (R1), R2 PC MAR, PC+1 PC DBUS MDR IR R1 MAR, MBUS MDR

129 5 157 MDR Y R2 + Y Z Z MDR, PC MAR PC + 1 PC DBUS MDR MDR IR R1 Y R1 MAR IR(mem) MAR DBUS MDR MDR MAR DBUS MDR MDR Y R2 +Y Z R2 MAR IR(mem) MAR MBUS MDR MDR MAR MBUS MDR MDR+Y Z Z R2 Z MDR, MAR

130 CPU ADD R3,R1,R2 // R1+R2 R3 MOVE R1,R2 // R1 R2 MOVE R1,mem // R1 mem MOVE mem,r1 // mem R1 MOVE mem1,mem2 // mem1 mem2 JMP #A ADD PC MAR PC+1 PC DBUS MDR MDR IR R1 Y R2+Y Z Z R3 MOVE PC MAR PC+1 PC DBUS MDR MDR IR R1 R2 MOVE PC MAR PC+1 PC DBUS MDR MDR IR IR(mem) MAR R1 MDR, MOVE PC MAR PC+1 PC DBUS MDR MDR IR IR MAR, DBUS MDR R1 MOVE PC MAR PC+1 PC

131 5 159 DBUS MDR MDR IR IR(mem1) MAR DBUS MDR IR(mem2) MAR JMP PC MAR PC+1 PC DBUS MDR MDR IR PC Y IR+Y Z Z PC 5-4 PC MAR PC + 1 PC DBUS MDR ADD MOVE1 MDR IR MOVE2 MOVE3 MOVE4 JMP R1 Y R1 R2 IR MAR IR MAR, IR MAR, PC Y R2+Y Z R1 MDR, MDR R1 DBUS MDR IR+Y Z Z R3 IR MAR, Z PC BCF BAF 16 BCF BAF 1024 = 2 10 BAF 10 BCF = 6 13 PC MAR

132 160 PC+1 PC DBUS MDR MDR IR PCout MARin PC+1 MDRin MDRout IRin 6 PC PCout MAR MARin PC+1 PC MDRin MDRout IRin T1 T2 T3 T4 T5 D Q D Q D Q D Q D Q Q Q Q Q Q CLK CPU ADD R3,R1,R2

133 5 161 LOAD mem,r1 STORE mem,r1 JMP #A ADD,LOAD,STORE JMP (1) 5-6 T1 T2 T3 T4 T5 ADD IR LOAD STORE JMP 5-6 (2) ADD T1 PCout, MARin, PC+1, Read ;PC MAR, PC+1, read T2 MDRout, IRin ;MDR IR T3 R1out, Yin ;R1 Y T4 R2out, Zin, ADD ;R2+Y Z T5 Zout, R3in ;Z R3 LOAD T1 PCout, MARin, PC+1, Read ;PC MAR, PC+1, read T2 MDRout, IRin ;MDR IR T3 IRout, MARin, Read ;IR MAR, read T4 MDRout, R1in ;MDR R1 STORE T1 PCout, MARin, PC+1, Read ; PC MAR, PC+1, read T2 MDRout, IRin ;MDR IR T3 IRout, MARin ;IR MAR T4 R1out, MDRin, Write ;R1 MDR, write JMP T1 PCout, MARin, PC+1, Read ; PC MAR, PC+1, read T2 MDRout, IRin ;MDR IR T3 PCout, Yin ;PC Y T4 IRout, ADD, Zin ;IR+Y Z

134 162 T5 Zout, PCin ;Z PC (3) PCout=T1+JMP*T3 PC+1=T1 MARin=T1+STORE*T3+LOAD*T3 MDRout=T2+LOAD*T4 Read=T1+LOAD*T3 IRin=T2 R1out=ADD*T3+STORE*T4 Yin=ADD*T3+JMP*T3 R2out=ADD*T4 Add=ADD*T4+JMP*T4 Zin=ADD*T4+JMP*T4 Zout=ADD*T5+JMP*T5 R3in=ADD*T5 IRout=LOAD*T3+STORE*T3+JMP*T4 R1in=LOAD*T4 PCin=JMP*T5 MDRin=STORE*T4 Write=STORE*T4 END=(LOAD+STORE)*T4+(ADD+JMP)*T ROM ROM (1) (2) PCout PC+1 MARin MDRout Read IRin R1out Yin R2out Add Zin Zout R3in IRout R1in PCin MDRin Write 18 T1 T2 T T ADDT

135 5 163 ADDT ADDT LOADT LOADT STORET STORET JMPT JMPT JMPT (3) T1 T xx10 ADD LOAD STORE ADDT3 LOADT3 STORET ADDT4 LOADT4 STORET ADDT JMP 1110 JMPT JMPT JMPT (4) (5) 5-7 BCF BAF 4 BAF 18 BCF(1 ) BAF 4 T T xx10 ADDT ADDT ADDT

136 164 LOADT LOADT STORET STORET JMPT JMPT JMPT (T2) BCF 5-8 (18 ) BCF BAF (1) (2) 5-9 S0 S2 S1 ADD LOAD STORE S5 S7 JMP S9 S3 S6 S8 S10 S4 S (3) S S

137 5 165 S S S S S S S S S S IR PC MAR MDR r0 r7 ALU Y ALU ALU Z ADD r1,r2,r3 // r1 r2 + r3 JUMP #a // pc pc +1+ a LOAD r1,1000 // r1 mem[1000] STORE r1,1000 // mem[1000] r1 (1) (2) ER ER 1 (3) (1) 5-10 PC MAR PC + 1 PC DBUS MDR MDR IR add store load jump r2 Y IR( MAR IR( MAR PC Y r3 +Y Z r1 MDR DBUS MDR Y+IR( ) Z Z r1 MDR r1 Z PC 5-10

138 166 (2) 5-11 (3) E 1 PC MAR PC + 1 PC DBUS MDR MDR IR add store load jump r2 Y IR( MAR IR( MAR PC Y 1 E r3 +Y Z r1 MDR DBUS MDR Y+IR( ) Z Z r1 MDR r1 Z PC C 0 C 9 C i N i N i i N i (1) =34 (2) =

139 I 1 I 2 I 3 I 4 I 5 a, c, e, g, i a, b, d, f, h, j a, d, e, f a a, d, j a b c d e f g h i j I 1 I 2 I 3 I 4 I 5 c, g, i b h 10 7 b c e j a bh cgi d e f j b,c,d e,f,g h,i,j ( )

140 168 (1) (2) (1) (2) BCF 4 BAF 7 µar µir A D BCF BAF CPU CPU 5-13 CPU PC A MAR Z B R1 A ALU A R2 B ALU B

141 5 169 / IR PC MAR A MDR B R 0 R n 1 SR A ALU B Z 5-13 CPU

142 CPU ( ) ( ) 2 1 CPU CPU CPU CPU 2 Cache

143 CPU 1 2

144 m EIA-232-D 2 - CPU 3 UART UART EIA-232-D UART b/s 19200b/s 6.2

145 6 173 UART/ DMA

146 a) b) c) d) 2 a) b) c) d) 3 a) b) c) d) 4

147 6 175 a) b) c) d) 5 a) b) c) d) 6 a) b) c) d) 7 a) b) c) d) 8 a) b) c) d) 9 a) b) c) d) 10 a) b) c) d) 11 a) b) c) d) 12 a) b) c) d) 13 a) b) c) d) 14

148 176 a) b) c) d) 15 a) b) c) d) 16 a) b) c) d) 17 a) b) c) d) 18 n a) n b) 3 c) 2+ log 2 n d) 2n+1 19 n a) n b) 3 c) 2+ log 2 n d) 2n+1 20 a) b) c) d) 21 a) b) c) d) 22 a) b) c) d) 23 a) b) c) d) 24 a) CPU IO b) CPU c) CPU d)

149 a) b) CPU c) CPU d) CPU 26 a) CPU b) c) d) 27 a) b) c) d) 28 / / a) b) c) CPU d) 29 a) b) PROM c) d) 30 a) b) c) d) 1 d 2 a 3 b 4 c 5 b 6 d 7 b 8 c 9 c 10 b 11 c 12 d 13 b 14 a 15 b 16 a 17 c 18 b 19 d 20 b 21 b 22 a 23 d 24 c 25 b 26 c 27 a 28 d 29 a 30 a

150 178 1 backplane (1) 3 (2) (3) 4 5? (1)

151 6 179 (2) PCI PC USB P (1) (2) (3) A D0 D1 D2 D3 D4 D5 D6 D RS-232-C A

152 b/s = = b/s 4 TR0 TR1 TR2 1 BG 0 BG TR0 TR1 TR2 BG 1 x x 0 x 1 x 0 x x TR0 TR1 TR2 BG BR0 BR3 x y BR

153 BR0 BR1 BR2 B R3 BG0 BG1 BG2 BR3 1 x x x x x x BG0 = BR0 BG1 = BR1* BR0 BG2 = BR2* BR1 * BR0 BG3 = BR3* BR2 * BR1 * BR0 6-4 BG0 BG1 BG2 BG3 BR0 BR1 BR2 BR MHz 4 32 (1) T =4/50MHz = = (s) B = 2/T = 2/ = (B/s) (2) 32 B = 4/T = 4/ = (B/s) (3) B = 2 2/T = (B/s)

154 182 (1) (2) (3) 7 50MHz 8 8 Cache (1) (2) (3) 65% 35% (1) T m = (1+3+8) = (s) B m = 8/T m = 33.3MW/S = 133.3MB/S (2) T m = ( ) = (s) B m = 8/T m = 28.6MW/S = 114.4MB/S (3) T m = ( ) 10 9 = (s) B m = 8/T m = 31.50MW/S = 126.0MB/S B m = = MB/S 8 Cache Cache % Cache 60%Cache CPU Cache Cache ( ) = = =

155 (1) 60% 40% (2) 8 (1) = 1/5 = 0.2 W/C W Word C Cycle 2 = = 0.22 W/C (2) 1 = 8/8 = 1 W/C 2 = / /11 = 0.69 W/C (1) (2) 10 33MHz 4 Cache 4 (1) (2) (1) 1+2+4=7 4 4= M/7=75.43MB/s (2) 1+1+4=6 4 4= M/6=88MB/s

156 CRT LCD RLL 2 =

157 RAID RAID-0 RAID-1 RAID-2 RAID-3 RAID-4 RAID-5 RAID-6 RAID RAID 4 WORM 3 WORM 1 0 WORM

158 186 CPU DMA CPU 2 CPU 3 IO CPU CPU CPU CPU CPU CPU CPU CPU

159 7 187 CPU CPU CPU CPU CPU 3 CPU 2 CPU PC 3

160 188 CPU CPU 3 CPU CPU CPU CPU CPU DMA 1 DMA DMA CPU DMA DMA DMA IO CPU 2 DMA DMA DMA 1 1

161 DMA CPU DMA 3 DMA 1 DMA 3 CPU CPU CPU 2 DMA CPU 3 CPU DMA DMA CPU DMA DMA CPU CPU CPU 2 3 2

162 190 CPU RLL 0 1 DMA CPU CPU CPU 1 RAID 2

163 CPU CPU CPU CPU 4 CPU DMA CPU 27

164 192 1 RAID-6 RAID-2 RAID-3 RAID-4 RAID PC 27 1 CRT RAM a) 2µs b) 0.5µs c) 1µs d) 1.5µs 2 CRT a) b) c) d) 3 a) b) c) c)

165 a) b) c) d) 5 a) b) c) ROM d) 6 a) ROM b) c) d) 7 a) b) c) FM d) 8 a) b) c) d) ST506/412 9 a) b) c) d) 10 a) b) c) d) 11 a) b) c) d) a) b) c)

166 194 d) 13 a) b) c) d) 14 RLL a) b) c) d) 15 a) ST506/412 b) ST506/412 c) d) 16 a) 1/2 b) 1/3 c) 2/3 d) 1 17 a) b) c) d) 18 a) b) c) d) 19 I/O a) b) c) d) 20 a) b) c) d) 21 a) b) c) d) 22 a) b) DMA c) DMA d) DMA 23 a) b) c)

167 7 195 d) 24 a) b) DMA c) DMA CPU DMA d) 25 a) b) CPU c) d) DMA 26 a) DMA b) SCSI c) d) 27 a) b) c) d) 28CPU a) b) c) d) Cache 29 a) b) c) d) 30 ALU a) b) c) d) 31 a) b) c) d) 32 a) b) c) DMA d) 33 a) b) c) DMA d) 34 CPU a) b) c) d)

168 a) b) c) d) 36 a) b) CPU c) CPU d) CPU 37 a) DMA b) DMA CPU c) d) DMA 38 DMA CPU DMA a) CPU b) c) d) DMA 39 DMA CPU a) CPU b) c) d) DMA 40 a) b) c) d) 41 a) b) c) d) 42 a) b) DMA c) d) 43 a) b) c) d) DMA 44 CPU a) b) c) I/O d) 45 a) b) c) d) 1 b 2 a 3 a 4 c 5 a 6 d 7 b 8 a 9 c 10 c

169 d 12 d 13 a 14 b 15 d 16 a 17 b 18 d 19 a 20 c 21 d 22 a 23 c 24 b 25 d 26 a 27 c 28 c 29 b 30 a 31 a 32 b 33 c 34 b 35 c 36 a 37 d 38 a 39 b 40 a 41 b 42 d 43 c 44 c 45 d 1 n r/min 4 m 256 (1) (2) (3) (1) m=1024m (2) nm /min (3) 1/(2n) min 2 : (1) CPU (2) (3) (trap) 3 (1) CPU (2) (3) (4) PC (5)

170 CPU CPU CPU (1) (2) (3) (4) (5) 7 CPU CPU 8 CPU CPU CPU

171 CPU 10 DMA DMA DMA 11 DMA DMA CPU DMA DMA DMA CPU DMA DMA CPU 12 DMA DMA CPU CPU DMA CPU CPU CPU

172 Mb/s 6Mb/s 8Mb/s 8Mb/s 7.3 1?? 3 (1) 68ms (2) (3) (4) (5) 48~135 TPI 8717 ~ CD-ROM CD-I DVI Photo CD LV 1982 CD-DA(Compact Disk-Digital Audio) CD-DA CD-DA PCM EFM 120mm 0.12µm 0.5µm ~0.6µm T 0.3µm 11T 3T µm km 8 780nm 1.2m/s

173 7 201 CD-ROM CD-DA CD-ROM CD-ROM 1986 CD-ROM High Sierra High Sierra CD-ROM ISO CD-ROM/XA 1991 CD-R CD-ROM CD-ROM CD-ROM DVD 1996 DVD CD 650nm 635nm 0.4µm 0.74µm 3.49m/s DVD 8-16EFM PLUS RS-PC(Reed Solomon Product Code)DVD 4 DVD 4.7GB 8.5GB 9.5GB 17GB DVD 10.8MB/s DVD rpm (1) (2) (3) (4) (1) 8 2 = 16 (2) 4970 (3) = KB (4) /60 = 1890 KB/s

174 202 4 t s = r = / n = N = t A = t A t A = t s + 1/(2*r) + n/(n*r) 5 20ms 1MB/s 2ms = 0.5/5400 = = 5.6ms = = 20ms + 5.6ms + 0.5KB/1.0MB/s + 2ms = ms = 28.1ms 6 20MB/s 5400rpm 10ms 64KB 0.5ms Cache (1) Cache 64KB (2) Cache 64KB Cache Cache (3) Cache 0.8 (1) = = (1/2)(60/5400) + max{(64/64)( 60/5400),64K/20M} = max{11.11,3.12}=27.17 ms (2) = += =3.65ms (3) = (1 0.8) 27.17= =8.35 ms 7 50s CPU 30s I/O 30s CPU 4 50s CPU I/O 60s 10s T workload = T CPU + T I/O T overlap

175 7 203 T workload T CPU CPU T I/O I/O T overlap CPU I/O CPU S CPU T CPU (1) CPU I/O T I/O (a) T scale = T CPU /S + T I/O T overlap /S CPU T CPU T scale = 30/ /5 = 34 I/O T I/O (2) CPU (b) CPU CPU I/O T worst = T CPU /S + T I/O max{0, T overlap (c) (T CPU T CPU /S)} CPU I/O T worst = 30/ = 36 (d) (3) CPU 7-2 T best = T CPU /S + T I/O min{t overlap, T CPU /S} T best = s CPU I/O 36s CPU 2 CPU I/O CPU I/O S cpu = 3 T scaled = 64/ /3 = 45.3

176 204 T best = 36 T worst = 64/ = 57.3 S cpu =2, S i/o =2 CPU T scaled = 64/2 + 36/2 36/max(2,2) = 32 T best = 32 T worst = 32 CPU T scaled = 64/2 + 36/2 36/max(2,2) = 32 T best = 32 T worst = 64/2 + 36/2 max{0, (36 (64 64/2))} = = L 1 L 2 L 3 L 4 L 5 L L L L L D1 D2 D3 D4 D D1 D2 D3 D4 D5 D1 D2 D3 D4 D5 D D D D D (1) (2)

177 7 205 (3) D1 D2 D3 D4 D5 5 (1) (2) (3) D1 D2 D3 D4 D CPU CPU 3 3 CPU CPU

178 IG IG IGin IGout 1 IGin 0 0 IGout IG 1 BGI 0 IGout 1 IGin 1 IGout 7-6 IGin S Q R IGout IR CPU 50MHz CPU 3 I/O (1) 30 (2) CPU 16 50KB/s (3) 32 2MB/s (1) =3000 ( )

179 7 207 CPU 3000/( )=0.006% CPU (2) 50KB/2B=25K=25600 () = CPU /( )=5% (3) 2MB/4B=512K () = CPU 52.4/50 = 105% CPU KB/s () 100 CPU CPU 50KB/2B = 25K = ( / ) = CPU /( ) = 5% DMA DMA 1000 DMA 500 2MB/s DMA 4KB 50MHz DMA DMA 4KB/2MB = (s) ( )/0.002 = CPU /( ) = 1.5%

180 I/O 100MB/s CPU 80MIPS MB MB TP TPS 10GB TP G/100M = 100 (2+2) = = /4 = M/(4 100) = CPU 80M/64000 = 1250 min(750, , 1250) = G/250M = = /4 = 300 min(300, , 1250) = = 50, /750 = = 50, /300 = CPU 100MB/s I/O TP-1 I/O 100M = CPU = 16GIPS I/O

181 KB/s 200KB/s 6.6KB/s 1.2KB/s 1KB/s 800KB/s 2 6.6KB/s KB/s KB/s = 25.6 KB/s 2 800KB/s KB/s = KB/s 20 SCSI 20MB/s (1) SCSI 500KB/s 4MB/s 6MB/s 20MB/s (2) 4ms 64KB 4ms 256KB (1) r 1 r 2 4 r 1 + n r 2 20 = 20 n = (20 4r 1 )/(20r 2 ) 1 (2) 64KB/4MB/s=16ms 256KB/20MB/s = 12.8ms =16/ 16+4 =0.80 =12.8/ =0.76

182 9 inter-connection network

183 N N 1 1 N(N 1)/2 O(N 2 ) N 1/N

184 252 M M>1 M 1 N M/N m n N 0 1N 1 i (i 1)mod N 0 i N 1 n/2 2 N 1 2 n/2 4 2N 4 ( ) i (i 1)mod N (i+w)modn (j W) mod N0 i N 1 W N/ (n 1) n= N n 2n(n 1) 4 2 n/2 2n 2N Illiac-IV PE 0 PE N 1 PE i PE i+1 PE i 1 PE i+r PE i r r= N i (i+1) mod N i (i-1) mod N i (i+r) mod N i (i-r) mod N 5 n N=2 n n=log 2 N n nn/2 N/2 N