12 Differential Low-Power 6x6 12 bit multiply 1

12 Differential Low-Power 6x6 12 bit multiply 1

2

07 1.1 07 1.2 07 1.2.1 (Sequential Structure Multiplier )07 1.2.2 (Array Structure Multiplier) 09 1.2.3 (Parallel Multiplier) 10 1.2.3.1 10 1.2.3.2 10 1.2.3.3 10 12 2.1 12 2.2 12 2.3 12 2.3.1 Differential and circuit 13 2.3.2 A fully differential full adder (a)the sum-generate circuit. 14 2.3.2 A fully differential full adder (b)the carry-generate circuit.15 2.3.3 A simple sense amplifier circuit16 3

2.3.4 Invert circuit 17 2.3.5 Superbuffer circuit18 2.3.6 bias circuit19 2.3.7 All compose Differential 6X6 multiplication circui 20 21 3.1 Hspice 21 3.2 22 3.3 22 3.4 23 3.5 24 3.6 (Layout)25 27 27 4

1.2.1 (a)08 1.2.1 (b)08 1.2.2 (a)09 1.2.2 (b)09 1.2.2 (c)09 1.2.3 11 2.1 12 2.3.1 Differential and circuit13 2.3.2 (a) The sum-generate circuit14 2.3.2 (b) The carry-generate circuit 15 2.3.3 A simple sense amplifier circuit16 2.3.4 Invert circuit17 2.3.5 Superbuffer circuit18 2.3.6 bias circuit19 2.3.7 All compose Differential 6X6 multiplication circuit20 3.1 Hspice 21 3.3 22 3.4 23 5

3.5 (a) DRC / 24 3.5 (b) Calibre LVS 24 3.6 (a) (Layout)25 2.3.1 Differential and 13 2.3.2 (a) The sum-generate circuit 14 2.3.2 (a) The sum-generate circuit.14 2.3.2 (b) The carry-generate circuit 15 2.3.2 (b) The carry-generate circuit 15 2.3.4 Invert circuit. 17 2.3.5 Superbuffer circuit. 18 3.2 22 3.5 DRC /24 6

1.1 DSP(Digital Signal Processing)CPU 3D DSP (Parallel) : DSP 1.2 1.2.1 (Sequential Structure Multiplier) 1.2.2 (Array Structure Multiplier) 1.2.3 (Parallel Multip lier) () (1.2.1) (Sequential Structure Multiplier) ALU (Shift Register) 1.2.1 (a) 7

n-bit x m-bit m n-bit m (Clock Cycle) 1.2.1 (b) 4-bit x 4-bit n-bit x m-bit m 1.2.1 (a) (b) 8

(1.2.2) (Array Stru cture Multiplier) (a) n 2n (Two-Dimensional Logic Array)(b) (a) (b) (c) 1.2.2 (a) (b) (c) < (b) Cell > 9

(Layout)(Pipeline) (1.2.3) (Parallel Multiplier) 1.2.3 --1.2.3.1-- (Partial Product Generation Block) (Partial Product) --1.2.3.2-- (Compress Tree Block) Sum and Carry vectors Wallace Dadda --1.2.3.3-- (Final Adder Block) 1.2.3 N M 10

Sum vector Carry vector Vectors (M+N) 1.2.3 11

[2.1] A B 2.1 differential cmos circuit 6X6 A bit B bit Superbuffer TSMC 0.35um 2p4m CMOS HSPICE differential [2.2] Differential 6X6 multiplication circuit 1. Differential and circuit. 2.A fully differential full adder(a)the sum-generate(b)the carry-generate circuit. 3.A simple sense amplifier circuit. 4.Invert circuit. 5.Superbuffer circuit. 6. bias circuit 7. All compose Differential 6X6 multiplication circuit 12

[2.3] 2.3.1 Differential and circuit. vdd M3 M6 out out B M2 A M1 A M4 B M5 gnd 2.3.1 Differential and circuit Different and 2.3.1 Differential and a b a b out out 0 0 1 1 ab X 1 1 0 0 X ab X (1) M1 gate(pad a) M2 gate(pad b) High M4 gate(pad a ) M5 gate(pad b ) invert Low M6 gate Low M6 out ab (2) M4 gate(pad a ) M5 gate(pad b ) High M1 gate(pad a) M2 gate(pad b) invert Low M3 gate Low M3 out ab <<(1) ab >> 13

2.3.2 A fully differential full adder (a)the sum-generate circuit (b)the carry-generate circuit. (a)the sum-generate circuit. 2.3.2 (a) The sum-generate circuit 2.3.2 (a) The sum-generate circuit M1 gate Cin M6 gate Cin M2 M8 gate A M3 M7 gate A M4 M9 gate B M5 M10 gate B Cin High invert Cin Low A B High invert A B Low 2.3.2 (a) The sum-generate circuit. b a Cin sum 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 14

(b)the carry-generate circuit. 2.3.2 (b) The carry-generate circuit 2.3.2 (b) The carry-generate circuit M5 gate Cin M8 gate Cin M1 M3 gate A M6 M9 gate A M2 M4 gate B M7 M10 gate B Cin High invert Cin Low A B High invert A B Low 2.3.2 (b) The carry-generate circuit A B Cin Cout 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 15

2.3.3 A simple sense amplifier circuit. 2.3.3 A simple sense amplifier circuit. Sel Low Q5 the sense amplifier power the sense amplifier, Sel high Q5 Q5 low, Q1 Q2 differential data-line, Q1 Q2 Q1 Q3, Q4 Q2 Q1 Q2 sense amplifier high, Q1 Q2 sense amplifier low < simple sense amplifier circuit. Q1 Q2 high > <<Data line >> 16

2.3.4 Invert circuit. 2.3.4 Invert circuit. 2.3.4 Invert circuit. in out 0 1 1 0 in High M0 M1 out Low in Low M1 M0 out High 17

2.3.5 Superbuffer circuit. 2.3.5 Superbuffer circuit 2.3.5 Superbuffer circuit. in out 0 1 1 0 Superbuffer Invert Hspice 20pf 3 35 = u inverter size inverter u bigger than previous one 1 u u 2 u 3 C g C load Total delay time u Total delay ln( x) ln( u) u 2.7 X=Cload/Cg t p 0 18

2.3.6 bias circuit 2.3.6 bias circuit L M1 M0 19

2.3.7 All compose Differential 6X6 multiplication circuit ( cadance ) 2.3.7 All compose Differential 6X6 multiplication circuit Different A A B B A0 A5 B0 B5 high Invert circuit low A0 A5 B0 B5 differential full adder circuit and circuit : S S simple sense amplifier circuit S simple sense amplifier circuit bias bias simple sense amplifier circuit Cload PAD simple sense amplifier circuit S Superbuffer << Hspice >> 20

[3.1] Hspice 3.1 Hspice a5 a4 a3 a2 a1 a0 1 1 1 0 1 1 = 59 b5 b4 b3 b2 b1 b0 1 0 1 1 1 1 = 47 59 X 47 = 2773 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 0 1 0 1 1 0 1 0 1 0 1 = 2773 <<>> 21

[3.2] 3.2 2.5V~ 3.3V 4.8m W 1318 X 1318 10MHz [3.3]: HP 16522A Pattern Generator 12 bits MATLIB LED HP 16522A Pattern Generator 12 22Ω 12 Super Buffer 22

[3.4] Different NO IC YES IC 3.4 23

[3.5] TSMC 0.35um Mixed-Signal 2P4M Polycide 3.5 DRC / D35.X.01.P0.R.1 TSMC IP 1. D35.IO.01.AMS.1.M1 2. D35.IO.01.AMS.1.M2 3. D35.IO.01.AMS.1.M3 4. D35.IO.01.AMS.1.M4 (a) DRC / AMS IO PAD CIC (b) Calibre LVS 3.5 (a) DRC / (b) Calibre LVS Calibre LVS mul6x6.lvs.report FTP CIC MATCH 24

[3.6] (Layout) (Layout) B1 B2 B3 vdd B4 B5 P0 B0 P1 A0 P2 A1 P3 A2 P4 A3 P5 A4 P6 A5 P7 gnd P11 P10 P9 P8 3.6 (a) (Layout) 25

Side Braze 28L inner lead B1 B2 B3 vdd B4 B5 P0 P1 B0 P2 A0 A1 A2 P4 P5 A3 A4 P7 A5 gnd P11 P10 P9 P8 3.6 (b) 26

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