gate level ADMS Power Noise Timing RC RCC Signal Integrity RC RCC Calibre xrc Eldo Hspice spectre DSPF SPEF Calibre xrc reduce thresholds tolerances C

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Calibre xrc 1 Calibre xrc intrinsic coupled substrate 1 1 intrinsic plate 4 5 intrinsic fringe 1 2

1 Calibre xrc 1 Calibre xrc intrinsic coupled substrate 1 1 intrinsic plate 4 5 intrinsic fringe nearbody 3 crossover fringe 6 crossover plate 1 RC 2 Calibre xrc Calibre xrc transistor level

2 gate level ADMS Power Noise Timing RC RCC Signal Integrity RC RCC Calibre xrc Eldo Hspice spectre DSPF SPEF Calibre xrc reduce thresholds tolerances Calibre xrc layout schematic 3 Calibre xrc 2 Calibre xrc 2 Calibre xrc 3 1 xrc 2 Calibre xrc xrc xrc LVS xrc

3 3 1 1 Calibre xcalibrate xcalibrate xcalibrate shielding CAPACITANCE ORDER ndiff pdiff poly1 metal1 metal2 metal1 poly poly metal1 poly Calibre SVRF metal1 0.2ohm metal1 poly1 10ohm, RESISTANCE SHEET METAL1 [0.2 0] RESISTANCE CONNECTION METAL1 POLY1 [10 0] LVS PEX LVS LVS PEX xrc 5 Lumped C RC RCC R-only PEX PEX xrc PEX NETLIST SIMPLE PEX NETLIST LUMPED PEX NETLIST DISTRIBUTED Calibre xrc pdb rcc rules Calibre xrc fmt simple rules Calibre xrc pdb rcc rules Calibre xrc fmt c rules Calibre xrc pdb rcc rules Calibre xrc fmt rc rules Calibre xrc pdb rcc rules Calibre xrc fmt rcc rules Calibre xrc pdb rcc rules Calibre xrc fmt r rules Lumped C RC RCC R

4 PEX xrc //***************************************************************************** LAYOUT PATH.../***.gds LAYOUT PRIMARY layout_topcell_name LAYOUT SYSTEM gds2 ( ) SOURCE PATH.../netlist_name SOURCE PRIMARY schematic_topcell_name SOURCE SYSTEM spice MASK SVDB DIRECTORY.../svdb QUERY XRC LVS xrc LVS REPORT lvs.rep LVS PEX NETLIST SIMPLE.../top.simp HSPICE SOURCE LOCATION PEX hspice PEX NETLIST LUMPED.../top.lump HSPICE SOURCE PEX REPORT LUMPED.../lump.rep PEX hspice PEX NETLIST DISTRIBUTED.../top.dist DSPF SOURCE PEX REPORT DISTRIBUTED.../dist.rep ASCII SOURCE PEX RC RCC DSPF include.../pex.rules include.../lvs.rules ( lvs ) //**************************************************************************** PEX xrc PEX NETLIST SIMPLE PEX NETLIST LUMPED HSPICE SPECTRE HSPICE SPECTRE ELDO PEX NETLIST DISTRIBUTED HSPICE SPECTRE DSPF SPEF ELDO

5 3 1 3 PEX 1 Excluding and selection PEX EXCLUDE LUMPED SOURCE net1 net2 PEX EXCLUDE DISTRIBUTED SOURCE net1 net2 net1 net2 PEX INCLUDE LUMPED net1 net2 PEX INCLUDE DISTRIBUTED net1 net2 net1 net2 net1 net2 PEX EXCLUDE PEX INCLUDE calibre xrc pdb -select xrc PEX INCLUDE PEX EXCLUDE 2 Reduction PEX TOLERANCE DISTRIBUTED TICER Time Constant Equilibration Reduction PEX THRESHOLD PEX REDUCE LUMPED C PEX REDUCE COUPLED( calibre xrc fmt -g ) mgcdocs Calibre xrc LVS Layout vs. Schematic or PHDB Persistent Hierarchical Database DRC LVS LVS DRC LVS Calibre SVRF Standard Verification Rule Format LVS Calibre SVDB Standard Verification Database LVS xrc LVS SVDB LVS topcell.sp PHDB Persistent Hierarchical Database LVS calibre lvs hier spi svdb/layout_spice_file rule_file_name

6 layout_spice_file rule_file_name LVS xrc calibre xrc phdb rule_file_name PDB Parasitic database LVS calibre xrc pdb [ r -c -rc -rcc ] [-select] rule_file_name [ ] rule_file_name Calibre xrc LVS Calibre xrc PDB Parasitic Database Calibre xrc PDB xrc xrc RC RCC coupled C xrc PDB FMT Format Netlists or Reports calibre xrc fmt [-c -r -rc -rcc all] [-g] rule_file_name Calibre xrc PDB /bin/csh f rm rf svdb/*.pdb calibre lvs hier spi svdb/topcell.sp rules tee lvs.log calibre xrc pdb rcc rules tee pdb.log calibre xrc fmt all rules tee fmt.log rules xrc

7 4, 1.a Flat Transistor-Level netlist 2 a Gate-Level Netlist xcell Calibre xrc calibre lvs hier spice svdb/design.sp hcell xcell_list rules calibre xrc pdb rc xcell xcell_list rules calibre xrc fmt all xcell xcell_list rules LVS hcell xcell_list hcell 3. a Hierarchical Netlist xcell_list xcell calibre lvs hier spice svdb/design.sp hcell xcell_list rules calibre xrc pdb rc full xcell xcell_list rules calibre xrc fmt all full xcell xcell_list rules 5 Calibre xrc design.*** design.***.pex design.***.topcell.pxi design.*** design.***.pex RC design.***.topcell.pxi design.***.pex *.pex *.pxi xrc LVS design.sp svdb Calibre RVE calibre rve svdb&

8 3 Calibre RVE Calibre RVE DRC LVS 3 View Net Parasitics 4 4

Find 4 OSCO 5 5 6 Calibre Calibre PEX Cadence.

9 Find 4 OSCO Calibre Calibre PEX Cadence.cdsinit Calibre load ( /usr/calibre/mgc_skl.skl ) icfb Calibre Cadence Calibre 6

10 6 Run PEX 7 7 PEX GUI

11 Rules Inputs LVS Inputs/H-cells PEX x-cells file, xcell Outputs ADMS AdvanceMS license 9

12 10 5 No Inductance default CALIBREVIEW Calibre license 11

13 12 SCHEMATIC LAYOUT 12 Exclude Include Top-Level Nets Recursive Nets xrc xrc

14 Run Control Advanced Show PEX steps in task button bar PEX Generate PDB incrementally xrc PDB PDB PEX PEX Options Setup PEX Options PEX Options PEX Opitons Run PEX xrc PEX GUI xrc 7 Calibre xrc

15 % setenv PEX_*** 1 % setenv PEX_EXTRACT_FLOATING_NETS OFF/ON xrc floating OFF ON 2 % setenv PEX_FMT_GLOBAL VDD;VSS VDD VSS PIN.subckt.global VDD VSS

混訊設計流程_04.PDF

混訊設計流程_04.PDF CIC Referenced Flow for Mixed-signal IC Design Version 1.0 (Date) (Description) (Version) V. 1.0 2010/11/ Abstract CIC IC (Mixed-signal Design Flow) IC (Front End) (Back End) Function Timing Power DRC