ebook105-12

Size: px

Start display at page:

Download "ebook105-12"

裤胥
9 years ago
Views:

1 C P U T x X T y Y T x >T y Y P XY Y X P x = 1 / T x P y = 1 / T y ( ) P y > P x ( ) C P U = # 12.2

2 334 C P U 12-1 a I F I D E X E M E M W B C P U 12-1 b C P U C P U t i n s t t i n s t = t I F + t I D + t E X E + t M E M + t W B ( ) C P U T 1 T 1 t i ( 12-4 ) n s t n n T a C P U I FI D E X EM E MW B a) 1 2 b) 12-1

3 a ) 12-2 φ 12-2 b TT 1 T = max{t I F t I D t E X E t M E M t W B } ( ) 5T T 1 b) C C 1C C 2 C C 1 C C 2 C C 3 C C 4 I F I D E X E M E M 12-4 A D D I n s t 1I n s t 2I n s t 3 I F 12-5 C C 1 I n s t 1 I F C C 2 I n s t 1 I D

4 336 I n s t 2 I F C C 3 I n s t 1 E X E I n s t 2 I D I n s t 3 I F C C 5 I n s t 1 C C 6 I n s t 1 I n s t Inst1 Inst I n s t 1 5T 12-5 I n s t 26T I n s t 37T 5T

5 N t 1 = N 5T= 5N T ( ) t p i p e = 5T + (N- 1 )T = (N+ 4 )T ( ) 5T N- 1T N- 1 N= 1000 t 1 = T t p i p e = T ( ) 5 T a E X E 1 E X E 2 M E M 1M E M 2 T D T D <T 12-6 b T D 7 T D < 5T ( ) T = T D a) b) 12-6

6 I n s t 2 I n s t 1 M E M W B add R1R 8R 9 # R 8 + R 9R 1 sub R2 R 1R 6 #R1- R6R 2 R 8R 9 R 1 R 1 R 6 R 2 S U B A D D 12-7 a) a A D D E X E 12-7 bs U B R 1 R 1 - R 6 R 1 W B 12-7 c S U B SUB R1 R 1 b) a A D DS U B 12-8 bs U B A D D R 2 = R 1 - R 6 = 12-4 = 8 S U B A D D W B R 2 =R 8 + R 9- R6=30-4 = 2 6 c) ADD A D D R a) b) SUB c) ADD WB 12-8 S U B R 1 A D D 12-9 N O P 12-9 A D D S U B

7 A D D W B S U B S U B E X E ADD SUB SUB N O P I FI D E X E M E M W B M E MW

8 340 P C 6 4 M B C M Price = MC (12-10) C t a c c / R A M R A M S R A M S R A 46 R A MD R A MD R A M S R A M D R A S R A M t a c c D R A M D R A M S I M M D I M M D R A M C P U C a c h e S R A M C a c h e K B C a c h e C P U C a c h e C P U C a c h e (CPU) 12-11

9 (CPU) Cache memory (fast) ) C a c h e C P U l ws w C a c h e C a c h e C a c h ec P U C a c h e C a c h b C a c h e C a c h e = / 100 % CPU Cache a) CPU Cache b) Cache C a c h e C a c h

10 342 C a c h e C P U C a c h ec P C a c h e a C P U C a c h e b C a c h e C a c h C a c h e C a c h e C a c h el 1 L1 Cache C a c h el 2 L1 Cache L 1 L2 Cache L1 Cache L2 L 1 C a c h e L 1 CPU Cache a) C a c h e CPU Cache b) Cache Cache () () Cache

11 V L S IC a c h e L1 Cache C a c h e WL( ) C a c h e C a c h e V L S I S R A M C a c h e C P U C a c h e CMOS SRAM M O S 8 68 = CMOS SRAM = 192M O S K C a c h e 1024*192= C a c h e C a c h C a c h e L 1 V L S I 1 2-7I n t e l Pro CPU P G A Intel Pro

12 344 C P U L1 Cache L2 Cache L2 Cache C a c h e C a c h e M E M W B P C C a c h e

13 I n t e l U V V U U W B / F P 1 F P 2F P 2 F o r m a t E r r o r s 60 M H z 66 M H z4 86 C M O S Cache Format Errors Caohe/ Intel I F 2. I D 3. E X E 4. S TO

14 346 T a A T b B T b <T a B A I F - I D - E X E - S TO B A B A P E P E P P E b) c) CPU

15 P E P E P N S N= 1S= 1 S I S D S I S D Inst X R x D S I M D N= 1S> 1 M I S D N> 1S= 1 M I M D N> 1S> 1 S I M D S I M D 4 P E 0P E 1P E 2P E 3 D0D1D2D3 P E 0P E 1P E 2P E 3 R X ( D 0 )R X ( D 1 )R x ( D 2 )R X ( D 3 ) ( ) A D D M I S D SISD SIMD M I S D M I S D D 4 I n s t A I n s t BI n s t CI n s t C 4

16 348 R A ( D )R B ( D )R C ( D )R D ( D ) ( ) M I M D MISD M I M D D0D1D2D3 R A ( D 0 )R B ( D 1 )R C ( D 2 )R D ( D 3 ) ( ) MIMD D S P 4 [A]

17 A 1 A 2 A 3 A 4 4 [B] ( ) ( ) B 1 B 2 B 3 B 4 44 [C] ( ) C α β α β 4 [ 4 ]2 ( ) S I S D 2 *[ A ] 2 *A 1 2 *A 2 2 *A 3 2 *A SIMD

18 350 4 S I M D 2 A 1 A 2 A 3 A P ES I S D S I M S I S D P ( ) S I S D A k B k k = 1234 ( ) S I M D A k B k P E n P E 2n 2 n P P E SIMD SIMD ( )

19 [C] C i j =A i B j ) i, j= 1, 2, 3, 4 S I S D S I M D SIMD SIMD

20 352 P E P E PE P E P E P E P E P E P E P E P E P E P E P

21 N I C a b a) b) n 2 n n P E a 2 P E 3

22 b P E n> 3n = 16 P E4 P E 3 a) 2 b) n=2n=3 n n n= 3 3 n 2 n 1 n 0 n i = n = 4

23 L E D a b a) b) clock ø

24 AT A BT B (a) f = 66 MHz (b) f = 100 MHz (c) f = 300 MHz

25 (d) f = 333 MHz (e) f = 450 MHz t I F = 1. 6 n s t I D = 1. 4 n st E X E = 3. 2 n st M E M = 3. 7 n st W B = 1. 8 n s (a) f 1 (b) 12-2 f 2 (c) t i n s t M H z (a) (b) (c) 6. (a) 12-1 (b) M H z (a) 5 % (b) 8. L 1L (a) (b) I F 88 n s 2 (a) t p i p e (b) 11. S I M D [a][x] 12.

26 358 ( a ) ( b ) ( c ) [Z] = [X] + [Y] 13. ( a ) S I M D [c] = [a] + [b] ( b )( a ) S I M D [c]k ( c ) S I M D K [c] 14. [u] = [u1 u 2 u 3 ] [u] 2 [u]3 [u]1 0 [u][u/ 2 ] ( a ) ( b ) 15. P EM I M D M I M D [ ] 16. n= 3 0x x 1x x 17. n= 3 n 2 n 1 n 0 (a) 101 (b)

27 [ 6 ] 12.7 I A I A [1] Don Anderson and Tom Shanley. Pentium T M Processor System Architecture,2nd ed. R e a d i n g, M A : A d d i s o n - We s l e y, Intel Pentium [2] James M. Feldman and Charles T. Retter. Computer Architecture. New York: McGraw- Hill, 1994.A. [3] David A. Patterson and John L. Hennessy. Computer Organization & Design, 2nd ed. San Francisco: Morg a n - K a u ffman Publishers, R I S C [4] Tom Shanley and Don Anderson. ISA System Architecture, 3rd ed. Reading, MA: A d d i s o n - We s l e y, P C

着力推进提高项目总包能力 ; 加快优势产品进入海外市场 ; 努力盘活资产, 提高经营收现能力 ; 开源节流, 做好资金收支平衡, 确保资金链安全但由于当前重机行业形势仍未明

着力推进提高项目总包能力 ; 加快优势产品进入海外市场 ; 努力盘活资产, 提高经营收现能力 ; 开源节流, 做好资金收支平衡, 确保资金链安全但由于当前重机行业形势仍未明证券代码 :601268 证券简称 : *ST 二重公告编号 : 临 2014-053 二重集团 ( 德阳 ) 重型装备股份有限公司 2013 年年报事后审核意见函回复的公告本公司董事会及全体董事保证本公告内容不存在任何虚假记载误导性陈述或者重大遗漏,