逢甲大學

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1 益老年

3 不易更例不異列 - I -

4 錄錄流錄六來錄 - II -

5 錄錄錄錄錄錄參料錄 - III -

6 料讀讀錄讀數錄錄錄錄錄 - IV -

7 錄錄行錄錄錄錄讀錄錄錄讀錄錄 - V -

8 了說力兩了 - 1 -

9 列邏路列不不 FLEX 10K Devices at a Glance Feature FLEX 10K Devices FLEX 10KE Devices PCI compliance 5.0-V PCI 3.3-V, 66-MHz, 64-bit PCI 33-MHz PCI Density up to 250,000 gates 10,000 to 100,000 gates 30,000 to 200,000 gates Memory support, including dual-port RAM FIFO RAM ROM Dual-port RAM FIFO RAM ROM Phase-locked loop (PLL) 1x, 2x clock multiplication Programmable delay User option 2.5-V, 3.3-V & 5.0-V device options 5.0 V 2.5 V MultiVolt I/O operation 5-V and 3.3-V V CCIO 5-V, 3.3-V, or 2.5-V V CCIO Advanced manufacturing process 0.42 µm 0.22 µm - 2 -

10 Feature UP2 Stratix EPF10K70RC240-4 EP1S10F780C6-ES LE Total RAM bits(on-chip) PLL 6 8 Flash memory 8M Bytes SRAM(static RAM) 1M Bytes SDRAM 16M Bytes Ethernet On-board Ethernet MAC/PHY device 7-segment LED display 2 2 LED 8 I/O pin 連 8 button 2 4 Compact Flash UART Two RS-232 DB9 serial ports Embedded Multipliers 48 Clock rate MHz 50 MHz Memory support, including dual-port RAM PS/2 FIFO RAM ROM Dual-port RAM FIFO RAM ROM D-Sub 了 - 3 -

11 兩都裡裡粒不兩讀讀不讀不列 Input Port Name Required Description data[] Yes 料 address[] Yes 讀 we Yes 1 inclock No clock outclock No 讀 clock Output Port Name Required Description q[] Yes 讀料兩讀兩讀讀不 - 4 -

12 料不量令都列 Input Port Name Required Description wren Yes data[] Yes 料 wraddress[] Yes wrclock No clockpositive-edge-triggered wrclken No clock rden No 讀 rdaddress[] Yes 讀 rdclock No 讀 clockpositive-edge-triggered rdclken No 讀 clock Output Port Name Required Description q[] Yes 讀料料度兩參數不不讀來不說 - 5 -

13 令兩令料都 Nios CPU Architecture Nios CPU Details 32-bit Nios CPU 16-bit Nios CPU Data bus size (bits) ALU width (bits) Internal register width (bits) Address bus size (bits) Instruction size (bits) 論都 Register Groups In registers %r24-%r31 or %i0-%i7 Local registers %r16-%r23 or %L0-%L7 Out registers %r8-%r15 or %o0-%o7 Global registers %r0-%r7 or %g0-%g7 裡都來 - 6 -

14 裡令來 - 7 -

15 理令理令 - 8 -

16 令來說不都理令讀裡兩令令裡來令令裡了來令類令理 - 9 -

17 來令令令裡令令令裡立

18 讀料裡料數邏理兩料兩讀裡

19 NIOS CPU Flash memory Controller SRAM Controller Main system Avalon Bus VGA Controller Display_PIO Finish_pio Button_PIO PS/2 Keyboard Controller

20 了行裡行來來量數料料兩連兩連狀利來裡令行

21 流錄

22 立不了

23 來裡都來便邏不數裡不都數參不裡不

24 來來來不裡

25 不行了浪量不來度浪不

26 令裡了裡狀

27 來數料裡了路度來裡不不浪

28 料令量量行裡論留來來數料行

29 來不不不讀讀兩讀讀兩了率了不不讀來

30 裡了不不行不讀狀不讀了不讀讀讀令裡裡不讀狀料來理令不不料來

31 留不路留來路來說理讀讀讀兩了來讀讀度度讀

32 料了理讀理不讀了讀讀兩讀不

33 降理讀

34 兩讀拉來行兩

35 - 28 -

36 來流立便來拉拉便

37 錄來流立令令流錄立令錄來都錄錄

38 錄兩令數錄兩都不錄兩了錄行列令參數料度錄度

39 來錄錄錄讀

40 錄讀讀令令錄錄

41 了異數料數料數數裡數數數數錄兩不率異量異數度異

42 數兩行兩都率令率狀數了令了讀令數令數了了數數不狀兩度不

43 讀令料度令兩兩數料料來行率論料度不度率降狀不了度了來行了了力不不率不狀

44 都行令令異兩了令令令了

45 裡裡令來論數

46 六來不參數數不來令行行來理來

47 不兩不來說不不不了留了練練立不了立什拉都理什了了不什都不什說了不了不裡了了了來來

48 了了不不不兩來兩了裡不來了什裡兩兩什兩來了不來了理論不數來了令不來兩了來不來都不

49 來來不行量了來裡兩不裡不了了行料說都弄度了兩都讀都來了讀切了流不不流了了了不來不不了來料料

50 令不料來了零度了都行不行不不讀料狀兩了讀料連讀了都論老裡令來料令不兩令不理令連錄不良來路度不良了不路了不不

51 浪不行了來路裡來了鍊了練了了了連串理了數了裡理論了益老磊

52 錄錄

53 錄

54 錄錄錄錄

55 錄錄

56 錄

57 錄行

58 錄錄錄

59 錄錄讀

60 錄錄錄

61 錄讀錄

62 錄 Function name Input parameter Return value features and_reduce arg : STD_LOGIC_VECTOR STD_LOGIC 參數 arg bit AND nand_reduce arg : STD_LOGIC_VECTOR STD_LOGIC 行 and_reduce NOT or_reduce arg : STD_LOGIC_VECTOR STD_LOGIC 參數 arg bit OR nor_reduce arg : STD_LOGIC_VECTOR STD_LOGIC 行 or_reduce NOT xor_reduce arg : STD_LOGIC_VECTOR STD_LOGIC 參數 arg bit XOR xnor_reduce arg : STD_LOGIC_VECTOR STD_LOGIC 行 xor_reduce NOT A_SRL arg shift bit 0 A_SLL arg shift bit 0 arg: std_logic_vector; shift: integer arg: std_logic_vector; shift: integer std_logic_vector std_logic_vector A_TOSTDLOGICVECTOR a: std_logic std_logic_vector std_logic std_logic_vector(0 DOWNTO 0) A_WE_StdLogic STD_LOGIC A_WE_StdUlogic STD_ULOGIC select_arg: boolean; then_arg: STD_LOGIC ; else_arg:std_logic select_arg: boolean; then_arg: STD_ULOGIC; else_arg:std_ulogic STD_LOGIC STD_ULOGIC

63 A_WE_StdLogicVector select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:std_logic_vector STD_LOGIC_VECTOR A_WE_StdUlogicVector select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:std_ulogic_vector STD_ULOGIC_VECTOR STD_LOGIC_VECTOR STD_ULOGIC_VECTOR Vector_To_Std_Logic vector: STD_LOGIC_VECTOR Std_Logic 參數 vector bit TO_STD_LOGIC arg : BOOLEAN STD_LOGIC BOOLEAN STD_LOGIC a_rep arg : STD_LOGIC; repeat : INTEGER STD_LOGIC_VECTOR arg repeat STD_LOGIC_VECTOR(repeat DOWNTO 0) bit 料 arg a_rep_vector arg repeat arg : STD_LOGIC_VECTOR; repeat : INTEGER STD_LOGIC_VECTOR Function name Input parameter Return value features

64 參料

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逢 甲 大 學

逢甲大學