第五章重叠、流水和现代处理器技术

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1 2006 5

3 l t 1 t 2 t 3 t 4 I: add r1,r2,r3 J: sub r4,r1,r5

5 : (Hazard)

6 : (Hazard)

7 Instr 1 Instr 2

8 ( ) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Load Ifetch ALU DMem Instr 1 Ifetch ALU DMem Instr 2 Ifetch ALU DMem Instr 3 Ifetch ALU DMem Instr 4

9 ( ) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Load Ifetch ALU DMem Instr 1 Instr 2 Stall Ifetch Ifetch ALU DMem ALU DMem Instr 3 Ifetch ALU DMem

10 1: ( / ) 2: ( Harvard Architecture )

12 i j i j RAW j i j WAR j i i WAW j i i

13 Read After Write (RAW) ( ) Instr J Instr I I: add r1,r2,r3 J: sub r4,r1,r3 RAW

14 Write After Read (WAR) Instr J Instr I r1 I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7

15 Write After Write (WAW) Instr J Instr I r1 I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7

16 r k (r i ) op (r j ) r k (r i ) op (r j ) r m (r k ) op (r n ) RAW Read After Write r i (r k ) op (r j ) r k (r m ) op (r n ) WAR Write After Read r k (r i ) op (r j ) r k (r m ) op (r n ) WAW Write After Write

17 Range) (Domain) R(i): i D(i): i j i j i RAW R(i) D(j) Ø; WAR D(i) R(j) Ø; WAW R(i) R(j) Ø;

18 RAW ( ) add r1,r2,r3 sub r4,r1,r3 Ifetch Ifetch ALU DMem ALU DMem and r6,r1,r7 Ifetch ALU DMem or r8,r1,r9 Ifetch ALU DMem xor r10,r1,r11 Ifetch ALU DMem

19 RAW Ifetch ALU DMem

20 RAW Load ( ) ld r1, 4(r2) sub r4,r1,r6 and r6,r1,r7 Ifetch Ifetch ALU Ifetch DMem ALU DMem ALU DMem or r8,r1,r9 Ifetch ALU DMem

21 Load Load RAW ( ) ld r1, 4(r2) sub r4,r1,r6 Ifetch Ifetch ALU DMem Bubble ALU DMem and r6,r1,r7 Ifetch Bubble ALU DMem or r8,r1,r9 Bubble Ifetch ALU DMem

22 WAR WAW WAW WAR WAW I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7

23 I: Fadd r1, r4, r3 J: mul r6, r1, r7 I J J I

24 IF ID Issue I: Fmul r1,r4,r3 GPR s J: add r1,r2,r3 FPR s K: mul r6,r1,r7 ALU Fadd Fmul WB I: Fdiv r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Fdiv 1 clock 3 clocks

25 WAR WAW WAR WAW In-order- Issue Out-of-order Complete

28 DIVD F0, F2, F4 ADDD F10, F0, F8 SUBD F12, F8, F10 Out of Order > DIVD F0, F2, F4 ADDD F10, F0, F8 SUBD F0, F8, F14 MULD F6,F10, F0 WAR WAW DIVD F0, F2, F4 ADDD F10, F0, F8 SUBD F100, F8, F14 MULD F6,F10, F100

29 (Scoreboard) CDC 6600

31 CDC6600 (Commit) ( )

32 CDC6600 WAR WAW WAR WAW

33 (Issue) (Read operands) (Execution) (Write Result)

35 CDC6600 FORTRAN ( load/store )

36 Tomasulo 1. IBM 360/91 (1967 ) IBM Robert Tomasulo Rrgister Renaming) ISA Instruction Set Architecture) ISA

37 3. : 4. Tomasulo 90 Alpha HP 8000 MIPS Pentium II PowerPC 604

38 FP Add1 Add2 Add3 Mult1 Mult2 FP FP Common Data Bus (CDB)

39 Tomasulo & FU Reservation Station WAR WAW RS FU (Common Data Bus) FU

40 Op: (+ ) Vj, Vk: Qj, Qk: Qj,Qk=0 Busy: FU FU

41 FP ( ) & ( ) (EX) CDB (WB) CDB : + ( ) ( )

42 Tomsulo

43 I 1 LD f2, 34(r2) 1 I 2 LD f4, 45(r3) I 3 MULTD f6, f4, f2 3 I 4 SUBD f8, f5, f2 1 I 5 DIVD f4, f2, f8 4 I 6 ADDD f10, f6, f4 1 1 (2,1)

44 Outof-order Issue Out-of-order Execution RAW,WAR,WAW

45 I 1 LD f2, 34(r2) 1 I 2 LD f4, 45(r3) I 3 MULTD f6, f4, f2 3 I 4 SUBD f8, f5, f2 1 I 5 DIVD f4, f2, f8 4 I 6 ADDD f10, f6, f (2,1) (2,1)

47 I 1 LD f2, 34(r2) 1 I 2 LD f4, 45(r3) I 3 MULTD f6, f4, f2 3 I 4 SUBD f8, f5, f2 1 I 5 DIVD f4, f2, f8 4 I 6 ADDD f10, f6, f4 1 1 (2,1) (2,1)

48 Tomasulo <=14 <=5 WAR WAW

49 ( )

50 17 / Taken Not Taken

51 ILP

52 for(i=0; i<4k; i++) A[i]=B[i]+C[i]; for(i=0; i<4k; i+=4){ A[i]=B[i]+C[i]; A[i+1]=B[i+1]+C[i+1]; A[i+2]=B[i+2]+C[i+2]; A[i+3]=B[i+3]+C[i+3]; };

53 SUB R4, R5, R6 ADD R1, R2, R3 if R1=0 then ADD R1, R2, R3 if R1=0 then SUB R4, R5, R6

54 > 95% BHT Branch History Table) BTB(Branch Target Buffer)

55 85% J Z 60% J Z 60~70%

56 if (x[i] < 7) y+=1; if (x[i] < 5) c-=4;

57 ---- ( ) ( ) ( ) ( )

58 i+1 i+2 i-1 i p+1 p+2

59 1 0

60 0 2 n n n-1

61 N

62 Fatch PC 0 0 I-Cache Instructions Opcode Offset k BHT Index 2 k -Entry BHT, 2bits/Entry Branch? + Target PC Taken / Taken

63 (1) 2 n (2) 4096 ( 12 ) (3)

64 IF ( BTB ) ( PC ) ( ) PC ( )

65 PC PC Y N PC

66 PC BTB No Yes BTB No Yes PC PC No Yes PC PC BTB BTB

67 Fatch PC I - Cache PC Entry Valid PC Entry k BTB Index = Match Valid Target

chx10_arch02_ilp.ppt [兼容模式]

chx10_arch02_ilp.ppt [兼容模式] 高等计算机系统结构指令级并行处理 ( 第二讲 ) 程旭 2010 年 3 月 29 日复习 : 三种数据冒险对于执行如下类型的指令序列 : r k (r i ) op (r j ) 真数据相关 (True Data-dependence) r 3 (r 1 ) op (r 2 ) Read-after-Write r 5 (r 3 ) op (r 4 ) (RAW) hazard 反相关 (Anti-dependence)

第五章 重叠、流水和现代处理器技术

第五章重叠、流水和现代处理器技术