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1 Logic Design Lab 邏輯設計實驗 Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B Textbook Recommended Texts 編撰之講義 References. M. Morris Mano, Digital Design, Prentice Hall, 3 rd Edition 2. T. L. Floyd, Digital Funcanentals with VHDL, Prentice Hall Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall, Thomas & Moorby s, The Verilog Hardware Description Language, 5th edition, KAP, 22. 2

2 Grading 兩人一組 每次實驗均須助教驗收, 下次實驗前繳交實驗報告 每次驗收 (3%) 每次報告與基本驗收以外之實驗成果 (3%) 共計 2 次實驗 期末個別上機測試 (28%) ( 公開題庫 ) 曠課一次扣總分 分, 滿 3 次即不及格 遲到一次扣總分 3 分, 病假需有醫師之診斷證明 上課期間, 使用電腦進行非關本課程之事者, 每紀錄一次, 扣總分 分 3 Part : Solderless breadboard ( 麵包板 ) Goal: Use standard (fixed-function) IC to design digital circuits on solderless breadboard. Lab Room: SF55 Lab : Decision machine 表決器 Lab 2: Frequency devider 除頻電路 Lab 3: BCD-counter and Display 4 2

3 Part 2: Design with Verilog HDL Goal: Design circuit with HDL and use CAD tool to synthesize and simulate the design. Lab Room: SF 742 Lab 4: Verilog Introduction Lab 5: Quatus II (CAD tools) (Draw schematic & use HDL) Lab 6: Basic combinational circuit module: MUX, decoder, encoder Lab 7: Basic Arithmetic combinational circuit: A 4-bit Adder-subtractor Lab 8: Latch and Flip-flip Lab 9: Counter Lab : shifter and Johnson counter Lab : State machine 5 Part 3: Prototyping design on CPLD(FPGA) with UP2 board Goal: Prototype your digital design on a CPLD(FPGA) board Lab Room: SF 742 Lab 2: Sequence detector Lab 3: Digital timer Lab 4: Traffic light 6 3

4 IC Packages Source: Floyd, Digital Fundamentals with VHDL, Fig SMT Package Configuration Source: Floyd, Digital Fundamentals with VHDL, Fig

5 Pin Numbering Source: Floyd, Digital Fundamentals with VHDL, Fig IC Function and Parameters Function TTL series Performance characteristics Propagation delay time 5

6 Fixed-Function ICs Pin Configuration Source: Floyd, Digital Fundamentals with VHDL, Fig. 3-5 Partial Data Sheet for a 74HC (Quad 2- Input NAND Gate) Source: Floyd, Digital Fundamentals with VHDL, Fig

7 DC Characteristics V IH (V IL ): input high (low) voltage V OH (V OL ): output high (low) voltage I IH (I IL ): input high (low) current I OH (I OL ): output high (low) current I CCH (I CCL ): Total supply current when the output is high (low). Note the range: min, typ, max 3 Performance (AC) Characteristics Propagation delay time = (t PHL + t PLH )/2 Source: Floyd, Digital Fundamentals with VHDL, Fig

8 Power Dissipation I CCL (I CCH ): The supply current for the low (high) output state P = Vcc x (I CCH +I CCL )/2 5 IC Technologies Logic family 74 74L 74LS 74S 74H 74ALS 74AS 74HC Propagation delay (ns) Power dissipation (mw) Characteristics Standard TTL Low-power LP Schottky Schottky High-speed Advanced LS Advanced S High speed MOS 6 8

9 Fan-out and Loading Fan-out: the maximum number of inputs of the same series in an family that can be connected to a gate s output an still maintain the output voltage levels within specified limits I OH / I IH I OL /I IL Source: Floyd, Digital Fundamentals with VHDL, Fig Printed Circuit Board Source: Floyd, Digital Fundamentals with VHDL 8 9

10 Solderless breadboard 9 Logic Design with Verilog A B C eseg e module binarytoeseg (input A, B, C, D, output eseg); C ~D A B ~B ~D D g g2 g3 p p2 p3 g5 eseg nand g (p, C, ~D); nand g2 (p2, A, B); nand g3 (p3, ~B, ~D); nand g4 (p4, A, C); nand g5 (eseg, p, p2, p3, p4); endmodule Verilog structural description A C g4 p4 Schematic 2

11 Logic Design with Verilog (Behavioral description) 2 Design creation and simulation using EDA tools (Quatus II) 22

12 UP2 Block Diagram 23 PLD (Programmable Logic Device) Source: Mano, Digital Design, 3th edition. 24 2

13 Types of PLDs Source: Mano, Digital Design, 3th edition. 25 FLEX K Device block diagram Source: Altera 26 3

14 Logic Element Source: Altera 27 4

15 Logic Design Lab : Decision machine Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 練習設計組合邏輯電路之方法, 並使用標準 IC, 在麵包板上實現之 2

16 Design Procedures for Combinational Circuits From the specification, determine the number of input/output variables and assign a letter symbol to each. Derive the truth table that defines the required relationships between inputs & outputs. Obtain the simplified Boolean function for each output. Draw the logic diagram Function Select appropriate ICs to realize the circuit 3 3-input Decision machine 4 2

17 Logic Circuit 5 IC (integrated Circuit) SSI (Small Scale IC): gate number <= MSI (medium Scale IC): <gate number <= LSI (Large Scale IC): < gate number <= VLSI (Very Large Scale IC) : gate number > 不同製程技術 TTL : 速度較快, 面積較大 CMOS: 速度較慢, 面積較小 6 3

18 Standard ICs 74 Function table 74 Function table 注意 VCC 與 GND 的位置, 接腳輸入或輸出方向 Source: 7 IC Family and Characteristics Logic family 74 74L 74LS 74S 74H 74ALS 74AS 74HC Propagation delay (ns) Power dissipation (mw) Characteristics Standard TTL Low-power LP Schottky Schottky High-speed Advanced LS Advanced S High speed MOS 8 4

19 IC Characteristics Propagation delay: T pd =(t PLH +t PH L)/2 Power dissipation per gate: P d =(V cc (I CCH +I CCL )/2)/G (per gate) Max fanout the number of gate inputs that a gate output can connect to I OH /I IH = I OL /I IL 9 Source: Floyd, Digital Fundamentals with VHDL 5

20 麵包板+每行的 a ~ e 及 f ~ j 相連接 列相連極和-極整使用.5mm 單心線 電阻值 第一位數第二位數指數 容許誤差 顏色 黑 棕 紅 澄 黃 綠 藍 紫 灰 白 金 銀 無色 第一位數 第二位數 指數 x x= 容許誤差 ± 5% % 2% 2 6

21 注意事項 接線與安插元件時, 關掉電源 電源供應器勿超過 5V 麵包板上, 電源線 ( 紅色 ) 與接地線 ( 藍色 ) 勿短路 瞭解 IC 腳位 LED( 二極體 ) 正負端勿接反 ( 長腳為正 ) 指撥開關 ON 代表短路 使用正確之電阻 LED: 限流 ma~3ma TTL: 高電位直接輸入, 接 k~k 電阻 3 問題與討論 為何連接 LED 之電阻選用 33Ω, 而連接 IC 輸入端之電阻使用 KΩ 之電阻? 請使用本實驗 IC 實現一個 3-input XOR function 利用成本接近之 IC, 來完成本實驗電路 ( 只需畫出電路即可 ) 4 7

22 實驗報告撰寫 (/2) 邏輯設計實驗報告 實驗名稱 : 表決器設計 學生 : 王大公 李小門 98 限用 A4 5 實驗報告撰寫 (2/2) 一 實驗目的二 實驗器材三 實驗內容四 實驗結果五 問題與討論 6 8

23 Logic Design Lab 2: Frequency Divider Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 瞭解循序邏輯電路, 熟悉計數器使用方法, 用以設計除頻電路 2

24 4-bit Binary Counter with Parallel Load (7463) Source: 3 Waveform of 4-Bit Synchronous Counter Clock QA QB QC QD 4 2

25 Mod (Divide-by-) Waveform QD and Clear both are divide- wave 5 Circuit Diagram Correct 6 3

26 Use carry out (mode 2) Source: Mano, Logic Design, 3th edition, Problem Construct a counter that counts from to 64 (mod 65) Source: Mano, Logic Design, 3th edition, Problem

27 問題與討論. 請利用 IC 7463 設計出一個除 8 的除頻器 ( 畫出電路圖即可 ) 2. 實驗結果我們所得除頻之 duty cycle 並非為 比, 請問要如何使 duty cycle 為 比? 3. 請利用數個 IC 7463 設計出一個除 的除頻器 ( 畫出電路圖即可 ) 今日完成驗收 3 者可加分 9 5

28 Logic Design Lab 3: BCD Counter and 7-Segment Displayer Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 瞭解循序邏輯電路, 熟悉 BCD 計數器原理與使用方法, 並使用七段 LED 顯示器來顯示計數數值 2

29 Circuit Diagram 7-Segment LED controller BCD counter 3 BCD Ripple counter (Fig. 6-) Source: Mano, Logic Design, 3th edition, Fig

30 Synchronous BCD counter (Fig. 6-5) Source: Mano, Logic Design, 3th edition, Fig BCD counter (749) (Ripple & Synchronous ) Source: 6 3

31 BCD counter (749) JK 未接者視為接地 為何使用兩個 clock 訊號? Q2 clock 係 Q (ripple) Source: Q2, Q3, Q4 係 synchronous Q3 何時為? 此 counter 如何從 9 歸? 7 BCD Counter Waveform Clock / CP Q /CP Q Q2 Q3 8 4

32 Multi-digit BCD counter Q3 ( 本圖之 Q8) 作為下一級之 clock (CP) 9 7 Segment LED 共陽 ( 共陰 ) 5V 5

33 BCD-To-7-Segment Decoder 問題與討論 參考 Fig.3-3 真值表, 畫出 IC 7447 的電路圖 請將此次實驗電路的 IC 749 改由 IC 7463 實現, 畫出電路圖即可 七段顯示器有共陰及共陽兩種, 請說明此兩種七段顯示器有何區別, 如何辨識? 2 6

34 Logic Design Lab 4 Verilog introduction introduction Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B Use CAD Tools to design and verify logic circuits Create design Draw schematic Use HDL (e.g. Verilog), like C programming Verify design: give test patterns, and check if outputs meet specification. Simulation Graphical input/ouput Embedded test_modules in HDL programs Emulation (Prototyping): FPGA/CPLD Discrete components 2

35 What is an HDL? A Hardware Description Language (HDL) is a high level programming language with special language constructs used to model the function of hardware logic circuits. The special language constructs provide you the ability to: Describe the connectivity (structure) of a circuit Describe the functionality (bhavior) of a circuit Describe a circuit at various levels of abstraction Describe the timing information and timing constraints of a circuit Express concurrency 3 Why Use an HDL? Model the design in higher level of abstraction Reduce the design capturing effort Easy for handling complex design Separate from implementation, increase the protability Potential for design re-use Mix behavioral/structural descriptioms in adesign Model datapath and regular portion of circuit structurally Model control and regular portion of circuit behaviorally Model the design and testbench with the same language 4 2

36 Overview of Verilog Module A verilog module includes the following parts: module module_name(port_name) ; Port declaration Data type declaration Task and function declaration Functionality and structure Timing specification endmodule 5 Structural Description (An SR Latch) A module is defined name of the module module nandlatch (q, qbar,set, reset); ouput q, qbar; input set, reset; nand #2 g (q, qbar, set), g2 (qbar, q, reset); endmodule set g q Port declaration Type declaration type and delay of primitive gates primitive gates with names and interconnections Not for synthesis! Reset g2 qbar 6 3

37 Structural Description (A combinational circuit) module binarytoeseg (input A, B, C, D, output eseg); nand g (p, C, ~D); nand g2 (p2, A, B); nand g3 (p3, ~B, ~D); nand g4 (p4, A, C); nand g5 (eseg, p, p2, p3, p4); endmodule Gate output is an implicit wires C ~D A B ~B ~D A C A B C D g g2 g3 g4 eseg p p2 p3 p4 e g5 eseg 7 Verilog Operator (PP. 52) module binarytoeseg (A, B, C, D, eseg); input A, B, C, D; output eseg; wire p, p2, p3, p4; assign p= c & ~D; assign p2= A & B; assign p3=~b & ~D; assign p4=a & C; assign eseg= ~(p & p2 & p3 & p4) C ~D A B ~B ~D g g2 g3 p p2 p3 g5 eseg // assign eseg = (c & ~D) (A & B) (~B & ~D) (A & C); endmodule A C g4 p4 8 4

38 A behavioral Model of BinaryToESeg module binarytoeseg_behavioral eseg (input A, B, C, D, AB output reg eseg); CD B, C, D) begin eseg =; if (~A & D) eseg=; if (~A & B & ~C) eseg = ; if (~B & ~C & D) eseg = ; end endmodule Sensitive list C-like Procedural statements 9 Behavioral modelling A behavioral model of a module is an abstraction of how the module works. always defines a process Suspend execution of this always process until a change occurs one of variable in the sensitive list. Procedural statement C programming-like Conversely, structural descriptions are concurrent statements. Within an always process, the left side of = must be declared as register. Register does not always need a physical storage. 5

39 Verilog 程式結構 module name signal 宣告 assign assign assign begin. end begin.. end Concurrent running Why use behavioral descrption? Use behavioral model on early design stage. HDLs are designed originally for simulation Write testbench Partial behavioral descriptions can be synthesized to circuits. 2 6

40 Create a Testbench For a Module testbench Test Generator And Monitor Design Under Test (DUT) 3 module_testbench module testbench; wire w, w2, w3, w4, w5; binarytoeseg d (w, w2, w3, w4, w5); test_btoeseg t (w, w2, w3, w4, w5); endmodule 4 7

41 Test module module test_btoeseg (output reg A, B, C, D, input eseg); initial // two slashes introduce a single line comment begin $monitor ( $time,, "A = %b B = %b C = %b D = %b, eseg = %b", A, B, C, D, eseg); //waveform for simulating the nand lip lop # A = ; B = ; C = ; D = ; # D = ; # C = ; D = ; # $finish; end endmodule A = x B = x C = x D = x, eseg = x A = B = C = D =, eseg = x 2 A = B = C = D =, eseg = 2 A = B = C = D =, eseg = 22 A = B = C = D =, eseg = 3 A = B = C = D =, eseg = 32 A = B = C = D =, eseg = 5 Interconnection of Design and Test Modules testbench Test Generator eseg And A Monitor B C D Design Under eseg A B C D Test (DUT) 6 8

42 Standard Model of a Moore FSM reset / / Q x clk reset D Q clk ~Q Z / x Q D Q Q clk Input Comb. Circuit State Registers Comb. Circuit Output 7 //D flip-flop module D_FF(D, Q, CLK, RST); input D, CLK, RST; output Q; reg Q; CLK or negedge RST) if(~rst) Q = 'b; else Q = D; endmodule Q x x Q clk reset D clk D clk Q Q ~Q Q module state_machine(x, reset, clk, z); input x, Reset, clk; output z; wire D, D; assign z =~Q & Q; assign D =Q & x; assign D= x Q; D_FF A(D, Q, clk, reset); D_FF A(D, Q, clk, reset); endmodule Z 9

43 Continuous assignment Continuous assignments provide a means to abstractly model combinational hardware driving values onto nets. always@(q, Q) z=~q & Q; assign z = ~Q & Q; e.g. assign a = (b & c) (~a & d); // bitwise logic assign a = b+c; //arithmetic assign a = b >> 2; //shift 9 behavioral model of FSM module fsm (output reg z, input x, clk, reset reg [:] curstste, nextstste; curstate) begin z=~curstate[] & curstate[]; nextstate=; if (curstate ==) if (x) nextstate=; if (curstate ==) if (x) nextstate=3; if (curstate ==3) if (x) nextstate=3; else nextstate =; end end reset / / / 2

44 D_FF clk, negedge reset) begin if (~reset) curstate = ; else curstate = nextstate; end endmodule 2 Model hardware concurrency Verilog is a parallel HDL. Model HW concurrency: Continuous assignment assign v = x + y + z; Procedural block c or d) begin v = c +d + e; w = m n; end Note: Any continuous assignment can be rewritten as a procedural block. 22

45 Nondeterminism When multiple processes execute simultaneously, how these processes are scheduled? Example : Execute in zero time. Different order of execution gives different but correct results. Two processes q = d; assign q = ~d; 23 Nonblocking assignment Use nonblocking assignment to remove the race. Scheduling of nonblocking assignments sample the values of the variables on the right-hand side at the moment the assignment is encountered, and assigns the result to the left-side variables at the end of the current simulation time. 24 2

46 Non-blocking assignment (cont.) module D_FF (D, CLK, Q); input D, CLK; output Q; reg Q; CLK) Q = D; endmodule module D_FF (D, CLK, Q); input D, CLK; output Q; reg Q; CLK) Q <= D; endmodule D D Q q D Q Q clk clk D_FF dff(d, CLK, q); D_FF dff2(q, CLK, Q); 這兩行敘述對調某些模擬器會有不同結果 25 Module Hierarchy board Display driver m6 count clk m555 A counter example 26 3

47 Top module module boardwithconcatenation; Bus concatenation wire clock, eseg, w3, w2, w, w; m6 counter ({w3, w2, w, w}, clock); m555 clockgen (clock); binarytoeseg disp (eseg, w3, w2, w, w); instantiate initial $monitor ($time,,,"count=%d, eseg=%d", {w3, w2, w, w}, eseg); endmodule 27 m6 (Counter) module m6 (output reg [3:] ctr =, input clock); clock) ctr<= ctr+ ; endmodule 28 4

48 A clock generator (simulation) module m555 (output reg clock); initial #5 clock = ; always #5 clock = ~ clock; endmodule 29 Identifier A sequence of letters, digits and underscore (_) except that: The first character must not be a digit Upper and lower case letters are considered to be different Escaped identifiers: allow for any printable ASCII character. Start with \, terminate with white space. \bus-index \a+b 3 5

49 Constants size binary value 3 b 792 d7 2 b_ 2 h7d9 2 o3456 可加入 _, Improve readability 3 module _4bit_adder (S,C4,A,B,C); input [3:] A,B; input C; output [3:] S; output C4; wire C,C2,C3; //Intermediate carries //Instantiate the fulladder fulladder FA (S[],C,A[],B[],C); fulladder FA (S[],C2,A[],B[],C); fulladder FA2 (S[2],C3,A[2],B[2],C2); fulladder FA3 (S[3],C4,A[3],B[3],C3); endmodule 32 6

50 Rules for Synthesizable Combinational Circuits All inputs to your combinational function must be listed in the sensitive list. Combinational output(s) must be assigned to every control path. 33 Example: Mux2to module Mux2to ( input a, b, c, output reg f); a, b,c) if (a == ) f = b; else f = c; endmodule *) 34 7

51 Example: Mux2to (cont.) module Mux2to ( input a, b, c, output reg f); begin f = c; if (a == ) f = b; end endmodule 35 amodule synautosensitivity ( input a, b, c, output reg f); if (a == ) f = b & c ; // else f =? endmodule Inferred Latches 36 8

52 Use case Statement Using Case Statement Using full_case (attributes) explicitly specify (truth table form) or a default item to fully specify. Specify Don t Care situations for input and output. 37 Use case Statement (cont.) Truth table method List each input combination Assign to output(s) in each case item. module fred (output reg f, input a, b, c); (a or b or c) case ({a, b, c}) 3 b: f = b; 3 b: f = b; 3 b: f = b; 3 b: f = b; 3 b: f = b; 3 b: f = b; 3 b: f = b; 3 b: f = b; endcase endmodule 38 9

53 Use case Statement (cont.) module fred (output reg f, input a, b, c); or b or c) case({a,b,c}) 3 b: f = b; 3 b: f = b; 3 b: f = b; default: f = b; endcase endmodule 39 Don t care in Synthesis Rules You can t say if (a == bx) this has meaning in simulation, but not in synthesis. However, an unknown x on the right-hand side will be interpreted as a don t care. ab c x x The inverse function was implemented; x s taken as ones. 4 2

54 Specify don t care (cont.) module caseexample( (output reg f, input a, b, c); (a or b or c) case ({a, b, c}) 3 b: f = b; 3 b: f = b; 3 b: f = b; 3 b: f = b; 3 b: f = b; 3 b: f = b; default: f = bx; endcase endmodule 4 Rules for Synthesizable Sequential Circuits The sensitive list includes only the edges of the clock, reset and preset conditions. Inside the always block, the reset and preset conditions are specified first. if (~reset),,,, Any register assigned to in the sequential always block will be implemented using flipflops. The <= states that all the transfers in the whole system that are specified should occur concurrently. 42 2

55 Latch inferences module synlatchreset( Q, g, d, reset); input g, d, reset; output Q; reg Q; if (~reset) Q = ; else if (g) Q = d; // else Q =? endmodule To infer a latch, two situations must exist in the always statement: At least one control path must exist that does not assign to an output. The sensitivity list must not contain any edge-sensitive specifications. (levelsensitive ) 43 Flip Flop inferences module syndff( q, clock, d); input clock, d; output q; reg q; clock, negedge reset, posedge set) begin if (~reset) q <= ; else if (set) q <= ; else q <= d; end endmodule The form of the description must follow these rule : Always statement must specify the edge for each signal. The first statement follow the always must be if. procedural assignments must either be blocking or non-blocking assignment

56 Conclusion Type of Logic Combinational Interred latch Inferred flip flop Output Assign To An output must be assigned to in all control path There must exist at least one control path where an output is not assign to. From this omission, the tool infers a latch. No affect. Edge Specifiers in Sensitivity List Not allowed. The whole input set must be in the sensitivity list.the assure this. Not allowed. Required from the presence of an edge specifier, the tool infers a flip flop. All registers in the always block are clocked by the specified edge. 45 Lexical convention (/2) White space -> ignored Comments // single line /* multiple lines */ Value: <size><base><value>: 8 b, 8 ha3 <base><value>: h83a <value>: 626 Real value & strings used in writing testbench 46 23

57 Lexical convention (2/2) Identifiers Letters, digits, $, _ The first character shall be a letter or _. Escaped identifier Start with \ Let you use illegal charater Ex. \4:MUX Special token: Start with $ : system task, $monitor Start with # : delay specification, # Start with ` : compiler directives `define, `include, `timescale 47 Four-Valued Logic Verilog Logic Values The underlying data representation allows for any bit to have one of four values,, x (unknown), z (high impedance) x one of:,, z, or in the state of change There is no real gate that drives an x on to a wire. z the high impedance output of a tri-state gate.. Input A Input B Nand x z x x x x x x z x x x A B A 4-valued truth table for a Nand gate with two inputs 48 24

58 Data type --Net wire modeling a standard net wire #3 x2; // a net x2 having a delay Other types: 49 Implicit declaration If an identifier appears in the connection list of an instance of a gate primitive, module, or on the left-hand side of a continuous assignment, it will implicitly be declared a net. If the net is connected to a module port, its default width will be that of the port declaration. Otherwise, it will be a scalar. By default, the type of an implicit declaration is wire. 5 25

59 Data type--register reg rega; reg [7:] a; //specify a range, also used in net reg [7:] table [:3] // 2 32 x 8 memory reg [8:] table [3:][5:]; integer integer a real float a time time a 5 Describing Mealy FSM(/3) Example 52 26

60 Describing FSM(2/3) module Mealy_md ( x, y, CLK, RST); input x, CLk, RST; output y; reg [:] Prstate, Nxtstate; parameter S=2 b, S=2 b, S2=2 b, S3=2 b; // DFF (posedge CLK or negedge RST) if (!RST ) Prstate=S; else Prstate = Nxtstate; //Output function (Prstate or x ) case (Prstate) S: y=; S: if (x) y= b; else y= b; S2: if (x) y= b; else y= b; S3: if (x) y= b; else y= b; // y = (x)? b: b ; endcase 53 Describing FSM(3/3) //next state function (Prstate or x ) case (Prstate) S: if (x) Nxtstate=S; else Nxtstate = S; S: if (x) Nxtstate=S3; else Nxtstate = S; S2: if (x) Nxtstate=S2; else Nxtstate = S; S3: if (x) Nxtstate=S2; else Nxtstate = S; // Nxtstate = (x)? S:S ; endcase endmodule 54 27

61 Operators () Are all Verilog operators synthesizable? Conditional operators e.g. assign a = c? x : y ; Shift operators e.g. assign a = b << 2; Writing test bench or in process, Arithmetic operators do not use assign. e.g. assign a = b+c; assign a = b-c; assign a = b*c; assign a = b/c; assign a = b%c; 55 Operators (2) Logic operators : return a value. &&,,! assign a = b && c; Bitwise logic operators : return result in bus form. &,, ~, assign a[2:] = b[2:] & c[2:]; Equality operator: ==,!= Reduction operator: a = &b; Relational operator: >=, >, <=, < 56 28

62 Quartus II (CAD Tools) Department of Electronic Engineering, FJU 邏輯設計實習 Lab 5:Quartus II (CAD Tools) 實驗目的藉由 draw schematic 與 edit Verilog HDL file 設計一個 4- bit adder 使大家熟悉 Quartus II (CAD Tools) 的使用 Field Programmable Gate Array (FPGA) Quartus II (CAD Tools) Department of Electronic Engineering, FJU Complex Programmable Logic Device (CPLD) FPGA consists of an N x N array of PLB and programmable I/O blocks, connected by a programmable interconnect network. Programmable Logic Blocks Programmable I/O Blocks Programmable Interconnect 2

63 Configuration Memory Quartus II (CAD Tools) Department of Electronic Engineering, FJU 3 Configuration Memory Quartus II (CAD Tools) Department of Electronic Engineering, FJU 4 2

64 Simplified Block Diagram of a CLB (XC4-Family FPGA by Xilinx) C C2 C3 C4 Quartus II (CAD Tools) Department of Electronic Engineering, FJU G4 G3 G2 G F4 F3 F2 F K (clk) Logic Function of G-G4 Logic Function of F-F4 G F Logic function of F, G and H H DIN S/R EC DIN F G H G H DIN F G H H F S/R control S/R control SD D Q RD EC SD D Q RD EC YQ Y XQ X 5 FPGA Configuration Quartus II (CAD Tools) Department of Electronic Engineering, FJU 6 3

65 Altera: The Programmable Solutions Company Quartus II (CAD Tools) Department of Electronic Engineering, FJU Programmable Devices Design Software Intellectual Property (IP) 7 Introduction to Altera Devices Quartus II (CAD Tools) Department of Electronic Engineering, FJU Programmable Logic Families High & Medium Density FPGAs Stratix II, Stratix, APEX II, APEX 2K, & FLEX K Low-Cost FPGAs Cyclone & ACEX K FPGAs with Clock Data Recovery Stratix GX & Mercury CPLDs MAX 7 & MAX 3 Embedded Processor Solutions Nios, Excalibur T Configuration Devices EPC 8 4

66 Introduction to Altera Design Software Quartus II (CAD Tools) Department of Electronic Engineering, FJU Software & Development Tools: Quartus II Stratix II, Stratix, Stratix GX, Cyclone, APEX II, APEX 2K/E/C, Excalibur, & Mercury Devices FLEX K/A/E, ACEX K, FLEX 6, MAX 7S/AE/B, MAX 3A Devices Quartus II Web Edition Free Version Not All Features & Devices Included MAX+PLUS II All FLEX, ACEX, & MAX Devices 9 Quartus II Operating Environment Quartus II (CAD Tools) Department of Electronic Engineering, FJU 5

67 PLD Design Flow Quartus II (CAD Tools) Department of Electronic Engineering, FJU Design Specification LE M4K M52 I/O Design Entry/RTL Coding - Behavioral or Structural Description of Design RTL Simulation - Functional Simulation (Modelsim, Quartus II) - Verify Logic Model & Data Flow (No Timing Delays) Synthesis - Translate Design into Device Specific Primitives - Optimization to Meet Required Area & Performance Constraints - Precision, Synplify, Quartus II Place & Route - Map Primitives to Specific Locations inside Target Technology with Reference to Area & Performance Constraints - Specify Routing Resources to Be Used PLD Design Flow Quartus II (CAD Tools) Department of Electronic Engineering, FJU t clk Timing Analysis - Verify Performance Specifications Were Met - Static Timing Analysis Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology PC Board Simulation & Test - Simulate Board Design - Program & Test Device on Board -Use SignalTap II for Debugging 2 6

68 Design Entry Methods Quartus II (CAD Tools) Department of Electronic Engineering, FJU Quartus II Text Editor AHDL, VHDL, Verilog Memory Editor HEX, MIF Schematic Design Entry 3 rd -Party EDA Tools EDIF HDL VQM Mixing & Matching Design Files Allowed 3 Design Entry Files Quartus II (CAD Tools) Department of Electronic Engineering, FJU Verilog VHDL AHDL Schematic Schematic.bdf.gdf Block File Quartus II Block Editor.bsf Symbol File.tdf Text File.vhd Text File Quartus II Text Editor MegaWizard Manager Top- Level File.v Text File Quartus II Memory Editor Top-level design files can be.bdf,.tdf,.vhd,.vhdl,.v,.vlg,.edif or.edf.edf.edif Text File.v,.vlg,.vhd,.vhdl, vqm Text File Mentor Graphics, Synopsys, Synplicity, etc... Generated within Quartus II Imported from thirdparty EDA tools 4 7

69 Logic Design Lab 6: Basic Combinational Circuit Module Decoder Encoder MUX Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 了解 Decoder Encoder Multiplexer 等電路之操作原理, 使用 Verilog 語言設計電路, 並應用 CAD 軟體來輔助驗證所設計的電路 2

70 2X4 Decoder 注意 high-active or low-active Source: Mano, Digital Design, 3th edition. 3 具有 Enable 功能之 3 對 8 解碼器 Truth Table Input i i i2 X X X enable Output out[:7] 4 2

71 Structural description of 3x8 decoder module DEC_3X8(i, i, i2, enable, out); input i, i, i2, enable; output [7:] out; wire i_n, i_n, i2_n; not g(i_n, i); not g2(i_n, i); not g3(i2_n, i2); and a(out[], i_n, i_n, i2_n, enable); and a2(out[], i, i_n, i2_n, enable); and a3(out[2], i_n, i, i2_n, enable); and a4(out[3], i, i, i2_n, enable); and a5(out[4], i_n, i_n, i2, enable); and a6(out[5], i, i_n, i2, enable); and a7(out[6], i_n, i, i2, enable); and a8(out[7], i, i, i2, enable); end module 5 Behavioral Description of 3x8 decoder module DEC_3X8(i, i, i2, enable, out); input i, i, i2, enable; output [7:]out; reg [7:]out; or i or i or i2) begin 漏掉 i 會如何? 漏掉這行會如何? if (enable = = 'b) begin case ({i, i, i2}) 3'b: out = 8'b; 3'b: out = 8'b; 3'b: out = 8'b; 3'b: out = 8'b; 3'b: out = 8'b; 3'b: out = 8'b; 3'b: out = 8'b; 3'b: out = 8'b; endcase end else out = 8'b; end endmodule 6 3

72 4 7 Priority Encoder X X X X X X X X V y x D3 D2 D D Outputs Inputs Source: Mano, Digital Design, 3th edition. 8 8X3 Priority Encoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X None_ON Out[] Out[] Out[2] In[7] In[6] In[5] In[4] In[3] In[2] In[] In[] Output Input

73 module Encoder_8X3 (In, Out, None_ON); input [7:] In; output [2:] Out; output None_ON; reg [2:] Out; reg None_ON; begin: Encoder_Block integer i; Out = ; None_ON = ; for (i = ; i<8; i = i+) begin if (In[i]) begin Out = i; None_ON = ; end end end endmodule Named block 可否自動轉成電路? 如果是 In[] priority 最高, 程式應改為如何? 9 4X 多工器 Source: Mano, Digital Design, 3th edition. 5

74 8X 多工器 sel [2] Input sel [] sel [] output out i i i2 i3 i4 i5 i6 i7 module MUX_8X(sel, i, i, i2, i3, i4, i5, i6, i7, out); input i, i, i2, i3, i4, i5, i6, i7; input [2:] sel; output out; reg out; or i or i or i2 or i3 or i4 or i5 or i6 or i7) case(sel) 3'b: out = i; 3'b: out = i; 3'b: out = i2; 3'b: out = i3; 3'b: out = i4; 3'b: out = i5; 3'b: out = i6; 3'b: out = i7; endcase endmodule 2 6

75 問題與討論 在 3x8 decoder 範例中, () 若在 always 敘述中的 sensitive list 漏掉 i, 電路有何不同? (2) 另外若漏寫 else out = 8 b, 電路有何不同? 若要完整測試實驗內容中 8 對 3 的優先編碼器 (Priority Encoder), 請問其測試樣本輸入應為何? 請利用數個 4 多工器完成一個 6 的多工器 假設一電腦有四個週邊裝置, 其 I/O 位址空間分配如下表 令其位址 BUS 為 6 bits, 請設計 decoder 電路產生各裝置之 enable 線驗收第 3, 4 題 devices Dev Dev2 Dev3 Dev4 Address range x~xfff x2~x4fff x5~x57ff x58~x5fff 3 7

76 Logic Design Lab 7: A 4-bit Carry Look-ahead Adder and Comparator Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 了解 Carry Look-ahead Adder (CLA) 及 Comparator 等電路之操作原理, 使用 Verilog 語言設計電路, 並應用 CAD 軟體來輔助驗證所設計的電路

77 Ripple Adder The delay is proportional to the bit length. Source: Mano, Digital Design, 3th edition. Carry and Sum in recursive form A i B i P i S i G i C i+ C i P i = A i B i G i = A i B i The output sum and carry can be expressed as S i = P i C i C i+ = G i + P i C i Source: Mano, Digital Design, 3th edition. 2

78 3-bit carry generation C = input carry C = G + P C C 2 = G + P C = G + P (G + P C ) = G + P G + P P C C 3 = G 2 + P 2 C 2 = G 2 + P 2 G + P 2 P G + P 2 P P C Source: Mano, Digital Design, 3th edition. 4-Bit Adder with Carry Lookahead Source: Mano, Digital Design, 3th edition. 3

79 Structure vs. Behavior module adder (output carryout, sum, input ainput, binput, carryin); xor (sum, ainput, binput, carryin); or (carryout, ab, bc, ac); and (ab, ainput, binput), (bc, binput, carryin), (ac, ainput, carryin); endmodule Continuous assignment assign is a form of behavioral modeling for combinational circuits Concurrent with procedural processes ( always ) module adder (output carryout, sum, input ainput, binput, carryin); assign sum = ainput ^ binput ^ carryin, carryout = (ainput & binput) (binput & carryin) (ainput & carryin); endmodule module cla4 (s, cout, A, B,c); input [3:] A; input [3:] B; input c; output [3:] s; output cout; // the following wire declaration can be omitted wire [3:] s; wire cout; wire [3:] g; wire [3:] p; wire [3:] c; assign g[3:] = A[3:] & B[3:]; //carry generation assign p[3:] = A[3:] ^ B[3:]; //carry propagation assign c[] = g[] (p[] & c); //calculate each stage carryout assign c[2] = g[] (g[] & p[]) (p[] & p[] & c); assign c[3] = g[2] (g[] & p[2]) (g[] & p[] & p[2]) (p[] & p[] & p[2] & c); assign cout = g[3] (g[2] & p[3]) (g[] & p[2] & p[3]) (g[] & p[] & p[2] & p[3]) (p[] & p[] & p[2] & p[3] & g[]); assign s[] = p[]^c; assign s[3:] = p[3:] ^ c[3:]; endmodule //calculate summation An identifier appears on the left-side of a continuous assignment implicitly is declared a net. 4

80 Verilog 程式結構 module name signal 宣告 assign assign assign begin. end begin.. end Concurrent running Is the verification enough? 5

81 4-bit Comparator A [3:] = A 3 A 2 A A, B[3:] = B 3 B 2 B B, 令 x i = A i B i + A i B i, (A > B) = A 3 B 3 + x 3 A 2 B 2 + x 3 x 2 A B + x 3 x 2 x A B (B > A) = A 3 B 3 + x 3 A 2 B 2 + x 3 x 2 A B + x 3 x 2 x A B Source: Mano, Digital Design, 3th edition. module magcpm (A, B, ALSB, AGTB, AEQB); input [3:] A, B; output ALSB, AGTB, AEQB; assign ALSB = (A < B); assign AGTB = (A > B); assign AEQB = (A = = B); endmodule Equality operator: ==!= Relational Operator: >, <, >=, <= Single bit 可以多個 bit 6

82 觀察 <,<,== 等運算被轉化成之電路為何? 直接用 +, - 等運算可以實現加減法電路? 問題與討論. 請問在 4-bit Carry Look-ahead Adder 實驗範例中所輸入的波型, 能否驗證出所有邏輯閘誤用之錯誤, 例如在電路中某個 XOR 閘被誤用為 OR 閘等? 請舉例說明 2. 利用本實驗之 4-bit CLA, 設計一個 8-bit Adder-subtractor, 其中負數是用 2 s 補數表示 ( 不含 overflow 電路 ) 3. 使用布林代數之描述, 來完成比較器之設計 今日實驗下課前, 驗收第 2 題 7

83 8

84 Logic Design Lab 8: Latch and Flip-flop Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 了解基本的循序邏輯電路及 Latch 和 Flip-flop 等電路之操作原理, 使用 Verilog 語言設計電路, 並應用 CAD 軟體來輔助驗證所設計的電路 2

85 SR Latch with Control Input Source: Mano, Digital Design, 3th edition. 3 D Latch with Control Input Source: Mano, Digital Design, 3th edition. 4 2

86 Master-slave D Flip-flop (negative-edge) Clock D-input Y Q 5 module MS_DFF(D, CLK, Q); input D, CLK; output Q; wire y; wire CLK_n; assign CLK_n = ~CLK; D_latch D(D, CLK, y); D_latch D2(D, ~CLK, Q); endmodule //D latch module D_latch(D, control, Q); input D, control; output Q; reg Q; or D) if (control) Q = D; endmodule 6 3

87 Behavioral description of negativeedge triggered D Flip-flop /module D_FF (D, CLK, Q); input D, CLK; output Q; reg Q; CLK) Q = D; endmodule 7 JK Flip-flop module JK_FF(J, K, CLK, Q); input J, K, CLK; output Q; wire JK; assign JK = (J & ~Q) (~K & J); D_FF D(JK, CLK, Q); endmodule // D Flip-flop module D_FF (D, CLK, Q); input D, CLK; output Q; reg Q; CLK) Q = D; endmodule Source: Mano, Digital Design, 3th edition. 8 4

88 Verilog 程式結構 module name signal 宣告 assign assign Instantiate modules begin. end begin.. end Concurrent running assign assign always module 9 D flip-flop with RST input //D flip-flop module D_FF(D, Q, CLK, RST); input D, CLK, RST; output Q; reg Q; CLK or negedge RST) if(~rst) Q = 'b; else Q = D; endmodule 5

89 T Flip-flop module T_FF(T, CLK, Q); input T, CLK; output Q; wire DT; assign DT = Q ^ T; D_FF D(DT, CLK, Q); endmodule // D Flip-flop module D_FF (D, CLK, Q); input D, CLK; output Q; reg Q; CLK) Q = D; endmodule Source: Mano, Digital Design, 3th edition. Non-blocking assignment module D_FF (D, CLK, Q); input D, CLK; output Q; reg Q; CLK) Q = D; endmodule module D_FF (D, CLK, Q); input D, CLK; output Q; reg Q; CLK) Q <= D; endmodule D D Q q D Q Q clk clk D_FF dff(d, CLK, q); D_FF dff2(q, CLK, Q); 這兩行敘述對調某些模擬器會有不同結果 2 6

90 問題與討論 今日實驗下課前, 驗收第 3 題. 輸入下列波型到正邊緣觸發之 D Flip-flop,T Flip-flop, 紀錄 Q 之輸出 CLK D 2. 使用 verilog 設計一個 D Flip-flop, 其具有 set 及 reset 兩個 asynchronous input ( 課本 Fig-3) 3. 使用 verilog 設計一個 4 位元具有平行輸入之暫存器 ( 課本 Fig 6-2) 3 4-Bit Register with parallel Load I I A A Source: Mano, Digital Design, 3th edition. 4 7

91 Logic Design Lab 9: Counter Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 了解漣波計數器, 上 下數計數器及 IC 7463 四位元同步計數器之操作原理, 使用 Verilog 語言設計電路, 並應用 CAD 軟體來輔助驗證所設計的電路

92 Ripple Counter Ripple Counter (Verilog code) module ripple_counter (Count, Reset, A, A, A2, A3); input Count, Reset; output A, A, A2, A3; wire A, A, A2, A3; D_FF D(~A, A, ~Count, Reset); D_FF D2(~A, A, ~A, Reset); D_FF D3(~A2, A2, ~A, Reset); D_FF D4(~A3, A3, ~A2, Reset); endmodule 2

93 D flip-flop with RST input //D flip-flop module D_FF(D, Q, CLK, RST); input D, CLK, RST; output Q; reg Q; CLK or negedge RST) if(~rst) Q = 'b; else Q = D; endmodule Up/Down Counter 3

94 module up_down_counter (up, down, CLK, A, A, A2, A3); input up, down, CLK; output A, A, A2, A3; wire A, A, A2, A3; wire T, T, T2, T3; assign T = (up (~up & down) ); assign T = ( (up & A) (~up & down & ~A) ); assign T2 = ( (up & A & A) (~up & down & ~A & ~A) ); assign T3 = ( (up & A & A & A2) (~up & down & ~A & ~A & ~A2) ); T_FF G(T, CLK, A); T_FF G(T, CLK, A); T_FF G2(T2, CLK, A2); T_FF G3(T3, CLK, A3); Endmodule // T-FF 省略 Behavioral Description of 4-bit Up- Down Counter module up_down_counter (up, down, CLK, A, A, A2, A3); input up, down, CLK; output A, A, A2, A3; reg A, A, A2, A3; CLK) if (up = = && {A3, A2, A, A} = = 4'b) {A3, A2, A, A} = 4'b; else if (down = = && {A3, A2, A, A} = = 4'b) {A3, A2, A, A} = 4'b; else if (up = = ) {A3, A2, A, A} = {A3, A2, A, A} + 4'b; else if (down = = ) {A3, A2, A, A} = {A3, A2, A, A} - 4'b; endmodule 4

95 7463 時脈 CLK 為正緣觸發 當 Clear 為 且 CLK 為正緣時, 即將計數器之輸出清除為 載入 (Load) 為同步載入, 當 Load 訊號為 時, 在 CLK 之正緣會將 4 個輸入資料 A B C D 載入到 4 個輸出端 計數器之 Enable P Enable T 兩者均為 時, 計數器才能正常計數 此外,Enable T 可控制 Carry out 提供一個進位訊號, 當計數器多級串接時, 作為下一級計數器的致能信號, 使計數器做同步計數 當輸出狀態為 時,Carry out 輸出一正電位信號 5

96 A A A2 A3 // Behavioral description of IC 7463 module IC7463(A, B, C, D, Clear, Load, enable_p, enable_t, CLK, Qa, Qb, Qc, Qd, Carry_out); input A, B, C, D, Clear, Load, enable_p, enable_t, CLK; output Qa, Qb, Qc, Qd, Carry_out; reg Qa, Qb, Qc, Qd; assign Carry_out = (Qa & Qb & Qc & Qd & enable_t); (posedge CLK) if (Clear = = ) {Qd, Qc, Qb, Qa} = 4'b; else if (Load = = ) {Qd, Qc, Qb, Qa} = {D, C, B, A}; else if (enable_p = = && enable_t = = && {Qd, Qc, Qb, Qa} = = 4'b) {Qd, Qc, Qb, Qa} = 4'b; else if (enable_p = = && enable_t = = ) {Qd, Qc, Qb, Qa} = {Qd, Qc, Qb, Qa} + 4'b; endmodule 6

97 Behavioral description of frequency divider (mod 2) module f_div (RST, CLK, f_out); input RST, CLK; output f_out; reg f_out; reg [3:]q; parameter count = 2; CLK) if (RST = = 'b) begin f_out = ; q = count; end else if (q = = ) begin f_out = ; q = count; end else begin q = q - ; f_out = ; end endmodule Mod 2 7

98 問題與討論 今日實驗下課前, 驗收第 題. 利用兩個 4-bit counter with parallel load ( 如 IC7463), 當控制線 S= 時, 除頻器暫停計數 ; 當控制線 S= 時, 除頻器為一除以 之計數器 2. 假定系統之 clock 為 2MHz, 基於此 clock, 設計一電路產生 clock cycle time 為 5ns, 除頻 之電路, 並其正電位及負電位時間比為 : ( 即 duty cycle 為 5 %) 3. 承上題, 匯出 Quatus II 所產生之硬體電路, 並討論其可能改進之處 8

99 Logic Design Lab : Shifter and Johnson Counter Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 了解 Shift Register 及 Johnson Counter 之操作原理, 使用 Verilog 語言設計電路, 並應用 CAD 軟體來輔助驗證所設計的電路

100 4-bit Serial In Parallel Out (SIPO) Shift Register PISO? 2

101 Behavioral Description of an Universal Shift-Reg module shftreg (s,s,pin,lfin,rtin,a,clk,clr); input s,s; //Select inputs input lfin, rtin; //Serial inputs input CLK,Clr; //Clock and Clear input [3:] Pin; //Parallel input output [3:] A; //Register output reg [3:] A; (posedge CLK or negedge Clr) if (~Clr) A = 4'b; else case ({s,s}) 2'b: A = A; //No change 2'b: A = {rtin,a[3:]}; //Shift right 2'b: A = {A[2:],lfin}; //Shift left 2'b: A = Pin; //Parallel load input endcase endmodule Structural Description of an Universal Shift-Reg module SHFTREG (I,select,lfin,rtin,A,CLK,Clr); input [3:] I; //Parallel input input [:] select; //Mode select input lfin,rtin,clk,clr; //Serial inputs,clock,clear output [3:] A; //Parallel output //Instantiate the four stages stage ST (A[],A[],lfin,I[],A[],select,CLK,Clr); stage ST (A[],A[2],A[],I[],A[],select,CLK,Clr); stage ST2 (A[2],A[3],A[],I[2],A[2],select,CLK,Clr); stage ST3 (A[3],rtin,A[2],I[3],A[3],select,CLK,Clr); endmodule 3

102 //One stage of shift register module stage(i,i,i2,i3,q,select,clk,clr); input i,i,i2,i3,clk,clr; input [:] select; output Q; reg Q; reg D; //4x multiplexer (i or i or i2 or i3 or select) case (select) 2'b: D = i; 2'b: D = i; 2'b: D = i2; 2'b: D = i3; endcase //D flip-flop (posedge CLK or negedge Clr) if (~Clr) Q = 'b; else Q = D; endmodule How to verify 4

103 Four-Stage Johnson Counter Generate Signals Using Johnson Counter 5

104 Four-Stage Johnson Counter (V-code) (/2) module Johnson_counter(CLK, reset, D_out); input CLK, reset; output [7:]D_out; wire [7:]D_out; reg [3:]D; assign D_out[] = ~D[] & ~D [3]; assign D_out[] = D[] & ~D []; assign D_out[2] = D[] & ~D [2]; assign D_out[3] = D[2] & ~D [3]; assign D_out[4] = D[] & D [3]; assign D_out[5] = ~D[] & D []; assign D_out[6] = ~D[] & D [2]; assign D_out[7] = ~D[2] & D [3]; Four-Stage Johnson Counter (V-code) (2/2) CLK) if(reset) D <= ; else begin D[3:] <= D[2:]; D[] <= ~D[3]; end endmodule 6

105 問題與討論 今日實驗下課前, 先驗收第 2 題再驗收第 題 () 請設計一個 8 位元移位暫存器, 規格如下 : 當控制線 S,S2 輸入為 時, 平行載入 ; 當控制線 S,S2 輸入為 時, 在一時脈內向右 shift 位元 ; 當控制線 S,S2 輸入為 時, 在一時脈內向右 shift 2 位元 ; 當控制線 S,S2 輸入為 時, 在一時脈內向右 shift 3 位元 (2) 請利用 Johnson Counter, 設計一電路, 每 6 個 clocks, 重複產生 x y z 三個訊號, 其波形如下 : X Y Z 7

106 Logic Design Lab : State Machine Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 了解狀態機之操作原理, 使用 Verilog 語言設計狀態機電路, 並應用 CAD 軟體來輔助驗證所設計的電路

107 A Sequence Detector x State machine y clk 連續讀入三個 即輸出, 否則輸出 X Y Source: Mano, Digital Design, 3th edition. 設計狀態機電路 由所求電路的設計描述及行為模式, 畫出其狀態圖 化簡其狀態數量 指定二位元值於各個狀態 畫出狀態表 選擇所需正反器之種類 利用激態表 (excitation table), 由狀態之改變, 推導正反器之輸入方程式 另推導輸出及輸出的 由方程式將電路的邏輯圖畫出 2

108 Synthesis Using D Flip-flop Present State Input Next State Output A B x A B y S = S = S 2 = S 3 = Source: Mano, Digital Design, 3th edition. Maps for Sequence Detector Source: Mano, Digital Design, 3th edition. 3

109 Logic Diagram of Sequence Detector Source: Mano, Digital Design, 3th edition. Synthesis Using JK FFs Present State Input Next State Flip-Flop Inputs A B x A B J A K A J B K B X X X X X X X X X X X X X X X X 4

110 Maps for J and K Input Equations Source: Mano, Digital Design, 3th edition. Moore Machine Input Comb. State Comb. Output Circuit Registers Circuit Outputs dependent on state variables only. 5

111 Mealy Machine Outputs dependent on inputs and state variables. Are inputs synchronized with clock? A Moore-Machine Example Source: Mano, Digital Design, 3th edition. 6

112 Structural Description of Moore Machine module Moore_mdl (x,ab,clock); input x,clock; output [:]AB; wire [:]AB; wire Ja, Ka, Jb, Kb; assign Ka = AB[] & ~x; assign Kb = AB[] ^ x; JK_FF J(AB[],Ka,Clock,AB[],Qnot); JK_FF J2(~x,Kb,Clock,AB[],Qnot); endmodule //JK flip-flop module JK_FF (J,K,CLK,Q,Qnot); output Q,Qnot; input J,K,CLK; reg Q; assign Qnot = ~ Q ; (posedge CLK) case ({J,K}) 2'b: Q = Q; 2'b: Q = 'b; 2'b: Q = 'b; 2'b: Q = ~ Q; endcase endmodule Behavioral Description of Moore Machine module Moore_mdl (x,ab,clk,rst); input x,clk,rst; output [:]AB; reg [:] state; parameter S = 2'b, S = 2'b, S2 = 2'b, S3 = 2'b; (posedge CLK or negedge RST) if (~RST) state = S; //Initialize to state S else case (state) S: if (~x) state = S; S: if (x) state = S2; else state = S3; S2: if (~x) state = S3; S3: if (~x) state = S; endcase assign AB = state; //Output of flip-flops endmodule 7

113 module Moore_mdl (x,ab,clk,rst); // 另一種寫法 input x,clk,rst; output [:]AB; reg [:] state; parameter S = 2'b, S = 2'b, S2 = 2'b, S3 = 2'b; (posedge CLK or negedge RST) if (~RST) state = S; else state = next_state; (state or x) case (state) S: if (~x) next_state = S; S: if (x) next_state = S2; else next_state = S3; S2: if (~x) next_state = S3; S3: if (~x) next_state = S; endcase assign AB = state; //Output of flip-flops endmodule A Mealy-Machine Example Source: Mano, Digital Design, 3th edition. 8

114 Mealy state diagram (Fig.5-6) //module Mealy-mdl(x, y, CLK, RST); input x, CLK, RST; output y; reg y; reg [ : ] Prstate, Nxtstate; parameter S =2 b, S =2 b, S2 =2 b, S3 =2 b; (posedge CLK or negedge RST) if(~rst)prstate = S; / / Initialize to state S else Prstate = Nxtstate; / /Clock operations (Prstate or x) case(prstate) / /Determine next state S:if(x) Nxtstate = S; else Nxtstate = S; S:if(x) Nxtstate = S3; else Nxtstate = S; S2:if(~x)Nxtstate = S; else Nxtstate = S2; S3:if(~x)Nxtstate = S2; else Nxtstate = S; endcase (Prstate or x) / /Evaluate output case(prstate) S:y=; S:if(x)y= b; else y = b; S2:if(x)y= b; else y = b; S3:if(x)y= b; else y = b; endcase endmodule 9

115 // 另一種寫法 ( 合併 ) module Mealy_mdl(x,y,CLK,RST); input x,clk,rst; output y; reg y; reg [:] Prstate, Nxtstate; parameter S = 2'b, S = 2'b, S2 = 2'b, S3 = 2'b; (posedge CLK or negedge RST) begin if (~RST) Prstate = S; else begin Prstate = Nxtstate; case (Prstate) S: begin y = 'b; if (x) Nxtstate = S; else Nxtstate = S; end S: if (x) begin Nxtstate = S3; y = 'b; end else begin Nxtstate = S; y = 'b; end S2: if (~x) begin Nxtstate = S; y = 'b; end else begin Nxtstate = S2; y = 'b; end S3: if (x) begin Nxtstate = S2; y = 'b; end else begin Nxtstate = S; y = 'b; end endcase end //end if-else end //end always endmodule

116 問題與討論 今日實驗下課前, 驗收第 題 請設計出一 Mealy machine, 輸入為 X, 輸出為 Z 和 Z2, 當檢測到 X 之輸入順序為 時,Z 輸出為 ; 當檢測到 X 之輸入順序為 時,Z2 輸出為 繪出其狀態圖及狀態表, 請使用 Verilog HDL 描寫出並於 QuatusⅡ 模擬訊號波型加以驗證結果 請設計出一 Moore machine, 輸入為 X, 輸出為 Z, 當檢測到 X 輸入之 的個數和為奇數, 並且 X 輸入之 的個數和為偶數時 ( 但不包括 ), Z 輸出為 ; 否則 Z 輸出為 繪出其狀態圖及狀態表, 請使用 Verilog HDL 描寫出並於 QuatusⅡ 模擬訊號波型加以驗證結果 使用 state machine 產生 lab problem 2 之波形 (clock 為輸入 )

117 Logic Design Lab 2: UP2 Education Kit Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 認識 UP2 Education Kit, 使用 Verilog 語言設計電路, 並應用 QuartusⅡ 軟體下載到 UP2 實驗板上驗證所設計的電路 2

118 Altera UP2 實驗版 上圖為 UP2 之實驗板, 此實驗板支援 JTAG Programming cable Mouse cable 及 VGA cable, 此處我們只需 JTAG Programming cable, 將其接至電腦, 而電源線接至電源供應 3 平面配置圖 4 2

119 JTAG Jumper 5 QuartusⅡ 軟體設定 先將所設計的電路依照原步驟經 QuartusⅡ 模擬波型驗證之後, 選擇 Assignments Device 再於 Family 處選擇 FLEXK 系列之晶片 6 3

120 QuatusⅡ 軟體設定 (Cont.) 接下來在底下的 Available devices 處選擇 EPFK7RC24-4 的晶片後, 點擊 OK 7 QuatusⅡ 軟體設定 (Cont.) 選擇完 Device 之後, 接下來我們開始設定 Pin 腳的位置, 選擇 Assignments Pins 在 Location 處點擊兩下便可以選擇所需之 Pin 腳, 其設定可參考下圖

121 7 段顯示器腳位 9 實驗接腳圖 5

122 QuatusⅡ 軟體設定 (Cont.) 設置完腳位之後, 再點擊圖示, 再做一次 compile, 之後在 Tools 之處選擇 Programmer, 準備 download 至 UP2 實驗板 點選 Hardware Setup 後點選 Add Hardware OK 2 6

123 之後在 Currently selected hardware 處選擇剛剛加入的 Hardware 接著在 Program/Configure 處選擇打勾 點選 Start 之後便 download 至實驗板中 3 實驗範例 此次的程式分成 4 個 module, 分別為 adder cla4 bin2bcd 及 seg7disp; 其中 adder 為 Top module,cla4 為一 4-bit carry look-ahead adder, 本實驗從 switch 輸入是 2 進制, 而在 LED 則輸出相加後 進制 bin2bcd 用來將 2 進位轉為 進位輸出, 其工作原理如圖 2.6 所示, 將二進位的 至 加 3, 下圖 2.7 為其轉換過程 x 2 換成 BCD 碼應為 x 2 即 (+)x2 4 7

124 5 7 段顯示器 6 8

125 程式碼 //Top module module adder(a_in, B_in, reset, ones_out, tens_out); input [3:] A_in, B_in; input reset; output [7:] ones_out, tens_out; wire [7:] ONES,TENS; wire [3:] sum; wire carryout; cla4 c(sum, carryout, A_in,B_in, 'b); bin2bcd c2(sum, carryout, ONES, TENS); seg7disp c3(reset, ONES, ones_out); seg7disp c4(reset, TENS, tens_out); endmodule //4-bit carry look-ahead adder module cla4(s,cout,i,i2,c); output [3:] s; //summation output cout; //carryout input [3:] i; //input input [3:] i2; //input2 input c; // 前一級進位 wire [3:] s; wire cout; wire [3:] g; wire [3:] p; wire [3:] c; assign g[3:]=i[3:] & i2[3:]; //carry generation assign p[3:]=i[3:] ^ i2[3:]; //carry propagation assign c[]=g[] (p[] & c); //calculate each stage carryout assign c[2]=g[] (g[] & p[]) (p[] & p[] & c); assign c[3]=g[2] (g[] & p[2]) (g[] & p[] & p[2]) (p[] & p[] & p[2] & c); assign cout=g[3] (g[2] & p[3]) (g[] & p[2] & p[3]) (g[] & p[] & p[2] & p[3]) (p[] & p[] & p[2] & p[3] & c); assign s[]=p[]^c; //calculate summation assign s[3:]=p[3:]^c[3:]; endmodule 7 程式碼 (Cont.) //Binary to BCD // 本題結果最多 5 binary bits module bin2bcd(a,carryin,ones,tens); input [3:] A; input carryin; output [7:] ONES, TENS; wire [3:] c,c2; wire [3:] d,d2; assign d = {'b,carryin,a[3:2]}; assign d2 = {c[2:],a[]}; add3 m(d,c); add3 m2(d2,c2); assign ONES = {4'b,c2[2:],A[]}; assign TENS = {6'b,c[3],c2[3]}; endmodule module add3(in,out); input [3:] in; output [3:] out; reg [3:] out; (in) case (in) 4'b: out <= 4'b; 4'b: out <= 4'b; 4'b: out <= 4'b; 4'b: out <= 4'b; 4'b: out <= 4'b; 4'b: out <= 4'b; 4'b: out <= 4'b; 4'b: out <= 4'b; 4'b: out <= 4'b; 4'b: out <= 4'b; default: out <= 4'b; endcase endmodule 8 9

126 程式碼 (Cont.) Module seg7disp(rst, datain, segledout); input rst; input [7:] datain; output [7:] segledout; reg [7:] segledout; or datain) if(~rst) segledout = ~8'h3f; else begin case(datain) 8'h: segledout = ~8'h3f; 8'h: segledout = ~8'h6; 8'h2: segledout = ~8'h5b; 8'h3: segledout = ~8'h4f; 8'h4: segledout = ~8'h66; 8'h5: segledout = ~8'h6d; 8'h6: segledout = ~8'h7d; 8'h7: segledout = ~8'h7; 8'h8: segledout = ~8'h7f; 8'h9: segledout = ~8'h6f; default: segledout = 8'h3f; endcase end endmodule 9 顯示結果 2

127 問題與討論 利用 Textbook Fig. 4-4 BCD adder, 重新設計此一電路 2

128 Logic Design Lab 3: Traffic Light Controller Instructor: Kuan Jen Lin ( 林寬仁 ) kjlin@mails.fju.edu.tw Web: Room: SF 727B 實驗目的 使用 Verilog 硬體描述語言設計一個紅綠燈控制電路, 並應用 QuatusⅡ 軟體下載到 UP2 實驗板上驗證所設計的電路 2

129 紅綠燈切換順序 每單位一秒 需要幾個狀態? 8? 4? 3 Design a counter generating Hz clock 4 2

130 LAB 9 Behavioral Description of Frequency Divider (mod 2) module f_div (RST, CLK, f_out); input RST, CLK; output f_out; reg f_out; reg [3:]q; parameter count = 2; CLK) if (RST = = 'b) begin f_out = ; q = count; end else if (q = = ) begin f_out = ; q = count; end else begin q = q - ; f_out = ; end endmodule 5 : 綠燈 2: 黃燈 : 紅燈 6 3

131 接腳說明 clock 之設置腳位為 9; input switch 設置於 FLEX DIP Switch Input, 用於選擇手動或自動之模式 ; 輸出之訊號 A 及 B 之綠 黃 紅燈, 選擇於 MSD 及 LSD Display Segment 七段顯示器上顯示其結果 (optional) 手動模式時的輸入控制訊號 chn 可設置於 Push Button, 當手動模式時控制狀態之變換 ; 7 問題與討論 使用 HDL 完成紅綠燈控制設計, 依固定時間量自動轉換燈號 當 switch = 時燈號轉換順序如講義 當 switch = 時燈號轉換順序如講義, 但南北向綠燈加長為 6 秒 使用 HDL 完成紅綠燈控制設計, 轉換燈號係由手動控制 當 switch 為 時, 燈號轉換順序如上, 但由 chn 之訊號控制, 只有當 chn 控制訊號被觸發時 Traffic Light 轉換至下一燈號組合 8 4

132 (Lab 3-prob ) 假設 A 街道及 B 街道十字交叉路口,AB 街道分別設有紅 黃 綠三種燈 另設有一時間調控開關 SW 當 SW on 時, 其燈號顯示依下列順序循環操作 : A 綠燈亮, B 紅燈亮, 時間 3s A 黃燈亮, B 紅燈亮, 時間 s A 紅燈亮, B 綠燈亮, 時間 3s A 紅燈亮, B 黃燈亮, 時間 s 當 SW off 時,A 綠燈亮與 B 紅燈亮之時間會增長為 6s 完成紅綠燈控制電路, 下載至 UP2, 並用七段 LED 顯示器, 以 表示綠燈, 以 2 表示黃燈, 以 表示紅燈 9 (Lab 7-prob 2) 利用兩個 4-bit CLA, 設計一個 8-bit Adder-subtractor, 其中負數是用 2 s 補數表示 此電路有一輸入訊號 M, 當 M= 時, 執行減法, M= 時, 執行加法 ( 電路不需含 overflow 偵測 ) 5