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野庸江
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1 .,,.,!, ( ), :

2 r=0, g=0, ( ). Ok,,,,,.,,. (stackup) stackup, 8 (4 power/ground 4,sggssggs, L1, L2 L8) L1,L4,L5,L8

3 , Oz Oz Oz( )=28.3 g( ), 1Oz, (DK) Cx Co = Cx/Co = - Prepreg/Core pp,,core pp,, pp.,, :,, 1, 2, 8, top bottom,, : 55 60Ohm, 70~110Ohm, 1~2mm,. 1.6mm, 63mil, 60Ohm, 100Ohm,

4 , top bottom, top, polar si6000, : : 1, W( ) 2,,, 3, coated microstrip, surface microstrip, surface microstrip, 4,w1 w2 pcb, ( ) 5, 60Ohm,, 1,2ohm 6,h/t L5

5 stripline symmetrical stripline, symmetrical stripline offset stripline H1=H2,, :

6 1, DDR2 clock 85Ohm~ Ohm, ( ) (,,, via ) (, ) a. (microstrip) Z={87/[sqrt(Er+1.41)]}ln[5.98H/(0.8W+T)] W T H Er PCB (dielectric constant) 0.1<(W/H)<2.0 1<(Er)<15 b. (stripline) Z=[60/sqrt(Er)]ln{4H/[0.67 (0.8W+T)]} H W/H<0.35 T/H<0.25 The Differential Impedance Calculator is provided free to registered users. Please Register here Instructions: 1. Select the number of substrate layers required. 2. You will then be presented with a table representing the suggested stack-up for that type of substrate. 3. Modify the variables to examine the effects on the trace Characteristic and Differential Impedance. Number of physical board layers

7 Important: The trace separation should not be adjusted to alter the Differential Impedance - trace separation should always be kept to the minimum clearance specified by the PCB vendor. Note: 1. All dimensions are in MIL (thousands of an inch). 2. The Dielectric Constant of FR4 material may vary by as much as 20% (4.2 to 5.2). 3. The overall Dielectric Thickness (Cu to Cu) should total 62 MIL nominally. 4. Variables unavailable for modification have no significant effect on the impedance of the traces. 5. The default multilayer board stack-ups are taken from Advance Design for SMT, Barry Olney/AMC. 6. The Impedance Calculator uses formulae derived from: IPC-D Design Standard for Electronic Packaging Utilizing High Speed Techniques. EMC & the Printed Circuit Board - Montrose. 7. Only Edge Coupled Differential Pairs are considered. No allowance has been made for Broad Side Coupling from adjacent layers. It is good practice to route adjacent layers orthogonal to each other in order to reduce any coupling that may occur. 8. To reduce EMI, high frequency, fast rise time signals should be routed between the reference planes. All care has been taken to ensure that the results are correct but no responsibility is taken for any errors. If you prefer to do the calculations yourself - please use the formulae below. Microstrip Differential Unbalanced Stripline Impedance (for traces routed on an outer layer) Differential Impedance (for traces embedded between planes) Zo = [87/Sqrt(Er+1.41)]* Zo = [80/Sqrt Er]*

8 ln(5.98h/(0.8w+t)) Zdiff = 2*Zo ( e -0.96D/H ) ln(1.9(2h+t)/(0.8w+t)) * (1 - (H / 4(H + C + T))) Zdiff = 2*Zo ( e -2.9D/B ) where W = trace width T = trace thickness H = distance to nearest reference plane Er = dielectric constant D = trace edge to edge spacing C = signal layer separation B = reference plane separation Material Dielectric Constant FR4 Fiberglass Epoxy 4.7 Teflon 2.2 Teflon Glass 2.5 Polyimide 3.5 Polyimide Glass 4.2 Relative Dielectric Constants of substrate materials PCB 1,,,,,, EMI PCB PCB

9 2 Zo (signal layer) (reference plane) 2.1 (1), PCB, square wave signal, pulse (2), Zdiff (3) Zoo (4), Zcom (5) Zoe, 2.2 W----- / H---- T H1--- Er----- DK, Undercut----W1-W undercut, 3 Polar Si8000 Field Solver Si8000 Polar Er PCB 4 5

10 InPlan InPlan Si8000 InPlan PP InPlan Rule Undercut InPlan Rule InPlan 4, ( ), PCB :MI CAM MI Script, 10 InCoupon Genesis InCoupon Coupon CAM Coupon Coupon Coupon Coupon 5 PCB InPlan InCoupon PCB Layout InPlan PCB

11 T=2.1 T=1.4 ZY

Microsoft Word - PZ series.doc

Microsoft Word - PZ series.doc 叠层片式铁氧体磁珠 P 系列 Multilayer Chip Ferrite Bead P Series Operating Temp. : -4 ~ +8 特征 FEATUES 内部印有银电极的叠层结构, 铁氧体屏蔽无串扰 Internal silver printed layers and magnetic shielded structures