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1 Verilog 1

2 錄料 7. 邏 8. 料流 9. 行 10. 令 11. 邏路例 2

3 1. Verilog 路 (Flexibility) 易更更易連林數 (Portability) 不不易 C 3

4 2. Verilog Verilog (model) (switch level) (transistor) 邏 (gate level) 料流 (data flow) (register transfer level) 行 (behavioral) 4

5 2.1 邏路邏連 // 2-input AND gate module and2(in1, in2, out); input in1, in2; output out; endmodule and u1(out, in1, in2); 5

6 2.2 料流路說料路 // 2-input AND gate module and2(in1, in2, out); input in1, in2; output out; endmodule assign out = in1 & in2; 6

7 2.3 行 Verilog HDL 路不 // 2-input AND gate module and2(in1, in2, out); input in1, in2; output out; reg out; or in2) begin out = in1 & in2; end endmodule 7

8 3. Verilog Verilog (module) 路了數路路 (assign) 路行數 (functions) (task) 8

9 3.1 // include & define module module_name(port list); Port // input, output, inout 數料 // wire, reg, 邏料流 function task 行 endmodule 9

10 3.2 路 C 數 Verilog 不 Verilog 識 10

11 3.3 Verilog Verilog (token) (whitespace) (comment) (keyword) 識 (identifier) (operator) 數 (number) 11

12 3.3 Verilog Verilog 行 // 行 (end_of_line) 行 /* */ 12

13 3.3 Verilog 來見 always negedge posedge begin end assign wire integer function endfunction module endmodule for if else inout input output and buf nand nor not or xnor xor 13

14 3.3 Verilog Verilog 路識數數例 (instance) 識數 ( _ ) ($) 識度識 14

15 3.3 Verilog Binary bit-wise operators: ~, &,, ^, ~^, ^~ Unary reduction operators: &, ~&,, ~, ^, ~^, ^~ Logical operators:!, &&, 2 s complement operators: +, -, *, /, % Relational operators: >, <, >=, <=, ==,!=, ===,!== Logical shift operators: >>, << Conditional operators:? : Duplication operators: {n{ <exp> <,<exp>> *}} Concatenation operators: {} 15

16 3.3 Verilog 數度數 <size> <base><number> <size> bit 數 <base> B O D H 例 1 B0, 4 O7, 8 HF, 10 D9 不度數不 <size> 來 bit 數 HDL 例 h89ab, 128, O377, b

17 4. MAX+plus II MAX+plus II Verilog 路利立 Verilog v Verilog 路立行立 scf 路 17

18 4. MAX+plus II MAX+plus II Verilog module Module 不 task IEEE 料邏 MAX+plus II Verilog 利 on-line help 來了 18

19 5. 料 Verilog 料 wire wand Wired-AND MAX+plus II 不 wor Wired-OR MAX+plus II 不 reg 路 integer, real, MAX+plus II integer for 19

20 5.1 數 Verilog 數 (value level) 0 邏 0, Zero, False, Low, Logic Low, Ground, V SS, Negative Assertion 1 邏 1, One, True, High, Logic High, Power, V DD, V CC, Positive Assertion X Unknown value Z High impedance, Floating state, Tri-state, Disable driver 20

21 5.2 wire 料 wire 數連連數量 wire 數 Z wire a, b, c; assign c = a & b; 21

22 5.3 reg 料 reg 數數類數量 reg 數 X reg a, b, c; always@( ) c = a & b; 22

23 5.4 wire reg wire 數 assign 來不 always (l-value) reg 數 always 23

24 5.5 量量 (vector) wire reg 量量 wire [0:3] in; wire [0:3] out; wire [3:0] a, b; reg [0:3] c; reg [3:0] d, e; 24

25 5.6 列列列 wire reg integer 量列 1 列 wire in[0:100]; reg out[0:100]; MAX+plus II 25

26 5.7 量數量數連 wire [7:0] a, b, c; assign c[0] = a[0] & b[0]; wire [7:0] a, b, c; assign c[3:0] = a[5:2] & b[7:4]; assign c[0:3] = a[3:0]; // X 26

27 6. Verilog (input) (output) (inout) 27

28 6.1 module and_2_1(in1, in2, out); input in1, in2; output out; assign out = in1 & in2; endmodule 28

29 6.2 module bidir(rw, din, da, iop); input rw, din, da; inout iop; assign iop = rw? ((din)? da : iop) : 1'bZ; endmodule * MAX+plus II 路 rw din da iop 29

30 6.3 Verilog 料 wire 若來料 reg 行連連兩 30

31 7. 邏路邏連 Verilog 邏邏 and, nand, or, nor, xor, xnor MAX+plus II 12 不 xor xnor 邏 buf, not 邏 bufif0, bufif1, notif0, notif1 31

32 7.1 邏例 -1 module test(in, out); input [2:0] in; output out; and u1(out, in[0], in[1], in[2]); endmodule 32

33 7.1 邏例 -2 module test(in, out); input [2:0] in; output out; nor u1(out, in[0], in[1], in[2]); endmodule 33

34 7.2 邏例 -1 module test(in, out); input in; output [1:0] out; not u1(out[0], out[1], in); endmodule 34

35 7.2 邏例 -2 module test(in, out); input in; output [1:0] out; buf u1(out[0], out[1], in); endmodule 35

36 7.3 邏例 -1 module test(in, out, en); input in, en; output out; bufif1 u1(out, in, en); endmodule 36

37 7.3 邏例 -2 module test(in, out, en); input in, en; output out; notif0 u1(out, in, en); endmodule 37

38 8. 料流路說料路 assign wire wand wor tri 邏路路 assign a = b + a; 38

39 8.1 邏路例 X = A C D + B C + B D + C D Y = A + B + C module boolean(a, b, c, d, x, y); input a, b, c, d; output x, y; assign x = (a & c & (!d)) (b & (!c)) (b & d) (c & d); assign y = (!a) b c; endmodule 39

40 8.2 路 Binary bit-wise operators ~ NOT & AND OR ^ XOR ~^, ^~ XNOR module test(in1, in2, out); input in1, in2; output [0:4] out; assign out[0] = ~in1; assign out[1] = in1 & in2; assign out[2] = in1 in2; assign out[3] = in1 ^ in2; assign out[4] = in1 ~^ in2; endmodule 40

41 8.2 路 Unary reduction operators & AND ~& NAND OR ~ NOR ^ XOR ~^, ^~ XNOR module test(in, out); input [0:3] in; output [0:5] out; assign out[0] = &in; assign out[1] = ~&in; assign out[2] = in; assign out[3] = ~ in; assign out[4] = ^ in; assign out[5] = ~^ in; endmodule 41

42 8.2 路 Logical operators! NOT && AND OR module test(in1, in2, out); input in1, in2; output [0:2] out; assign out[0] =! in1; assign out[1] = in1 && in2; assign out[2] = in1 in2; endmodule 42

43 8.2 路 2's complement arithmetic + Add - Subtract * Multiply / Divide % Module module test(i1, i2, o1, o2, o3); input i1, i2; output [0:1] o1, o2, o3; assign o1 = i1 + i2; assign o2 = i1 - i2; assign o3 = i1 * i2; endmodule 43

44 8.2 路 Relational operators > < >= <= ==!= module test(a, b, lt, eq, le); input [0:3] a, b; output lt, eq, le; assign lt = (a > b); assign eq = (a == b); assign le = (a < b); endmodule 44

45 8.2 路 Logical shift operators >> << module test(in, out1, out2); input [0:3] in; output [0:3] out1, out2; assign out1 = in << 1; assign out2 = in >> 1; endmodule * MAX+plus II 數量 45

46 8.2 路 Conditional operator?: module test(a, b, sel, out); input a, b, sel; output out; assign out = sel? a : b; endmodule 46

47 8.2 路 Duplication operator {{}} Concatenation operator {} module test(in, out1, out2); input [0:7] in; output [0:7] out1, out2; assign out1 = {2{4'b1100}} + in; assign out2 = {{3{2'b10}}, 2'b00} + in; endmodule 47

48 9. 行路不 Verilog (event-based timing control) 路 48

49 9.1 always always 念行理 always statement statement always begin statements end begin statements end 49

50 9.1 ) (event expression) (level trigger) 利 or 連不 (level trigger) posedge negedge 50

51 9.1 例 module test(in, out); input in; output out; reg out; out = ~ in; endmodule 51

52 9.1 例 module test(a, b, out); input a, b; output out; reg out; or b) begin out = a b; end endmodule 52

53 9.1 posedge module test(a, ck, out); input a, ck; output out; reg out; ck) begin out = ~ a; end endmodule 53

54 9.1 negedge module test(a, ck, out); input a, ck; output out; reg out; ck) begin out = ~ a; end endmodule 54

55 9.2 if 來行行理 if 理兩 if (expression) statement if (expression) begin statements end 55

56 9.2 if module test(reset, in, out); input reset, in; output out; reg out; always begin if (reset == 1 b1) // out = 0; if (reset == 1 b0) // out = in; end endmodule 56

57 9.2 if module test(reset, in, out); input reset, in; output out; reg out; always begin if (reset) // out = 0; if (! reset) // out = in; end endmodule 57

58 9.3 if-else if (expression) statement else statement if (expression) begin statements end else begin statements end 58

59 9.3 if-else 例 (priority encoder) Y, Z) begin if (Z) // highest out = result4; else if (Y) out = result3; else if (X) out = result2; else out = result1; // lowest end 59

60 9.4 case case 路路了 full case case (expression) alter_1, alter_2: stm_1; alter_3: stm_2; default: default_stm; endcase 60

61 9.4 case 例 2X1 Multiplexor module mux21(in1, in2, sl, out); input in1, in2, sl; output out; reg out; or in2 or sl) begin case (sl) 1 b0: out = in1; 1 b1: out = in2; endcase end endmodule 61

62 9.4 case 例 Priority encoder X Y Z 2 b11 out module test(x, Y, Z, out); input [0:1] X, Y, Z; output [0:2] out; reg [0:2] out; always@(x or Y or Z) begin case (2'b11) X: out = 3'b001; Y: out = 3'b010; Z: out = 3'b100; default: out = 3'b000; endcase end endmodule 62

63 9.4 casex casez Verilog casex casez 兩 case casex alter (?) experssion 不 Z X casez alter (?) experssion Z MAX+plus II 不 casex casez 63

64 for Verilog for while repeat forever MAX+plus II for for (statement; expression; statement) begin statements; end always 行 64

65 for module forloop(a, b, out); input [0:7] a, b; output [0:7] out; reg [0:7] out; integer i; or b) begin for (i = 0;i <= 7; i = i + 1) out[i] = a[i] b[i]; end endmodule 65

66 9.6 function Verilog function C 利 function 數 function 數數 function <range> name; input 參數 ; 數 endfunction 66

67 module fun_as(a, b, Add, Sub, Inc, c); input [0:3] a, b; 9.6 function input Add, Sub, Inc; output [0:3] c; reg [0:3] c; or b or Add or Sub or Inc) begin if (Add) c = a + b; else c = ff(a, b, Sub, Inc); end function [0:3] ff; input [0:3] a, b; input Sub, Inc; begin if (Sub) ff = a b; else if (Inc) ff = a + 1; else ff = a 1 b1; end endfunction endmodule * MAX+plus II function 67

68 9.7 parameter parameter 數來度量 parameter name = number; 68

69 9.7 parameter module add8(a, b, c); parameter width=8; input [1:width] a, b; output [1:width] c; assign c = a + b; endmodule 69

70 10. 令 C 令 (compiler directives) Verilog 了令利便行見令 `include `define 70

71 10.1 `include `include Verilog module fa1(a, b, ci, s, co); input a, b, ci; output s, co; assign {co, s} = a + b + ci; endmodule `include fa1.v module fa2(a, b, ci, s, co); input [1:0] a, b; input ci; output [1:0] s; output co; wire c1; fa1 ffa0(a[0],b[0],ci,s[0],c1); fa1 ffa1(a[1],b[1],c1,s[1],co); endmodule 71

72 10.2 net/register net 1. wire 2. wor 3. wand net input net/register output net inout net net 72

73 10.2 Verilog 來連 In-Order 來連 By-name 73

74 10.2 來連 module or_2(a, b, c); input a, b; output c; assign c = a b; endmodule `include "or_2.v" module or_8(a, b, c); input [3:0] a, b; output [3:0] c; or_2 o1(a[0], b[0], c[0]); or_2 o2(a[1], b[1], c[1]); or_2 o3(a[2], b[2], c[2]); or_2 o4(a[3], b[3], c[3]); endmodule 74

75 10.2 來連 `include "or_2.v" module or_8(a, b, c); input [3:0] a, b; output [3:0] c; or_2 o1(.a(a[0]),.b(b[0]),.c(c[0])); or_2 o2(.c(c[1]),.b(b[1]),.a(a[1])); or_2 o3(a[2], b[2], c[2]); or_2 o4(a[3], b[3], c[3]); endmodule 75

76 10.3 `define `define 來數 `define SI 4 module buf4(in, out, clock); input [0:`SI-1] in; input clock; output [0:`SI-1] out; reg [0:`SI-1] out; integer i; always@(posedge clock) begin for (i=0; i<`si; i=i+1) out[i] = in[i]; end endmodule 76

77 10.4 defparam parameter 數 defparam instance_name.id1 = number1; 77

78 10.4 defparam module or8(a, b, c); parameter width=8; input [1:width] a, b; output [1:width] c; assign c = a b; endmodule MAX+plus II defparam 來 parameter `include or8.v module or4(a, b, c); parameter size = 4; input [1:size] a, b; output [1:size] c; or8o4(a, b, c); defparam o4.width=4; endmodule 78

79 11. 邏路例邏路 (memory) (latch) (flip-flop) (register) 數 (counter) 數 (synchronous counter) 漣數 (ripple counter) 狀 (finite state machine) 79

80 output enable D-type latch module latch_d(enable, D, Q); input Enable, D; output Q; reg Q; or D) if (Enable) Q = D; endmodule D Q Enable 80

81 D-type flip/flop module D_FF_SR(clock, reset, D, Q); input clock, reset, D; output Q; reg Q; clock) begin if (reset == 1 b1) Q = 1 b0; // reset end endmodule else Q = D; D Q Reset Clock 81

82 clear 16 module reg_16(clear, clock, in, out); input clear, clock; input [0:15] in; output [0:15] out; reg [0:15] out; clock) begin if (clear == 1 b1) out = 16 b0; else out = in; end endmodule in out clear clock 82

83 11.2 數 -- 數 reset enable 4 數 module counter1(reset, enable, clk, out); input reset, enable, clk; output [0:3] out; reg [0:3] out; always@(posedge clk) begin if (reset) out = 0; else if (enable) out = out + 1; end endmodule Reset Enable Clk 4 83 out

84 11.2 數 -- 數數數 module counter1(direct, clk, out); input direct, clk; output [0:3] out; reg [0:3] out; integer value; clk) begin if (direct) value = 1; else value = -1; out = out + value; end endmodule direct Clk 4 84 out

85 11.3 狀狀路路路狀狀 Moore machine 狀 Mealy machine 狀 85

86 11.3 狀 Moore machine initial 1 S1 Y = 0 0 S0 Y = S2 Y = 1 狀 S0 S1 S2 狀 0 1 S2 S1 S0 S2 S1 S0 Y

87 11.3 狀 module moore(reset, clk, x, y); input reset, clk, x; output y; reg y; parameter s0=2 b00, s1=2 b01, s2=2 b10; reg [0:1] ps, ns; or ps) begin if (reset) begin ns = s0; y = 0; end else begin case(ps) s0: begin if (x == 0) ns = s2; else ns = s1; y = 0; end s1: begin if (x == 0) ns = s0; else ns = s2; y = 0; end endcase end end // else & always always@(posedge clk) ps = ns; endmodule 87

88 11.3 狀 Mealy machine initial 1/0 S1 S0 0/0 1/1 1/0 0/1 0/0 S2 狀 S0 S1 S2 狀 X=0 X=1 S2 S1 S0 S2 S1 S0 X=0 X=

89 11.3 狀 module mealy(reset, clk, x, y); input reset, clk, x; output y; reg y; parameter s0=2 b00, s1=2 b01, s2=2 b10; reg [0:1] ps, ns; or ps) begin if (reset) begin ns = s0; y = 0; end else begin case(ps) s0: begin if (x == 0) ns = s2; else ns = s1; if (x == 0) y = 0; else y = 0; end endcase end end // else & always always@(posedge clk) ps = ns; endmodule 89

90 LAB 90

91 LAB 1 verilog (Full Adder) 說 - in1 1 in2 2 carryin - sum carryout 林 sum=in1 in2 carryin Carryout=in1 in2+in1 carryin+in2 carryin * 度 Bioelectromagnetics 1 Lab 91

92 說 sum carryout (delay) 92

93 LAB 2 S1 S2 Y[3..0] S0 S Y[3..0]

94 LAB 3 利 hw1 a[3..0] b[3..0] carryin sum[3..0] carryout a b carryin fulladd4 sum carryout a[0] b[0] a[1] b[1] a[2] b[2] a[3] b[3] carryin c1 c2 c3 carryout _0 _1 _2 _3 sum[0] sum[1] sum[2] sum[3] 94

95 Thanks for your attention. 95

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untitled Verilog HDL Verilog HDL 邏令列邏路例練數度 (top-down design) 行 (concurrency) 2.1 Verilog HDL (module) 邏 HDL 理 HDL 邏料數邏邏路 module module_name (port_list) // 列 //