2. initial always initial always 0 always initial always fork module initial always 2 module clk_gen_demo(clock1,clock2); output clock1,clock2; reg cl

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婴垣贺
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1 Verilog HDL Verilog VerilogHDL 1. Module 1 2 (

2 2. initial always initial always 0 always initial always fork module initial always 2 module clk_gen_demo(clock1,clock2); output clock1,clock2; reg clock1,clock2; initial clock1=0; clock2=1; always #50 clock1=~clock1; always #100 clock2=~clock2; fork

3 1. #10 reg_a=reg_b; #10 reg_c=reg_a; reg_a=reg_b; reg_c=reg_a; // 2. fork- Netlist

4 #10 reg_a=reg_b; #10 reg_c=reg_a; fork #10 reg_a=reg_b; #10 reg_c=reg_a; module wave_gen_para(wav); output wav; reg wav; event _wave; initial fork wave=0; #50 wave=1; #100 wave=1; #150 wave=1; #200 wave=1; #250 ->_wave; : : fork 3. disable

5 1. reg=8 b1011_1100; reg_a[3]=1 b0; reg_a[7:4]=4 b1010; mem_a[3]=8 h5d; {carry,sum}=reg_a+reg_b;// 2. 1 < > < >=< > reg_a=reg_b; clock) clock) 1 or 2 or reset or posedge clear) reg_out=0;

6 1 < >= < > < > 1. reg_a= 10 reg_b; ) reg_b; fork #10 reg_a=reg_b; #10 reg_b=reg_a; fork reg_a= #10 reg_b; reg_b= #10 reg_a; 3. module wave_gen_para(wav); output wav; reg wav; event _wave; initial wave<=0; <= #50 wave<=1; #100 wave<=1; < #150 wave<=1; #200 wave<=1; #250 ->_wave;

7 module demo_seri_block(reg_a,reg_b,data,clock); input data,clock; output reg_a,reg_b; clock) reg_a=data; reg_b=reg_a; data clock reg_b reg_a module demo_seri_block(reg_a,reg_b,data,clock); input data,clock; output reg_a,reg_b; clock) fork reg_a=data; reg_b=reg_a; data clock reg_b reg_a module demo_seri_block(reg_a,reg_b,data,clock); input data,clock; output reg_a,reg_b; clock) reg_a<=data; reg_b<=reg_a; data clock reg_b reg_a 4. assign assign

8 module demo_and_assign(c,a,b) input a,b; output c; assign c=a&b; module demo_and_assign(c,a,b) input a,b; output c; reg c always@(a,b) c=a&b; 5. assign/deassign deassign,force/release assign/deassign deassign assign deassign force/release module dff_asyn(q,d,clear,clk); output q; input d,clear,clk; reg q; always@(clear) if(!clear) assignq=0; dessign q; always@(posedge clk) q=d; assign/deassign assign/deassign

9 1. if C 1 if 1 0 x z if if always@(enable or dada) case forever repeat while for if(enbale) out=data; 2 if( if( always@(enable or dada_a or data_b) if(enbale) out=data_a; out=data_b; MUX 2 if( if( 1 1 if( 2 2 if ( ( n n n+1 if

10 if( 1) if( 2) a=a+b; a=a+c; if( 1) if( 2) a=a+b; a=a+c; D module dff_sync(q,d,clear,clk); output q; input d,clear,clk; r4eg q; always@(posedge clk) if(!clear) q=0; q=d; D module dff_async(q,d,clear,clk); output q; input d,clear,clk; r4eg q; always@(clear or posedge clk) if(!clear) q=0; q=d; 2.case case casez casex

11 1 case module demo_case(sig); case( input sig; n n default n+1 case always@(sig) case(sig) 1 b1: 1 b0: 1 bx: 1 bz: $display( signal value is 1 ); $display( signal value is 0 ); $display( signal is unknown ); $display( signal is high impedence ); case 2)casez casez casex casez casex casez(r[3:0]) 4 b011z: 1 4 b01xz: 2

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