ebook122-3

Size: px

Start display at page:

Download "ebook122-3"

溜湛
5 years ago
Views:

1 3 Verilog Verilog HDL Ve r i l o g 3.1 Verilog HDL ( i d e n t i f i e r ) $ ( C o u n t COUNT _ R 1 _ D 2 R 56 _ 68 F I V E $ / / C o u n t (escaped identifier ) \ ( ) \ 7400 \.*.$ \{******} \ ~Q \O u t G a t e O u t G a t e \ O u t G a t e O u t G a t e Verilog HDL A a l w a y s ( ) A LWAY S( ) \initial i n i t i a l 3.2 Verilog HDL /* */ // 3.3 Verilog HDL Verilog

2 3 Verilog 15 initial begint o p = 3 b001; #2 T o p = 3 b011; e n d i n i t i a l begin T o p = 3 b001; #2 T o p = 3 b 011 ; e n d 3.4 $ 0 0 $d i s p l a y ("Hi, you have reached LT today"); /* $d i s p l a y */ $t i m e // ` Verilog `define, `undef `ifdef, `else, `endif `default_nettype `include `resetall `timescale `unconnected_drive, `nounconnected_drive `celldefine, `endcelldefine `define `undef ` d e f i n e C #define ` d e f i n e M A X _ B U S _ S I Z E 32 r e g [ `M A X _ B U S _ S I Z E - 10 ] A d d R e g; ` d e f i n e ` d e f i n e M A X B U S S I Z E `undef ` d e f i n e W O R D 16 // w i r e [ `W O R D 1] Bus;

3 16 Verilog HDL ` u n d e f W O R D // ` u n d e f, W O R D `ifdef `else `endif ` i f d e f W I N D O W S p a r a m e t e r WORD_SIZE = 16 ` e l s e p a r a m e t e r W O R D _ S I Z E = 32 ` e n d i f W I N D O W S ` e l s e `ifdef `default_nettype `default_nettype wand `include ` i n c l u d e, ` i n c l u d e.. /.. /primitives.v../../ p r i m i t i v e s. v `resetall ` r e s e t a l l `timescale Verilog HDL ` t i m e s c a l e ` t i m e s c a l e ` t i m e s c a l e t i m e _ u n i t / t i m e _ p r e c i s i o n t i m e _ u n i t t i m e _ p re c i s i o n s m s u s n s p s f s ` t i m e s c a l e 1 n s / p s 1ns, 100 p s `timescale,

4 3 Verilog 17 ` t i m e s c a l e 1ns/ 100ps m o d u l e A n d F u n c (Z, A, B ); o u t p u t Z; i n p u t A, B; a n d # (5.22, 6.17 ) A l (Z, A, B); // e n d m o d u l e n s 1/10 ns 100 ps ns, ns ` t i m e s c a l e, ` t i m e s c a l e 1 0 n s / 1 n s ns, n s ` t i m e s c a l e ` t i m e s c a l e ` r e s e t a l l ` t i m e s c a l e ` t i m e s c a l e 1ns/ 100ps m o d u l e A n d F u n c (Z, A, B ); o u t p u t Z; i n p u t A, B; a n d # (5.22, 6.17 ) A l (Z, A, B) ; e n d m o d u l e ` t i m e s c a l e 10ns/ 1ns m o d u l e T B; r e g PutA, PutB; w i r e G e t O; i n i t i a l b e g i n P u ta = 0; P u t B = 0; #5.21 P u t B = 1; #10.4 P u t A = 1; #15 P u t B = 0; e n d A n d F u n c A F 1(GetO, PutA, PutB) ; e n d m o d u l e ` t i m e s c a l e ` t i m e s c a l e ns, ns; ns, ns, ns T B 100 ps T B 100 ps 52 ns 520*100 ps *100 ps *100 ps 100 A n d F u n c T B A d d F u n c T B ` t i m e s c a l e

5 18 Verilog HDL `unconnected_drive `nounconnected_drive ` u n c o n n e c t e d _ d r i v e p u l l 1 /* */ ` n o u n c o n n e c t e d _ d r i v e `unconnected_drive pull0 /* */ ` n o u n c o n n e c t e d _ d r i v e `celldefine `endcelldefine ` c e l l d e f i n e m o d u l e F D 1 S 3 A X (D, CK, Z) ; e n d m o d u l e ` e n d c e l l d e f i n e P L I 3.6 Verilog HDL 1) 0 0 2) 1 1 3) x 4) z z 0 0 z x z 0 x 1 z 0 X 1 Z Verilog HDL Verilog HDL 1) 2) 3) _ 3.6.1

6 3 Verilog 19 1) 2) [s i z e ] base value s i z e b a s e o O b B d D h H v a l u e b a s e x z a f 5'O37 4'D2 4'B1x_01 7'Hx 4'hZ 4'd-4 8'h 2 A 3'b001 (2+3)'b x( x), x x x x x x x 4 z( z), z z z z, ` b x z 4 x z 3 x z 1 x z 'o721 'haf x z x z 10'b10 10'bx0x1 0, x, x x x x x x x 0 x 1 3 ' b _ 'b011 5'H0FFF 5'H1F z z

7 20 Verilog HDL 1) // 1 2) 23_5.1e ; 3.6E e E ( ) 5 E Ve r i l o g , "INTERNAL ERROR" " R E A C H E D > H E R E " 8 A S C I I 8 A S C I INTERNAL ERROR 8 * 14 r e g [1 8*14] M e s s a g e; M e s s a g e = "INTERNAL ERROR" (\ ) \n \t \\ \ \" " \ Verilog HDL 1) net type Ve r i l o g z 2) register type a l w a y s i n i t i a l x 3.7.1

8 3 Verilog 21 wire tri wor trior wand triand trireg tri1 tri0 supply0 supply1 n e t _ k i n d [m s bl s b] net1, net2,, n e t N; n e t _ k i n d m s b l s b 1 w i r e Rdy, Start; //2 1 w a n d [20] A d d r; //A d d r 3 w o r R d e; a s s i g n R d e = B l t & W y l; a s s i g n Rde = K b l K i p; R d e R d (wor) 1. wire t r i ( t r i ) w i r e R e s e t; w i r e [32] Cla, Pla, Sla; t r i [ M S B 1 L S B +1] A r t; wire ( t r i ) 0 1 x z 0 0 x x 0 1 x 1 x 1 x x x x x z 0 1 x z a s s i g n C l a = P l a & S l a; a s s i g n Cla = P l a ^ S l a; C l a

9 22 Verilog HDL C l a C l a 01 x, 11 z C l a x 1 x ( 0 1 x, x z x) 2. wor t r i o r 1 1 ( t r i o r ) w o r [M S BL S B] A r t; t r i o r [M A X 1 M I N 1] Rdx, Sdx, Bdx; wor ( t r i o r ) 0 1 x z x x x 1 x x z 0 1 x z 3. wand t r i a n d ( w a n d ) 0 0 ( t r i a n d ) w a n d [-7 0] D b u s; t r i a n d Reset, Clk; wand ( t r i a n d ) 0 1 x z x 1 x 0 x x x z 0 1 x z 4. trireg ( t r i r e g ) z x t r i r e g [18] Dbus, Abus; 5. tri0 t r i 1 t r i 0 t r i 1 0 t r i 1 t r i 0 [ 33] G n d B u s; t r i 1 [ 0 5] OtBus, ItBus; t r i 0 t r i 1 tri0 (tri1) 0 1 x z 0 0 x x 0 1 x 1 x 1 x x x x x z 0 1 x 0 ( 1 )

10 3 Verilog supply0 s u p p l y 1 s u p p l y 0 0 s u p p l y 1 s u p p l y 0 Gnd, ClkGnd; s u p p l y 1 [20] Vcc; Verilog HDL 1 ` d e f a u l t _ n e t t y p e ` d e f a u l t _ n e t t y p e n e t _ k i n d `default_nettype wand s c a l a re d v e c t o re d v e c t o re d, wire vectored[31] G r b; // G r b[ 2 ] G r b [ 3 2 ] wor scalared [40] B e s t; // w o r [40] B e s t B e s t [ 2 ] B e s t [ 3 1 ] reg integer time real realtime 1. reg r e g r e re g r e g [ m s b l s b] reg1, reg2, r e g N; m s b l s b 1 r e g [30] S a t; //S a t 4 r e g C n t; r e g [132] Kisp, Pisp, Lisp; //1, r e g [14] C o m b;

11 24 Verilog HDL C o m b = 2; //C o m b C o m b = 5; 2. //C o m b r e g [ m s b 1 s b] m e m o r y 1 [ u p p e r 1 l o w e r 1], m e m o r y 2 [u p p e r 2 l o w e r 2], r e g [03 ] M y M e m [ 0 63 ] //M y M e m r e g B o g [ 1 5 ] //B o g 5 1 M y M e m B o g 2 p a r a m e t e r A D D R _ S I Z E = 16, W O R D _ S I Z E = 8; r e g [1 W O R D _ S I Z E] R a m P a r [ A D D R _ S I Z E 1 0], D a t a R e g; R a m P a r 16 8 D a t a R e g 8 r e g [15] D i g; //D i g 5 D i g = 5'b11011;, r e g B O g[15]; //B o g 5 1 B o g = 5'b11011; r e g [03] X r o m [ 1 4 ] X r o m[1] = 4'hA; X r o m[2] = 4'h8; X r o m[3] = 4'hF; X r o m[4] = 4'h2; 1) $re a d m e m b 2) $re a d m e m b r e g [14] RomB [71] ; $ r e a d m e m b ("ram.patt", RomB); R o m b r a m. p a t t

12 3 Verilog $ r e a d m e m b 7 R o m b $ r e a d m e m b $r e a d m e m b ("ram.patt", R o m B, 5, 3); R o m b[ 5 ],R o m b[ 4 ] R o m b[ 3 ] $r e a d m e m b ("rom.patt", R o m B, 6); // 6 1 $r e a d m e m b ( "rom.patt",r o m B, 6, 4); // Integer i n t e g e r integer1, integer2, intergern [m s b1 s b] ; m s b l s b 32 i n t e g e r A, B, C; // i n t e g e r Hist [36]; // 2 B B[ 6 ] B[ ] r e g r e g [310] B r e g; i n t e g e r B i n t; //B i n t[ 6 ] B i n t[ ] B r e g = B i n t; / B r e g[ 6 ] B r e g[ ] B i n t /

13 26 Verilog HDL i n t e g e r J; r e g [30] B c q; J = 6; B c q = J; //J 32 ' b // B c q 4 ' b 0110 B c q = 4'b0101. J = B c q; //J 32 ' b J = 6; B c q = J; //J 32 ' b //B c q 4 ' b time t i m e t i m e t i m e time_id1, time_id2,, t i m e _ i d N [ m s b1 s b] ; m s b l s b 64 t i m e E v e n t s [031]; // t i m e C u r r T i m e; 5. real r e a l t i m e //C u r r T i m e / / r e a l r e a l _ r e g 1, r e a l _ r e g 2,, r e a l _ r e g N; // r e a l t i m e r e a l t i m e _ r e g 1, r e a l t i m e _ r e g 2,, r e a l t i m e _ r e g N; r e a l t i m e r e a l r e a l Swing, Top; r e a l t i m e C u r r T i m e; r e a l 0 r e a l x z r e a l 0 r e a l R a m C n t; R a m C n t = 'b01x1z; R a m C n t ' b p a r a m e t e r p a r a m 1 = c o n s t _ e x p r 1, param2 = c o n s t _ e x p r 2,, p a r a m N = c o n s t _ e x p r N; p a r a m e t e r L I N E L E N G T H = 132, A L L _ X _ S = 16'bx; p a r a m e t e r B I T = 1, B Y T E = 8, P I = 3.14; p a r a m e t e r S T R O B E _ D E L A Y = ( B Y T E + B I T) / 2;

14 3 Verilog 27 p a r a m e t e r T Q _ F I L E = " /h o m e/b h a s k e r/t E S T/ a d d. t q " ; 9 1 C O u n T, 1_2 M a n y, \**1, R e a l?, \wait, Initial Verilog HDL 5 7'o44, 'Bx0, 5'bx110, 'ha0, 10'd2, 'hzf 6 Q p r r e g [18*2] Q p r; Q p r = "ME" ; 7 8 Verilog HDL 9 i n t e g e r [03] R i p p l e; 10 m e m A. d a t a

本书简要介绍了Verilog硬件描述语言的基础知识，包括语言的基本内容和基本结构，以及利用该语言在各种层次上对数字系统的建模方法

本书简要介绍了Verilog硬件描述语言的基础知识，包括语言的基本内容和基本结构，以及利用该语言在各种层次上对数字系统的建模方法 Verilog HDL 硬件描述语言原书名 A Verilog HDL Primer (second Edition) 原出版社 Star Gralaxy Publishing 作者 J.Bhasker 译者徐振林等丛书名电子工程丛书出版社机械工业出版社书号 7-111-07890-X 页码 171 出版日期 2000 年 7 月本书简要介绍了 Verilog 硬件描述语言的基础知识,