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1 國立交通大學理學院應用科技學程碩士論文整合型溝渠式功率接面場效電晶體與蕭特基阻障二極體 Power Trench Junction Field Effect Transistor Integrated with Schottky Barrier Diode 研究生 : 劉莒光指導教授 : 羅正忠教授龔正教授中華民國九十八年六月

2 整合型溝渠式功率接面場效電晶體與蕭特基阻障二極體 Power Trench Junction Field Effect Transistor Integrated with Schottky Barrier Diode 研究生 : 劉莒光指導教授 : 羅正忠龔正 Student:Chu-Kuang Liu Advisor:J. C. Lou Advisor:J. Gong 國立交通大學理學院應用科技學程碩士論文 A Thesis Submitted to Degree Program of Applied Science and Technology College of Science National Chiao Tung University in partial Fulfillment of the Requirements for the Degree of Master in Degree Program of Applied Science and Technology June 2009 Hsinchu, Taiwan, Republic of China 中華民國九十八年六月

3 整合型溝渠式功率接面場效電晶體與蕭特基阻障二極體學生 : 劉莒光指導教授 : 羅正忠龔正國立交通大學理學院應用科技學程摘要現今在電源供應之開關應用方面, 以功率式金氧半導體場效電晶體為主要產品為了追求更高的轉換效率與操作頻率, 採用同步壓降轉換器設計可以達到此要求然而, 對同步壓降轉換器之下橋開關元件而言, 仍然有一些缺點仍需要克服, 譬如物理限制的元件通道導通電阻以及來自於本身具有的 PN 二極體在遲滯期間的造成的高功率損失本篇研究首先提出一個新穎的元件結構, 以整合型的溝渠式接面場效電晶體與蕭特基二極體來改善上述之缺點本設計可提供另一個吸引人的方法來實現同步壓降轉換器之下橋開關元件從模擬的結果得知, 較大的接面場效電晶體間距與蕭特基二極體之主動區平台寬度會得到較高的通道截止電壓, 以及在不變動通道截止電下的條件下, 會得到較低的汲極與源極之間崩潰電壓另一方面, 較大的通道寬度會得到較小的通道導通電阻而蕭特基二極體的平台寬度與二極體的反向回復 -i-

4 特性無顯著相關性至於磊晶層方面, 低摻雜的磊晶層濃度會造成低的通道截止電壓 ; 磊晶層的電阻率與汲極與源極之間崩潰電壓成反比, 與通道導通電阻成正比此新穎之結構可做成超高主動區元件密度可具競爭的導通電阻期望的崩潰電壓極好的低反向漏電流以及低的順偏電位壓降從整體的特性比較中可得知, 對直流轉直流轉換器之應用, 本元件結構可做為好的元件開關取代方案 -i-

5 Power Trench Junction Field Effect Transistor Integrated with Schottky Barrier Diode Student:Chu-Kuang Liu Advisors:Dr. J. C. Lou Dr. J. Gong Degree Program of Applied Science and Technology National Chiao Tung University ABSTRACT Nowadays, Power MOSFETs are dominant products of switching converters in the application field of power supply. For high power conversion efficiency and high frequency operating consideration, adopting synchronous buck converter (SBC) design would meet this requirement. However, for the low-side switch device of SBC, there are still some drawback characteristics such as physical limit of on-state resistance of channel, high power loss during the dead time due to the inherent PN body diode etc. In this study, a novel structure of power trench junction field effect transistor (JFET) integrated with Schottky barrier diode (SBD) is the first time being proposed. This design provides a new alternative solution for the low side switch -ii-

6 of synchronous buck converter. From the simulation result, we find the larger pitch size of JFET and mesa width of SBD causing higher pinch-off voltage, lower breakdown voltage of drain to source if it was under the same pinch-off voltage. On the other hand, it would result in lower specific on-resistance due to the larger channel width. There is no significant correlation between different mesa widths of Schottky diode and reverse recovery characteristics of diode. The lighter epitaxial doping concentration would get the lower pinch-off voltage. The lower resistively of epitaxial layer is in inverse proportional to breakdown voltage, but is in proportional to on-state resistance of drain to source. This novel structure is achievable for ultra high cell density, competitive on-state resistance, desirable breakdown voltage, excellent low reverse leakage level and lower forward voltage drop. The overall characteristic comparison shows it is a good candidate for switch device of DC-DC convertor application.

7 Acknowledge 感謝清大電子所龔正教授這兩年的研究指導與交大電子所羅正忠教授的共同指導感謝交大電物所碩士在職專班班主任陳永富教授在碩士專題研究的建解, 受益匪淺感謝清大電子所雜訊實驗室的同學智閩阿祐如意文山克濤彦宏長鑫范姜祐霖建豪冠宇士豪麗珍阿鴻仲璘竫渝感謝漢磊科技與杰力科技的長官們, 於我在職唸書間的包容與體諒, 由衷感謝 Thanks for the friendships of those who I met in NTHU & NCTU. Without yours friendly welcome and company, my master degree program can not be memorable. Finally, thank my sister and her daughter & sons. -iii-

8 Table of Contents Abstract (In Chinese). Abstract (In English).. Acknowledge Table of Contents... Figure captions Table captions. i ii iii iv v vi Chapter 1 Introduction Markets and Application of Low Voltage Power Device Motivation Application Guideline... 4 Chapter 2 Review of Junction Field Effect Transistor and 9 Schottky Diode Introduction Vertical Channel Metal-Oxide-Semiconductor Transistors Basic MOSFET VMOS DMOS UMOS Junction Field Effect Transistor Lateral Channel Junction Field Effect Transistor Vertical Channel Junction Field Effect Transistor Trench Junction Field Effect Transistor Schottky Diode Conventional Schottky Diode Junction Barrier Schottky Diode Trench MOS Schottky Diode iv-

9 2.5 Conclusion. 17 Chapter 3 Fabrication of Power Trench -iv- JFET Integrated with SBD Device Structure Process Flow 25 Chapter 4 Simulation of Power Trench JFET Integrated with SBD Introduction Two Dimension Simulation Two-Dimension Process Simulation Two-Dimension Electric Characteristic Simulation Two-Dimension Area Factor (α) Breakdown Voltage of Drain to Source (BV DSX ) Breakdown Voltage of Gate to Source (BV GSO ) Gate Threshold Voltage (V GS(TH) ) Specific On-Resistance (R on,sp ) and Drain to Source On Resistance (R ds,on ) Reverse Leakage Current (I R ) Forward Voltage Drop (V F ) Turn-on I D -V D Curve Three Dimension Simulation Three-Dimension Process Simulation Three-Dimension Electric Characteristic Simulation Three-Dimension Area Factor (β) Breakdown Voltage of Drain to Source (BV DSX ) Gate Threshold Voltage (V GS(TH) ) Specific On-Resistance (R on,sp ) and Drain to Source On Resistance (R ds,on ). 51

10 Reverse Leakage Current (I R ) Forward Voltage Drop (V F ) Study of Key Process Parameters Definition of Key Process Parameters JFET Pitch Size P+ Gate Implant Energy Schottky Mesa Width Resistivity of Epitaxial Layer Conclusion. 55 Chapter 5 Conclusion Conclusion Future work References 83

11 Figure Captions Chapter 1 Figure1.1 Discrete component markets.. 6 Figure1.2 Major types of power devices and its markets Figure1.3 Application for power devices in relation to their voltage and current rating 7 Figure1.4 Synchronous buck converter implemented by MOSFET 7 Figure1.5 Synchronous buck converter implemented by JFET integrated with JBS.. 8 Chapter 2 Figure2.1 A basic MOSFET structure.. 18 Figure2.2 A VMOSFET structure.. 18 Figure2.3 A DMOSFET structure. 19 Figure2.4 A UMOSFET structure. 19 Figure2.5 A junction field effect transistor (JFET). 20 Figure2.6 A modern version of lateral channel junction field effect transistor 20 Figure2.7 A vertical channel JFET structure using silicon planar technology 21 Figure2.8 A trench-type JFET structure. 21 Figure2.9 An Al-Si Schottky structure. 22 Figure2.10 Junction barrier Schottky diode structure. 22 Figure2.11 A Trench MOS barrier Schottky diode (TMBS) structure.. 23 Figure2.11 An Integration structure between trench MOSFET and trench MOS barrier Schottky diode (TMBS).. 23 Chapter 3 -v-

12 Figure3.1 Proposed power trench JFET integrated with SBD structure Figure3.2 Prepare N+ substrate and N-Epi Figure3.3 Grow field oxide Figure3.4 AA patterning Figure3.5 AA wet etching Figure3.6 AA cleaning Figure3.7 Source patterning Figure3.8 Source implant Figure3.9 Source cleaning Figure3.10 Deposit hard mask oxide Figure3.11 Trench patterning Figure3.12 Hard mask oxide etching Figure3.13 Trench cleaning Figure3.14 Trench etching Figure3.15 Source patterning Figure3.16 P+ gate implant Figure3.17 Source cleaning Figure3.18 Remove hard mask oxide Figure3.19 Deposit ILD-CVD oxide Figure3.20 Contact patterning Figure3.21 Contact etching Figure3.22 Contact cleaning Figure3.23 Deposit front side metal Figure3.24 Metal patterning Figure3.25 Metal etching Figure3.26 Metal cleaning Figure3.27 Alloy Figure3.28 Backside grinding and backside metal deposition

13 Chapter 4 Figure4.1 Trench etching with hard mask oxide Figure4.2 P + gate implant that with self-align hard mask oxide and source pattern 57 Figure4.3 Remove hard mask oxide Figure4.4 Deposit the LPCVD oxide as ILD Figure4.5 Contact dry etching Figure4.6 Define 2 nd source pattern and source implant Figure4.7 Strip source pattern Figure4.8 Sputter front-side metal as source electrode and alloy Figure4.9 The schematic of two-dimension unit cell Figure4.10 The breakdown voltage of drain to source Figure4.11 The electric potential profile of BV DSX (V G =-4.0V) Figure4.12 The electric field magnitude at BV DSX (V G =-4.0V) Figure4.13 The breakdown voltage of gate to source Figure4.14 The gate threshold voltage Figure4.15 The turn-on I D -V D curve for R on,sp Figure4.16 The reverse leakage current magnitude when V G =-0.4V and V D =20V.. 64 Figure4.17 The forward voltage drop when I S =10A Figure4.18 The forward voltage drop when I S =20A Figure4.19 The turn-on I D -V D curve Figure4.20 The turn-on electron current magnitude Figure4.21 Trench pattern.. 67 Figure4.22 Trench hard mask oxide etching Figure4.23 Trench etching Figure4.24 Source pattern & P+ gate implant Figure4.25 ILD CVD oxide deposition.. 69 Figure4.26 Contact etching v-

14 Figure4.27 Source pattern & source implant Figure4.28 Sputter front-side metal Figure4.29 The unit cell size of three dimension simulation Figure4.30 The BV DSX curve of three dimension simulation.. 71 Figure4.31 The electric potential profile at BV DSX Figure4.32 The electric field magnitude profile at BV DSX Figure4.33 The BV GS(TH) curve Figure4.34 The on-state I D -V D curve for Rd s,on Figure4.35 The V F (10A) curve Figure4.36 The V F (20A) curve Figure4.37 The schematic diagram of JFET pitch size and SBD mesa width Figure4.38 The chart diagram of JFET pitch size vs. BV DSX & V GS(TH) 75 Figure4.39 The chart diagram of JFET pitch size vs. BV DSX & R on,sp Figure4.40 The chart diagram of P + gate implant energy vs. BV DSX & V GS(TH). 76 Figure4.41 The chart diagram of P + gate implant energy vs. BV DSX & R on,sp Figure4.42 The net doping profile at different P + gate implant energy Figure4.43 The chart diagram of Schottky mesa width vs. BV DSX & V GS(TH) Figure4.44 The chart diagram of Schottky mesa width vs. BV DSX & R on,sp Figure4.45 The reverse recovery waveforms at different Schottky mesa width Figure4.46 The chart diagram of Epitaxy resistivity vs. BV DSX & V GS(TH). 79 Figure4.47 The chart diagram of Epitaxy resistivity vs. BV DSX & R on,sp 80

15 Table Captions Chapter 3 Table 3.1 Process flow of power trench JFET integrated with SBD structure Chapter 4 Table 4.1 Summary table of electrical characteristics of this proposal structure compared with prior structures. 80 -vi-

場效電晶體簡介.doc

場效電晶體簡介.doc (field effect transistor FET) FET (gate G ) FET (source S ) FET (drain D ) n (n-channel FET) p (p-channel FET) n FET n (channel) p FET p (channel) 1 n p FET FET (unipolar devices) 1 n p FET FET BJT FET