Microsoft PowerPoint - STU_EC_Ch12_new.ppt

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1 樹德科技大學資訊工程系 Chapter 1: Signal Interfacing and Processing Shi-Huang Chen Fall Outline Digital Signal Processing Basics Converting Analog Signals to Digital Analog-to-Digital Conversion (ADC) Methods Digital-to-Analog Conversion (DAC) Methods The Digital Signal Processor (DSP) 1

Digitalto-Analog Conversion 3 Digital Signal Processing

2 Digital Signal Processing Basics ADC: Analog-to-Digital Conversion DSP: Digital Signal Processor DAC: Digitalto-Analog Conversion 3 Digital Signal Processing Basics Basic block diagram of a digital signal processing system 4

3 Sampling Most input signals to an electronic system start out as analog signals. For processing, the signal is normally converted to a digital signal by sampling the input. Before sampling, the analog input must be filtered with a low-pass anti-aliasing filter. The filter eliminates frequencies that exceed a certain limit that is determined by the sampling rate. Analog input signal Sampling pulses Sampling circuit Sampled version of input signal 5 Anti-aliasing Filter HAY NYQUIST NYQUIST THEOEM (198) To understand the need for an anti-aliasing filter, you need to understand the sampling theorem which essentially states: In order to recover a signal, the sampling rate must be greater than twice the highest frequency in the signal. Stated as an equation, f sample >f a(max) where f sample = sampling frequency f a(max) = highest harmonic in the analog signal If the signal is sampled less than this, the recovery process will produce frequencies that are entirely different than in the original signal. These masquerading signals are called aliases. 6 3

4 Anti-aliasing Filter The anti-aliasing filter is a low-pass filter that limits high frequencies in the input signal to only those that meet the requirements of the sampling theorem. Filtered Unfiltered analog analog frequency frequency spectrum spectrum Sampling frequency spectrum f Overlap causes c aliasing error f sample The filter s cutoff frequency, f c, should be less than ½ f sample. f 7 Analog-to-Digital Conversion (ADC) To process naturally occurring analog quantities with a digital system, the analog signal is converted to digital form after the anti-aliasing filter. The first step in converting a signal to digital form is to use a sampleand-hold circuit. This circuit samples the input signal at a rate determined by a clock signal and holds the level on a capacitor until the next clock pulse. A positive half-wave from 0-10 V is shown in blue. The sample-andhold circuit produces the staircase representation shown in red. 10 V 0 V 8 4

5 Analog-to-Digital Conversion The second step is to quantize these staircase levels to binary coded form using an analog-to-digital converter (ADC). The digital values can then be processed by a digital signal processor or computer. What is the maximum unsigned binary value for the waveform? 10 V = 1010 V. The table lists the quantized binary values for all of the steps. Peak = 10 V 10 V 0 V Anti-aliasing Filter Most signals have higher frequency harmonic and noise. For most ADCs, the sampling and filter cutoff frequencies are selected to be able to reconstruct the desired signal without including unnecessary harmonics and noise. An example of a reasonable sampling rate is in a digital audio CD. For audio CDs, sampling is done at 44.1 khz because audio frequencies above 0 khz are not detectable by the ear. What cutoff frequency should an anti-aliasing filter have for a digital audio CD? Less than.05 khz. 10 5

6 Sample-and-Hold and ADC Following the anti-aliasing filter, is the sample-and-hold circuit and the analog-to-digital converter. At this point, the original analog signal has been converted to a digital signal. Samples held for one clock pulse ADC Many ICs can perform both functions on a single chip and include two or more channels. For audio applications, the AD1871 is an example of a stereo audio ADC. 11 Analog-to-Digital Conversion Methods Flash (Simultaneous) Analog-to-Digital Conversion Dual-Slope Analog-to-Digital Conversion Successive-Approximation Analog-to-Digital Converter Sigma-Delta Analog-to-Digital Converter 1 6

7 The operational amplifier (op-amp) V V out in = f i (1) V () V in1 in1 V V in in < 0, V > 0, V out out = V = V sat sat 13 Analog-to-Digital Conversion Methods V EF Op-amp comparators Input from sampleand-hold The flash ADC: The flash ADC uses a series highspeed comparators that compare the input with reference voltages. Flash ADCs are fast but require n 1 comparators to convert an analog input to an n-bit binary number. Priority encoder EN Enable pulses D 0 Parallel D 1 binary output D How many comparators are needed by a 10-bit flash ADC?

8 Analog-to-Digital Conversion Methods The dual-slope ADC: 1. The dual-slope ADC integrates the input voltage for a fixed time while the counter counts to n.. Control logic switches to the V EF input.. A fixed-slope ramp starts from V as the counter counts. When it reaches 0 V, the counter output is latched. V in I I C SW -V 0 V A 1 A EF Variable Fixed time interval 0 0 t = n counts Variable Variable voltage V Fixed-slope V ramp HIGH Control logic CLK C n EN Counter Latches D 7 D 6 D 5 D 4 D 3 D D 1 D 0 15 Analog-to-Digital Conversion Methods The successive approximation ADC: 1. Starting with the MSB, each bit in the successive approximation register (SA) is activated and tested by the digital-to-analog converter (DAC).. After each test, the DAC produces an output voltage that represents the bit. 3. The comparator compares this voltage with the input signal. If the input is larger, the bit is retained; otherwise it is reset (0). Input signal V out Comparator CLK (MSB) D C DAC SA (LSB) The method is fast and has a fixed conversion time for all inputs. D 0 D 1 D D 3 Serial binary output Parallel binary output 16 8

Analog-to-Digital Conversion Methods The sigma-delta ADC: With sigma-delta conversion, the difference between two samples of the analog input signal integrated and quantized.

9 Analog-to-Digital Conversion Methods The sigma-delta ADC: With sigma-delta conversion, the difference between two samples of the analog input signal integrated and quantized. The density of 1s at the output is proportional to the input signal. Analog input signal Summing point Σ Integrator 1-bit quantizer Quantized output is a single bit data stream. DAC 17 Analog-to-Digital Conversion Methods One option for the sigma-delta method is to count the onebit quantized output for a set interval. The output of the counter is latched with the parallel binary code. Analog input signal Summing point Σ Integrator 1-bit DAC 1-bit quantizer n-bit counter. Latch. Binary code output Sigma-delta ADCs can have high resolution and have advantages for rejecting noise signals (such as 60 Hz power line interference). They are available in ICs with internal programmable amplifiers. For these reasons, they are widely used in instrumentation applications. 18 9

10 Illustrations of ADC errors Missing code Incorrect codes Offset 19 Digital-to-Analog Conversion Methods Binary-Weighted-Input Digital-to-Analog Converter - Ladder Digital-to-Analog Converter 0 10

11 Digital-to-Analog Conversion Methods Binary-weighted-input DAC: The binary-weighted-input DAC is a basic DAC in which the input current in each resistor is proportional to the column weight in the binary numbering system. It requires very accurate resistors and identical HIGH level voltages for accuracy. The MSB is represented by the largest current, so it has the smallest resistor. To simplify analysis, assume all current goes through f and none into the op-amp. LSB D 0 D 1 D D 3 MSB 8 4 I 0 I 1 I I 3 I = 0 f I f V out Analog output 1 Digital-to-Analog Conversion Methods A certain binary-weighted-input DAC has a binary input of If a HIGH = 3.0 V and a LOW = 0 V, what is V out? 3.0 V 0 V 3.0 V 3.0 V 10 kω 60 kω 30 kω 15 kω f 10 kω Iout = ( I0 I1 I I3) 3.0 V 3.0 V 3.0 V = 0 V = 0.35 ma 10 kω 30 kω 15 kω V out = I out f = ( 0.35 ma)(10 kω) = 3.5 V V out 11

12 Digital-to-Analog Conversion Methods - ladder: The - ladder requires only two values of resistors. By calculating a Thevenin equivalent circuit for each input, you can show that the output is proportional to the binary weight of inputs that are HIGH. VS Each input that is HIGH contributes to the output: V = where V S = input HIGH level voltage n = number of bits i = bit number For accuracy, the resistors must be precise ratios, which is easily done in integrated circuits. Inputs D 0 D 1 D D out n i f = V out 3 Digital-to-Analog Conversion Methods An - ladder has a binary input of If a HIGH = 5.0 V and a LOW = 0 V, what is V out? D 0 D 1 D D V 5.0 V 0 V 5.0 V kω 4 50 kω 6 50 kω 8 50 kω 50 kω 5 kω 5 kω 5 kω f = 50 kω V out VS Apply Vout = to all inputs that are HIGH, then sum the results. n i 5 V 5 V Vout ( D0 ) = = V V ( 4 0 out D1 ) = = 0.65 V V Vout ( D3 ) = =.5 V Applying superposition, V 4 3 out = 3.43 V 4 1

esolution and Accuracy of DACs The - ladder is relatively easy to manufacturer and is available in IC packages. DACs based on the - network are available in 8, 10, and 1-bit versions.

13 esolution and Accuracy of DACs The - ladder is relatively easy to manufacturer and is available in IC packages. DACs based on the - network are available in 8, 10, and 1-bit versions. The resolution is an important specification, defined as the reciprocal of the number of steps in the output. What is the resolution of the BCN31 - ladder network, which has 8-bits? 8 1 = 55 1/55 = 0.39% The accuracy is another important specification and is derived from a comparison of the actual output to the expected output. For the BCN31, the accuracy is specified as ±½ LSB = 0.%. 5 D/A Conversion Errors 6 13

14 D/A Conversion Errors 7 The econstruction Filter The reconstruction filter smooths the output of the DAC. 8 14

15 The Digital Signal Processor (DSP) A digital signal processor (DSP) is optimized for speed and working in real time (as events happen). It is basically a specialized microprocessor with a reduced instruction set. After filtering and converting the analog signal to digital, the DSP takes over. It may enhance the signal in some predetermined way (reducing noise or echoes, improving images, encrypting the signal, etc.). The signal can then be converted back to analog form if desired. Analog signal Anti-aliasing filter Sample-andhold circuit ADC DSP DAC econstruction filter Enhanced analog signal 9 DSP Programming Because speed is important in DSP applications, assembly language is frequently used because in general it executes faster. Program cache/program memory (3-bit address, 56-bit data) CPU (DSP core) A general block diagram of the TMS30C6000 series DSP DMA EMIF Program fetch Instruction dispatch Instruction decode Data path A Data path B Control registers Control logic egister file A egister file B Test.L1.S1.M1.D1.D.M.S.L Evaluation Interrupts Data cache/data memory (3-bit address, 8-, 16-, bit data) Additional peripherals 30 15

Microsoft PowerPoint - STU_EC_Ch08.ppt

Microsoft PowerPoint - STU_EC_Ch08.ppt 樹德科技大學資訊工程系 Chapter 8: Counters Shi-Huang Chen Fall 2010 1 Outline Asynchronous Counter Operation Synchronous Counter Operation Up/Down Synchronous Counters Design of Synchronous Counters Cascaded Counters