USING THE DESIGN ASSISTANT PanDeng 2004 05
Quartus help/search Design Assistant TMG6480 Design Assistant warning 1. Combinational logic used as clock signal should be implemented according to Altera standard scheme assign clk_rst_a = CS_CPU == 1'b0 & BCTL0 == 1'b1 & Addr == 18'b000000000000001000;
always @(posedge clk_rst_a or negedge Reset) if (!Reset) RST_A<=1'd0; RST_A<=BD[7]; end DFF In a design, combinational logic that is used as a clock signal should follow the following guidelines: The gating logic should be a two-input gate or a two-input gate. NOT There should be only one input pin that acts as a primary input clock signal to the or gate. a b a && b The non-clock input clock enable signal to the or gate should be synchronized with a register. The register should be clocked by the same input pin that acts as the primary input clock signal to the or gate. If the combinational logic uses an gate, the clock port of the register that drives the gate should be active on the falling edge and the clock port of the register driven by the gate should be active on the rising edge. Or If the combinational logic uses an gate, the clock port of the register that drives the gate should be active on the rising edge and the clock port of the register driven by the gate should be active on the falling edge. and or and or 2. Input clock pin should fan out to only one set of combinational logic used as clock signal A design should not contain an input clock pin that fans out to more than one set of combinational logic that is used as a clock signal. To effectively save power using the combinational logic, you should make sure all the input clock pins in a design each fan out to only one set of combinational logic that is used as a clock signal. The following image shows an example of an input clock pin that fans out to more than one set of the combinational logic:
3. Clock signal should be a global signal 4. Clock Signal Source Should Drive Only Input Clock Ports Clock signal sources in a design should drive only input clock ports of registers. When a design contains clock signal sources that connect to ports other than clock ports, the design is considered asynchronous, which can cause problems in the design DFF CLK always @(negedge ByteCount8 or negedge RST) if (!RST) PrePassAll<=0; PrePassAll<=PrePassAlltemp; End ByteCount8 4'd8 : nextstate =(ByteCount8 && (RxData == 8'hd5))? 4'd9 : 4'd1; ByteCount8
5. Clock signal sources in a design should drive only input clock ports of registers When a design contains clock signal sources that connect to ports other than clock ports, the design is considered asynchronous, which can cause problems in the design CLK A CLKa B CLKb CLKa=CLK; CLKb=CLK; CLKa CLKb always @(negedge RXC_1 or negedge RST) if (!RST) RCLKa<=0; RCLKa<=count_rxa[1]; End always @(negedge RXC_1 or negedge RST) if (!RST) RCLKb<=0; RCLKb<=count_rxb[1]; End RCLKa RCLKb RXC_1 6. Clock Signal Source Should Not Drive Registers That are Triggered by Different Clock Edges A design should not contain nodes where a clock signal source (for example, an input clock pin) drives the design's registers in one of the following ways: The clock signal source drives registers that have clock inputs that trigger on the positive edge of the clock, and other registers that have clock inputs that trigger on the negative edge of the clock. The clock signal source drives only registers that have clock inputs that all trigger on either the positive or negative edge of the clock, but the design inverts the clock before driving some of the registers. These connections can cause various design problems, including an increase in timing requirement
complexity and difficulties. Also, because registers are not clocked on the same edge in the design, synchronous resetting is impossible. When a design inverts the clock, additional design problems may occur; for example, the inverted clock may be mapped to regular logic or may not contain the correct time relationship to the original clock. The registers that synchronize combinational logic that is used as a clock or reset signal are sometimes triggered by different clock edges. However, these registers do not cause problems in the design. always @ (negedge RCLKb or negedge RXDV_1) if(!rxdv_1).. end always @(posedge RCLKb or posedge RXDVb) if (!RXDVb) ByteCnt_b<=0; ByteCnt_b<=ByteCnt1_b+1'd1; End RCLKb RXDV_1 RXDVb negedge posedge 7. Two or More Register Outputs in Cascade Should Not Directly Drive Clock Ports of Following Registers Q A design should not contain ripple clock structures, that is, structures where the outputs of two or more registers in a cascade each directly drives the input clock port of the following register in the cascade. Cascading registers should have only one output, or no output, that directly drives the following register's input clock port. The following image shows an example of a ripple clock structure:
1 2 8. Inverter should not be implemented in logic cell CLK LUT inverter Instead, the inverter should be implemented with the register clock's programmable invert. module temp(a,b,c,d); output a; input b; input c; input d; reg a; always @(negedge b) if (!d) a<=1'b0; a<=c; end endmodule
FDR_1 D Flip-Flop with Negative-Edge Clock and Synchronous Reset FDR_1 9. Combinational logic used as reset signal should be synchronized. always @(posedge a or posedge CLR) : D1 if (CLR) a <= 1'b0; a <= 1'b1; end always @(negedge b or posedge CLR) : D2 if (CLR) b <= 1'b0; b <= 1'b1; end assign CLR = a & b ; DFF that is, the combinational logic should drive a register before driving one or more input reset ports of other registers. An asynchronous reset can cause glitches and stability problems in a design.
10. External Reset Should be Synchronized Using Two Cascaded Registers DFF An external reset, which is a primary input that is used as a reset signal, should be synchronized in a design (that is, it should drive two cascaded registers before driving one or more input reset ports of other registers). In a design, an asynchronous reset can affect the recovery time of a register, cause stability problems, and reset state machines to incorrect states. The synchronized gated reset should follow the following guidelines: The external reset should be synchronized with two cascaded registers. There should be no logic between the two cascaded registers. DFF 11. Reset Signal Source Should Drive Only Input Reset Ports DFF always @(posedge clka or negedge RST) if (!RST).. always @(posedge clkb or negedge RST) if (!RST)... DFF RST always 12. External reset should be correctly synchronized In a design, the synchronization of an external reset (which is a primary input that is used as a reset signal) should follow the following guidelines:
The external reset should be synchronized with two cascaded registers. There should be no logic between the two cascaded registers. 13. Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized In a design, a reset signal that is generated in one clock domain and used in one or more other, asynchronous clock domains should follow the following guidelines: The reset signal should be synchronized with two or more cascading registers in the receiving asynchronous clock domain The cascading registers should be triggered on the same clock edge. There should be no logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain. An incorrectly synchronized reset signal may cause metastability problems in the design. 14. Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized Timing Closure 15. Nodes with more than specified number of fan-outs. This rule reports the specified number of nodes with the highest fan-out, which can create timing challenges for a design. You can specify that the Design Assistant use this rule by turning on Top nodes with highest fan-out: <n> under Timing closure in the Design Assistant rules list in the Design Assistant page of the Settings dialog box (Assignments menu). You can use the High-Fanout Net Settings dialog box, which is available from the Design Assistant page, to specify the number of nodes you want the Design Assistant to report. The Design Assistant Settings section of the Report window lists the options you turn on and the settings you specify. The Design Assistant lists the nodes in the Messages window, the Design Assistant Messages section of
the Report window, and the Design Assistant Detailed Results section of the Report window. FPGA 16. Top nodes with highest fan-out. 17. Register output directly drives input of another register when both registers are triggered at same time If the two registers are triggered by clock edges at the same time, a hold time violation may occur. 18. Registers in direct data transfer between clock domains are triggered by clock edges at the same time In a design, the output of a register in one clock domain directly drives the input of another, synchronous register in another clock domain. If the two synchronous registers are triggered by clock edges at the same time, a hold time violation may occur. Non-synchronous design structure 19. Design should not contain delay chains A design should not contain any delay chains, which are two or more consecutive nodes with a single fan-in and a single fan-out that are used to cause delay. Delay chains often result from asynchronous design practices and can cause various design problems, including an increase in a design's sensitivity to operating conditions, a decrease in a design's reliability,
20. Design Should Not Contain Latches Latch A design should not contain latches, which are structures where two or gates (which the Quartus II software implements in logic cells) are cross-coupled using combinational loops that drive the output of one gate to an input of the other gate. These latches can cause glitches and ambiguous timing in a design, which makes timing analysis of the design more difficult. The Design Assistant generates this rule when it identifies one or more structures as latches but cannot determine the latch types. The latches may also be part of more sophisticated latches that the Design Assistant cannot identify. Latch glitch ambiguous 21. Design should not contain combinational loops. module temp(a,b,c); output a; input b; input c; assign a=c?b:a; endmodule a 22. Register output should not drive register's control signal directly or through combinational logic.
always @(posedge VCOCLK or posedge CLR) : D1 if (CLR) Q_VCO <= 1'b0; Q_VCO <= 1'b1; end always @(negedge REFCLK or posedge CLR) : D2 if (CLR) Q_REF <= 1'b0; Q_REF <= 1'b1; end assign CLR = Q_VCO & Q_REF ; DFF CLR A design should not contain any combinational loops where the output of a register directly drives one of its own control signals (for example, the register's preset signal or asynchronous load signal), or the output of the register drives combinational logic that drives one of the register's control signals. 1 2 These combinational loops can cause significant stability and reliability problems in a design. For example, because the behavior of a combinational loop often depends on the relative propagation delays of the combinational loop's logic, and because design tools experience difficulties when handling combinational loops, the combinational loop after fitting may not function as it was originally intended to function in the design. The following image shows an example of a combinational loop where the output of a register directly drives one of its own control signals: The following image shows an example of a combinational loop where the output of a register drives combinational logic that drives one of the register's control signals:
Clock 1. Combinational logic used as clock signal should be implemented according to Altera standard scheme 2. Inverter should not be implemented in logic cell 3. Input clock pin should fan out to only one set of combinational logic used as clock signal 4. Clock signal source should drive only input clock ports 5. Clock signal should be a global signal 6. Clock signal source should not drive registers that are triggered by different clock edges Reset 7. Combinational logic used as reset signal should be synchronized 8. External reset should be synchronized using two cascaded registers 9. External reset should be correctly synchronized 10. Reset signal source should drive only input reset ports 11. Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized 12. Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized Timing Closure 13. Nodes with more than specified number of fan-outs. 14. Top nodes with highest fan-out. 15. Register output directly drives input of another register when both registers are triggered at same time 16. Registers in direct data transfer between clock domains are triggered by clock edges at the same time
Non-synchronous design structure 17. Design should not contain combinational loops 18. Register output should not drive register's control signal directly or through combinational logic 19. Design should not contain delay chains 20. Two or more register outputs in cascade should not directly drive clock ports of following registers 21. Pulses should be implemented according to Altera standard scheme 22. Multiple pulses should not be generated in design 23. Design should not contain SR latches 24. Design should not contain latches 25. Combinational logic should not directly drive write enable signal of asynchronous RAM 26. Design should not contain asynchronous memory Signal race 27. One signal source should not drive both input and output enable of tri-state node Asynchronous clock domains 28. Data bits are not synchronized when transferred between asynchronous clock domains 29. All data bits that are transferred between asynchronous clock domains are synchronized 30. Data bits are not correctly synchronized when transferred between asynchronous clock domains HardCopy rules 31. Asynchronous load should be directly supported by one logic cell 32. Only one VREF pin should be assigned to HardCopy test pin in an I/O bank 33. PLL drives multiple clock network types Assignment checking 34. Design is missing fmax requirement 35. Design is missing tco, tpd, or tsu requirement