Terasic Technologies Company Introduction
Outline
Outline DE1-SoC 快速入门 SoC FPGA 设计流程 DE1-SoC 硬件实验 DE1-SoC 软件实验 DE1-SoC 进阶应用 Demo
DE1 SoC 快速入门
开发设计软件 Altera Quartus II Altera SoC Embedded Design Suite
实验教材文件 目录 内容 cd lb lab tool DE1-SoC 开发板光盘. 内有原理图, 设计范例等 本次实验课所使用到的设计范例 实验中所需要的驱动, 软件工具 (Quartus, EDS..etc.).
DE1 SoC Mode Select Switch MSEL[4:0] 设定模式 描述 10010 AS FPGA configured from EPCQ (default) 01010 FPPx32 FPGA configured from HPS software: Linux FPGA configured from HPS software: U-Boot, with 00000 FPPx16 image stored on the SD card, like LXDE Desktop or console Linux with frame buffer edition.
DE1 SoC 连接设定 USB Blaster II UART-to-USB Power Jack
安装 USB Blaster II 驱动 USB Blaster II : 下载 FPGA code, Debug HPS / FPGA
下载.sof 入 FPGA 测试
安装 UART to USB USB 驱动
Speed : 115200 p Serial Line : COMx Connection : Serial 设定串口终端工具
在 DE1 SoC 上运行 Linux 将 MicroSD card 插入 DE1-SoC
SoC FPGA 设计流程
SoC FPGA 系统开发流程
SoC FPGA 系统架构 处理器 4000 MIPs (up to 800Mhz per core) 双核 ARM Cortex-A9 处理器 NEON 媒体处理引擎 丰富的内嵌外围设备 32-KB L1 Caches 每核 512-KB L2 Cache 硬核内存控制器 支持 DDR2, DDR3 和 LPDDR2 支持 ECC 高带宽通道 HPS to FPGA FPGA to HPS FPGA to HPS SDRAM
HPS IP Features 双核 ARM Cortx-A9 处理器 SDRAM 控制器 DMA 控制器 2 Ethernet MACs NAND, QSPI, SD 和 MMC flash 控制器 Serial Interface - 2 USB OTG 控制器 - 2 SPI master 控制器 - 2 SPI slave 控制器 - 4 I2C 控制器 -2 CAN 控制器 2 串口 GPIO
SoC FPGA 设计理念 FPGA: 看起来像 FPGA 用起来像 FPGA 标准的 FPGA 开发流程 使用传统的开发工具 : Qurtus II, Qsys, Signal TabII, System Console, Programmer ARM HPS: 看起来像 ARM 处理器系统 用起来像 ARM 处理器系统 传统的 ARM 处理器开发流程 使用传统的 ARM 处理器开发工具 : ARM Cortex-A9 compiler/debugger, JTAG tools, program trace
SoC 硬件设计流程
创建 Quartus II 专案
Qsys 系统集成工具 使用 GUI 接口来做系统设计 简化系统开发的复杂性 为 IP 模块间自动生成内部连接 提供标准开发平台 IP integration Custom IP authoring IP verification 设计可再利用
为 Qsys 系统增添组件 包括 HPS, 现有的 IP 和客制化 IP 组件都可以在 Qsys 的 component Library 呼叫使用 可使用搜寻功能来找寻 IP 鼠标点击 IP 组件便可加入系统
创建一个新的 Qsys 系统
HPS 组件设定
HPS 组件设定页面 FPGA Interfaces Peripheral Multiplexing l i HPS Clocks SDRAM
Add Custom Components to Qsys 使用 Component Editor 支持标准 Interfaces Avalon-MM (memory mapped) Avalon-ST (streaming) ARMAXI30&40 AXI 3.0 4.0 ARM APB ARM AHB
建立元件間的連線 透过鼠标左键点击拉线建立连结 透过鼠标右键选择特定接口来建立连接
Generate Completed System
System Console Quick system-level l debug of Qsys systems Interactive Tcl Console Debug over various communication channels JTAG, USB or TCP/IP Read form or write to memory mapped components No processor required
On Chip Component Debug
SoC 硬件实验
硬件实验流程 了解 DE1-SoC 硬件系统架构 检视 HPS 系统 添加并配置 LED 和 Button PIO 组件 编译生成 Qsys 系统 编辑并编译 Quartus II 工程 验证硬件系统设计
DE1 SoC 系统框图
定义硬件系统架构
Golden Hardware Reference Design (GHRD) 提供 DE1-SoC 完整的 Quartus II 專案 基本的頂層 top.v 文件 Qsys : HPS (pin mux / ddr3 / clock etc.), AXI-bridge, On-ChipRAM and basic FPGA component 完整的 Pin assignment, SDC 文檔 可在 DE1-SoC CD 內取得
GHRD Qsys 组件一览 Golden System Reference Design
配置 HPS 系统 (1)
配置 HPS 系统 (2)
HPS 组件设定
通用选项与 Boot 控制 Events Event in and out Wait for event condition Wait for interrupt condition GIPO Debug interface Boot from FPGA
FPGA HPS Interfaces
HSP FPGA AXI Bridge
AXI Bridges FPGA-to-HPS 访问外设与内存 4GB space Widths 32, 64, 128 HPS-to-FPGA 960 MB space Widths 32, 64, 128 Lightweight HPS-to-FPGA Low performance (32 bits) 可以对 FPGA 组件控制并读取状态 2 MB space 可以连接 Avalon 总线
FPGA to SDRAM
FPGA to HPS SDRAM Interfaces AXI-3 or Avanlon-MM Select the number of interfaces Data widths: 32, 64, 128, 256
Other Interfaces to the HPS Resets FPGA can control debug, warm or cold reset signals HPS can send cold and warm reset signals to FPGA DMA requests Enable up to 8 from the FPGA Interrupts 64 inputs from FPGA to HPS interrupt controller HPS peripheral interrupt output to FPGA
HPS I/O Muxing Overview
Peripheral Pin Multiplexing Enable peripheral interface and choose modes Select I/O set
HPS I/O 管脚特性 可使用的外设的数目多于 HPS I/O 可使用的外设的数目多于 HPS I/Os 多数外设需要共享 HPS I/Os
Pin Usage and Conflicts
HPS Pin Assignments HPS 管脚设定会自定被 Quartus compiler 设定 SDRAM I/O 需要执行.tcl 来设定 执行 hps_sdram_po_pin_assigments.tcl I/O Standard
HPS Clock Block Diagram
HPS Clock Enable HPS clocks into the FPGA Drive FPGA clocks into HPS PLLs Peripherals SDRAM
SDRAM 一至的 SDRAM GUI Megafunction 界面 支持数种内存 DDR3 DDR2 LPDDR2 设置 clock 以及初始设定
設定 SDRAM 的 Timing & Skew
SoC EDS Contents
SoC Embedded Development Suite (SoC CEDS) Contains everything you need for firmware and application development on the Altera SoC hardware platform Board bring up Bare-metal application development and debugging Device driver development Linux based application development and debugging Debug systems running symmetrical multiprocessing Debug software targeting soft IP that resides in the FPGA fabric
SoC EDS Contents ts Component Key Feature Web Edition Subscription Edition Eclipse IDE Debugging over Ethernet (Linux) ARM Development Studio Debugging over USB Blaster II (JTAG) 5(DS 5) 5) Altera Edition Toolkit Automatic register views Hardware cross triggering CPU/FPGA event correlation Hardware/Software Interface Tools Compiler Tools Preloader Support Package Generator Device Tree Generator Linaro Linux GCC tool chain (arm linuxgnueabihf ) Mentor CodeBench Lite Bare metal GCC tool chain (arm none eabi ) SoC Hardware Libraries HWLibs SoC Programming Examples Golden Hardware Reference Design,Variety of software and Linux examples
ARM DS 5 Altera Edition Select Perspective Project File Viewer Outline View Terminal Window
Embedded Command Shell Cygwin base build environment Similar to Nios Command Shell <SoC EDS Installation <SoC EDS Installation folder>\embedded\embedded_comannd_sheel.bat
Hard Ware to Software Handoff Files
Generated Handoff Files Handoff for the preloader generator Contains information chosen during HPS component instantiation Preloader generator uses hand off to generate the preloader binary which used to setup the pin mux, SDRAM, clocks, etc. System View Description file (CMSIS-SVD) XML file allows registers of soft IP in FPGA to show within the DS-5.sopcinfo.sopcinfo Describes the FPGA system to Altera s device tree generator for uses in the linux envionment
生成 Preloader
Application Class Processor Booting Flow BootROM Stored in on chip ROM Preloader Stored in flash, runs from SDRAM U Boot Stored in flash, runs from SDRAM Linux Kernel Stored in flash/network, runs from SDRAM Run Application
生成 Preloader 流程
Handoff Folder
Handoff Folder
Preloader Source
Preloader Image File uboot-socfpga/spl/u-boot-spl Description Preloader ELF file uboot-socfpga/spl/u-boot-spl.bin b t l bi Preloader binary file
生成 Device Tree
Linux Device Tree
生成 Device Tree 流程
SOPC Info File
.dts 文件内容
生成 Device Tree Flow
可 Boot Linux MicroSD Card 内容
ARM DS 5 Altera Edtion
ARM DS 5 Altera Edtion File editing Project management Debugging Run control (Run, stop, breakpoints) Variables/Watch view HPS Register View FPGA and Soft IP Register View (using CMSIS-SVD SVD file) Tracing Cross-Triggering Profiling
DS 5 Debug Feature FPGA Trigger HPS Tracing Linux Kernel Debugging
ARM DS 5 Debugger Select Perspective Project File Viewer Outline View Terminal Window
Importing Project (1)
Importing Project (2) Highlight Project Select Project => Build Project Create ARM executable file (.axf)
Importing Project (3) Debug/Run configurations configure session Run scripts that specific setup and breakpoint procedures Repeatability
ARM DS 5 Debugger Perspectives Change Perspectives between C/C++ development and Debug
ARM DS 5 Demo Simple Hello_word HPS Control HPS LED HPS Control FPGA LED
Software Flow : Bare metal ae eta Application
System View Description file (CMSIS SVD) S SVD)
XML file allows registers of soft IP in FPGA to show within ihi the DS 5