Software Boot and PL Configuration

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1 Xilinx All Programmable 客户技术培训 1Software Boot and PL Configuration

2 **slide Objectives After completing this module, you will be able to: Differentiate between program storage and execution memory options and when to use them State various mechanisms for system initialization and application loading Describe the Zynq All Programmable SoC programmable logic (PL) configuration process from an FSBL software application Describe the flash writer utility and its requirements Analyze flash writing and different boot loading usage scenarios Software Boot and PL Configuration - 2 Copyright 2014 Xilinx 40362

4 **slide Introduction Embedded applications can range in size from a few kilobytes to a few megabytes Two types of external memory may be required Non-volatile memory for storing program and initialized data Memory for running the program If the application size and initialized data are small enough, they can then be downloaded into internal block RAM or OCM RAM A small application is needed to load the program from non-volatile memory into operational RAM Runs on power-on reset and soft resets Known as a boot loader Several mechanisms are available for loading large programs and data stored in non-volatile memory Software Boot and PL Configuration - 4 Copyright 2014 Xilinx 40362

5 5 Standard Zynq All Programmable SoC Boot Model PS is Boot Master Multi-stage boot process Stage 0: Runs from ROM; loads from non-volatile memory to OCM Provided by Xilinx; unmodifiable Stage 1: Runs from OCM; loads from non-volatile memory to DDRx memory User developed; Xilinx offers example code SDK project Initiates PS boot and PL configuration Stage 2: Optional; runs from DDR User developed; Xilinx offers example code Uboot Sourced from flash memory or through common peripherals, programmable logic I/O, etc. Programmable logic configuration can be performed in Stage 1 or 2 Software Boot and PL Configuration - 5 Copyright 2014 Xilinx 40362

6 **slide Zynq All Programmable SoC Program Loading and Initialization Mechanisms Debug mode: Configure PL with bitstream then run the application from XMD Boot mode: FSBL or SSBL configure PL with bitstream Size of application impacts where program can run from Very small applications can run from OCM (no DDR requirement) Small applications can run from BRAM (no DDR requirement) Applications can run from non-volatile or DDR memory Loading the application with a boot loader Use nonvolatile memory to store the application, initialize the processor memory from it, and execute it May execute application directly from flash or other non-volatile memory Software Boot and PL Configuration - 6 Copyright 2014 Xilinx 40362

address map AMBA, AXI interfaces, memory-mapped I/O, register access Custom Peripheral Code Snippet

7 7 Cortex-A9 Processor Memory Space in the Zynq-7000 AP SoC Processing system and programmable logic look the same from the processor's viewpoint Zynq All Programmable SoC PS-based peripherals have a fixed address map AMBA, AXI interfaces, memory-mapped I/O, register access Custom Peripheral Code Snippet Programmer s View of Custom Accelerators and Peripherals Software Boot and PL Configuration - 7 Copyright 2014 Xilinx 40362

8 18487**slide Configuring the PL through SDK Download the bitstream and then the application Select Xilinx Tools > Program FPGA Locate and select hardware bit file No BMM file as the ELF runs in PS

8 **slide Configuring the PL through SDK Download the bitstream and then the application Select Xilinx Tools > Program FPGA Locate and select hardware bit file No BMM file as the ELF runs in PS DDR memory Click Program The programmable logic configures and starts executing the application in DDR memory When launched (later), the XMD debugger will halt the processor and load the actual application for debugging Software Boot and PL Configuration - 8 Copyright 2014 Xilinx 40362

Double-click Xilinx C/C++ ELF(GDB) to create a run configuration for application Click Run to

9 9 Software Program Loading in the Zynq All Programmable SoC (1) Run configurations through SDK Select software application in the project explorer pane Select Run > Run Configurations Double-click Xilinx C/C++ ELF(GDB) to create a run configuration for application Click Run to download executables (.elf) and run application Software Boot and PL Configuration - 9 Copyright 2014 Xilinx 40362

10 51500**slide Software Program Loading in the Zynq All Programmable SoC (2) Debug using XMD If PL is used, select Xilinx Tools > Program FPGA Choose the.

10 **slide Software Program Loading in the Zynq All Programmable SoC (2) Debug using XMD If PL is used, select Xilinx Tools > Program FPGA Choose the.bit file and click Program; programmable logic configures Launch XMD and select Xilinx Tools > XMD Console Command console opens Connect to ARM hardware dow FSBL.elf to initialize PS dow <executable>.elf downloads executable Software Boot and PL Configuration - 10 Copyright 2014 Xilinx 40362

11 **slide Program Loading and Initialization Mechanisms (MicroBlaze Processor) Initializing bitstreams with the application Application is small enough to be contained within the programmable logic Downloading an application by using XMD Application resides in external memory, use XMD to download the application after the programmable logic has been configured with the bitstream Bitstreams must be initialized with the BootLoop program in order to place the processor in a proper state between bitstream downloading and application downloading through XMD Loading the application with a boot loader Use nonvolatile memory to store the application, initialize the processor memory from it, and execute it May be executing application from flash or other non-volatile memory Software Boot and PL Configuration - 11 Copyright 2014 Xilinx 40362

12 51285**slide Bitstream Initialization in SDK (MicroBlaze Processor) Initialize bitstreams with the application Select Xilinx Tools > Program FPGA Locate and select hardware bit and block RAM

12 **slide Bitstream Initialization in SDK (MicroBlaze Processor) Initialize bitstreams with the application Select Xilinx Tools > Program FPGA Locate and select hardware bit and block RAM location bmm files Specify an ELF to download and click Program Initialize bitstreams with BootLoop BootLoop is a software application that keeps the processor in a defined state until the actual application is downloaded in a controlled manner by the debugger Select Xilinx Tools > Program FPGA, select BootLoop, and click Program The programmable logic configures and starts executing the BootLoop program in block RAM When launched (later), the XMD debugger will halt the processor and load the actual application for debugging Software Boot and PL Configuration - 12 Copyright 2014 Xilinx 40362

13 **slide Software Program Loading with XMD (MicroBlaze Processor) Processor hardware debug unit must already be instantiated (JTAG) For MicroBlaze-processor systems, the processor must be connected to a Microprocessor Debug Module (MDM) Select Xilinx Tools > Program FPGA, select BootLoop, and click Program; programmable logic configures in an infinite loop Select Xilinx Tools > Program FPGA to download and execute the selected BootLoop Select Xilinx Tools > XMD Console to launch XMD Command console opens dow <executable>.elf downloads executable Software Boot and PL Configuration - 13 Copyright 2014 Xilinx 40362

15 **slide Boot Loader What is a boot loader? First program run Runs on power up or reset Copies program from non-volatile memory to DDR/OCM/block RAM Could load application directly, an OS loader, or the OS itself When done transfers control to selected program Why? Final software system... Might not fit into ROM Might require some kind of run-time set up before it is launched Might be determined dynamically Boot loaders tend to range from simple to quite complex systems May include communication drivers to download application from remote location May include decompression/decryption engine for compressed/encrypted images Software Boot and PL Configuration - 15 Copyright 2014 Xilinx 40362

16 **slide Boot Load Scenarios Commonly used boot load scenarios Booting from flash devices Booting from PROMs Booting from a serial line Booting from Ethernet with BootP and TFTP Booting from PCIe or other communications interface Command line-based interactive boot load Each method has its advantages, disadvantages, and applicability Software Boot and PL Configuration - 16 Copyright 2014 Xilinx 40362

17 **slide Image Formats Boot loader must understand both Image format of the file (application, bitstream, or data) Organization of the images in the NV storage medium Formats Common: ELF, Intel MCS-86 file (.mcs),.bin, Motorola SREC, Intel I-hex, binary, gzip/bzipped images Less common: Custom formats are common as well Image formats have different processing complexities and sizes ELF, SREC/iHex, binary, compressed Decreasing order of size requirements Compressed, ELF, SREC/iHex, binary Decreasing order of processing complexity Software Boot and PL Configuration - 17 Copyright 2014 Xilinx 40362

18 18 Stage 0: ROM Based (Zynq All Programmable SoC) Processor boots from boot ROM (128KB) Xilinx provided Not viewable Copies First Stage Boot Loader (FSBL) from memory device to OCM static RAM (256KB) Maximum size is 192KB (rest can be used as stack, BSS, or non-initialized memory) Xilinx provided Starts executing FSBL from OCM RAM Software Boot and PL Configuration - 18 Copyright 2014 Xilinx 40362

19 19 Stage 1: First Stage Boot Loader (FSBL) (Zynq All Programmable SoC) Example FSBL provided by Xilinx as an SDK example project Otherwise user developed Copies next stage of code into DDRx or static memory (OCM) And/or enables an external device for Stage 2 Further initialization of PS components and peripherals Optionally configures programmable logic Upon completion, launches application or Second Stage Boot Load Software Boot and PL Configuration - 19 Copyright 2014 Xilinx 40362

20 20 Stage 2: Second Stage Boot Loader (SSBL) (Optional) (Zynq All Programmable SoC) Example U-Boot provided by Xilinx Otherwise user developed Loaded from user-selected external device Flexibility in boot sources Static memory Dynamic memory PS peripherals such as USB, Ethernet, or SD Programmable logic I/Os Initializes rest of PS Optionally configures PL Software Boot and PL Configuration - 20 Copyright 2014 Xilinx 40362

21 **slide Boot Loader Flow in SDK (MicroBlaze Processor) Build the target software application as an ELF executable file Use the Flash Writer utility to Convert the application ELF to a Motorola S-Record format, an industry-standard format mostly used for flash programming Generate boot loader application Explained in the next section Select Xilinx Tools > Program FPGA, specify the boot loader application to be used, and click Program The programmable logic configures with the launch of the boot loader application On system start up, the boot loader fetches image from the boot load target Copies/unpacks the image to external memory Performs other initialization, if needed Transfers control to the entry point of the final application Software Boot and PL Configuration - 21 Copyright 2014 Xilinx 40362

23 **slide Zynq All Programmable SoC PS Boot and PL Configuration Overview Boot Loader Zynq All Programmable SoC PS Boot and PL Configuration Flash Programmer Utility Summary Software Boot and PL Configuration - 23 Copyright 2014 Xilinx 40362

24 24 Zynq-7000 All Programmable SoC Boot and Configuration Zynq-7000 All Programmable SoC devices can be booted and/or configured in Secure mode via static memories only (JTAG excluded) Ability to have secure software and protects bitstream and IP Non-secure mode via JTAG or static memories (debug and development environment) Standard boot model Three master boot devices QSPI: serial memory, linear addressing NAND: complex parallel memory NOR: parallel memory, linear addressing SD: Flash memory card JTAG: download cable Secondary boot devices USB, Ethernet, and most other peripherals Software Boot and PL Configuration - 24 Copyright 2014 Xilinx 40362

25 Non-Secure OS Boot Example Software Boot and

26 Secure Boot Example Software Boot and PL

27 Secure Linux Boot Example Software Boot and

28 28 Processing System (PS) Boot Configuration Handoff The Zynq All Programmable SoC is a processor first, programmable logic second Most options, features, and configurations are controlled by software setup Clock generation MIO usage Processor cache and memory configuration The Vivado Design Suite Export to SDK utility generates the PS configuration code Used by FSBL Various *.c and *.h files Software Boot and PL Configuration - 28 Copyright 2014 Xilinx 40362

29 **slide Software Drivers Xilinx provides drivers for all primary boot interfaces Linux driver Standalone driver Example FSBL provided Example SSBL provided Software Boot and PL Configuration - 29 Copyright 2014 Xilinx 40362

30 **slide PL Device Configuration Services Used by FSBL Set of Standalone library services The device configuration interface has three main functionalities AXI-PCAP Security policy System monitor Currently not implemented Supports the downloading of the programmable logic bitstream and readback of the decrypted image Services are detailed in the Software Developers Guide (UG821) Software Boot and PL Configuration - 30 Copyright 2014 Xilinx 40362

31 **slide SDK FSBL Support SDK software project Complete FSBL boot application Software application load PL configuration from bit file Support for golden image Requires *.bif file for image generation All source code is included Can be modified for other boot sources Ethernet USB Serial Software Boot and PL Configuration - 31 Copyright 2014 Xilinx 40362

32 41333**slide Building the FSBL Software Application Project Created with an SDK software project template Automatically loads program and bit file images from

32 **slide Building the FSBL Software Application Project Created with an SDK software project template Automatically loads program and bit file images from flash Requires a special FSBL partition image in flash BootGen tool builds flash image binary Software Boot and PL Configuration - 32 Copyright 2014 Xilinx 40362

33 **slide Programming the PL from SDK Configure PL from SDK Select Xilinx Tools > Program FPGA Specify hardware BIT file Files typically located in the Vivado Design Suite project No BMM file as the ELF file runs in DDR memory Once PS is configured, use RUN command to download new ELF file Software Boot and PL Configuration - 33 Copyright 2014 Xilinx 40362

34 50639**slide Creating a Single Boot Image File Creating a Zynq All Programmable SoC boot image file using SDK Right-click the software application project and select Create Boot Image Add the FSBL

34 **slide Creating a Single Boot Image File Creating a Zynq All Programmable SoC boot image file using SDK Right-click the software application project and select Create Boot Image Add the FSBL ELF file Add the PL bitstream file (if PL design available) Add the software application ELF file Select the output file name Click Create Image to create the image file Output files (based on extension.bin or.mcs) Creates Intel MCS-86 file (.mcs) for programming flash Creates.BIN image for booting the application from the SD card Software Boot and PL Configuration - 34 Copyright 2014 Xilinx 40362

35 35 PS Boot and PL Configuration Example 1 Enclosed System 1. PS runs Stage 0 boot from OCM-ROM, which loads the First Stage Boot Loader from Flash into OCM-RAM 2. PL bitstream may be loaded into the PL under FSBL control at this time or may be deferred until later 3. FSBL loads Second Stage Boot Loader or Application into DDRx memory and runs SSBL / Application When SSBL is complete, the OS begins execution out of DDRx memory Optionally, PL may be configured from SSBL now or even later under user software control Software Boot and PL Configuration - 35 Copyright 2014 Xilinx 40362

36 PS Boot and PL Configuration Example 2 Using Flash Memory and an SD Card 1. PS runs Stage 0 boot from OCM-ROM, which loads the First Stage Boot Loader from Flash into OCM-RAM 2.

36 36 PS Boot and PL Configuration Example 2 Using Flash Memory and an SD Card 1. PS runs Stage 0 boot from OCM-ROM, which loads the First Stage Boot Loader from Flash into OCM-RAM 2. PL bitstream may come from SD card or Flash and is loaded into the PL under FSBL control at this time or may be deferred until later 3. FSBL loads Second Stage Boot Loader or Application from the SD card into DDRx memory and runs SSBL / Application When SSBL is complete, the OS begins execution out of DDRx memory Optionally, PL may be configured from SSBL now or even later under user software control Software Boot and PL Configuration - 36 Copyright 2014 Xilinx 40362

37 PS Boot and PL Configuration Example 3 Networked System 1. PS runs Stage 0 boot from OCM-ROM, which loads the First Stage Boot Loader from Flash into OCM-RAM 2.

37 37 PS Boot and PL Configuration Example 3 Networked System 1. PS runs Stage 0 boot from OCM-ROM, which loads the First Stage Boot Loader from Flash into OCM-RAM 2. FSBL may configure the PL at this time or defer configuration 3. FSBL configures Ethernet MAC and loads Second Stage Boot Loader or Application from the remote server into DDRx memory and runs SSBL / Application When SSBL is complete, the OS begins execution out of DDRx memory Optionally, PL may be configured during FSBL or SSBL or even later under user software control Software Boot and PL Configuration - 37 Copyright 2014 Xilinx 40362

38 **slide Configuring and Re-Configuring the PL The PL is configured via the device configuration interface module Accessed via a software application using an AXI port in the PS Supported by Xilinx-provided APIs in SDK Recommended methodology Separate DMA port into the Central interconnect for simultaneous PL configuration with software download Accessed from the PL via a GPx master AXI port Not recommended Software Boot and PL Configuration - 38 Copyright 2014 Xilinx 40362

39 **slide Flash Programmer Utility Overview Boot Loader Zynq All Programmable SoC PS Boot and PL Configuration Flash Programmer Utility Summary Software Boot and PL Configuration - 39 Copyright 2014 Xilinx 40362

40 Flash Image Generation Flow (Zynq All Programmable SoC)

41 41 Flash Programming Support (Zynq All Programmable SoC) Use of the Vivado hardware manager to program flash Assign flash image to flash memory attached to the Zynq device Connect to the JTAG chain containing the ARM DAP of the Zynq device Download the flash programming application into the PS of the Zynq device using the hardware manager Procedure Erase: the hardware manager tells the Zynq device application to erase flash memory Program: the hardware manager loads the flash image into the PS buffer of the Zynq device; Zynq device application writes the image to flash memory Verify: Zynq device reads the flash contents and writes into buffer; reads the buffer and compares against the original flash image Use of SDK to program flash Creates a flash Image using a flash image generator The flash writer uses the same programming engine as hardware manager Software Boot and PL Configuration - 41 Copyright 2014 Xilinx 40362

42 Creating a First Stage Bootload Software Application (Zynq All Programmable SoC) SDK supports an example FSBL software application project Target application must be in Zynq device FSBL format in

42 42 Creating a First Stage Bootload Software Application (Zynq All Programmable SoC) SDK supports an example FSBL software application project Target application must be in Zynq device FSBL format in flash RAM must exist at location targeted by flash image format Selection of target hardware processor(s) FSBL May configure the programmable logic with hardware bitstream May load OS image or standalone image or SSBL image from the non-volatile memory to RAM (DDR) Transfers program control to the newly loaded application/os Xilinx FSBL supports multiple partitions; each partition can be a code image or a bitstream Software Boot and PL Configuration - 42 Copyright 2014 Xilinx 40362

43 50643**slide Flash Programming Utility (Zynq All Programmable SoC) Select Xilinx Tools > Program Flash Select the image file and offset A

43 **slide Flash Programming Utility (Zynq All Programmable SoC) Select Xilinx Tools > Program Flash Select the image file and offset A full flash image offset will always be 0 Click Program to "flash" the image Software Boot and PL Configuration - 43 Copyright 2014 Xilinx 40362

44 18502**slide Parallel Flash Memory Boot (MicroBlaze Processor) SDK provides a Program Flash Memory dialog box for programming flash devices Supports flash devices that support Intel command sets

44 **slide Parallel Flash Memory Boot (MicroBlaze Processor) SDK provides a Program Flash Memory dialog box for programming flash devices Supports flash devices that support Intel command sets Supports most all physical flash arrangements Supports flash bootloader software application creation Supports an executable file as an input format and provides the option of converting it into SREC format Flash devices must interface through the EMC peripheral Requires XMD to execute a Tcl file to perform programming and verification functions Software Boot and PL Configuration - 44 Copyright 2014 Xilinx 40362

location targeted by SREC format All source is provided and can be modified Address of flash memory must be specified in

45 45 Creating a Boot Load Software Application (MicroBlaze Processor) SDK supports an example boot load software application project Target application must be in SREC format in flash (as provided by the flash programming utility) RAM must exist at location targeted by SREC format All source is provided and can be modified Address of flash memory must be specified in blconfig.h Boot messages sent to STDout if VERBOSE symbol defined Software Boot and PL Configuration - 45 Copyright 2014 Xilinx 40362

46 18504**slide Flash Writer Utility (MicroBlaze Processor) Object file to be programmed Object in ELF or SREC format Hardware instance of flash memory Base address, size, and data width

46 **slide Flash Writer Utility (MicroBlaze Processor) Object file to be programmed Object in ELF or SREC format Hardware instance of flash memory Base address, size, and data width automatically determined from hardware platform specification Storage offset from beginning of flash memory Programming scratchpad RAM is required Software Boot and PL Configuration - 46 Copyright 2014 Xilinx 40362

48 48 Apply Your Knowledge 1. Where are the different places in which a user application can reside and when will you use them? 2. What is the Flash Programmer utility? What are some of the requirements? Software Boot and PL Configuration - 48 Copyright 2014 Xilinx 40362

49 **slide Summary SDK supports various mechanisms for initializing an application. The choice depends on the size of the application, how it will be stored, and the memory technology environment in which it will execute FSBL application provided in SDK features PS boot PL configuration SDK provides a Flash Programmer utility that you can use to program flash devices SDK provides a sample bootloader software application project Software Boot and PL Configuration - 49 Copyright 2014 Xilinx 40362

50 **slide Lab 6: Boot Loading from Flash Memory (Zynq All Programmable SoC) Introduction The lab illustrates the steps involved in booting an application from QSPI flash Objectives Open the Vivado Design Suite project and re-configure to Zynq All Programmable SoC PS settings Export to SDK and launch the software project Create a Zynq All Programmable SoC boot image file using the ELF and BIT files Program the flash by copying the MCS file to flash Boot the system by loading the actual application stored in flash Software Boot and PL Configuration - 50 Copyright 2014 Xilinx 40362

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2/80 2 2/80 2 3/80 3 DSP2400 is a high performance Digital Signal Processor (DSP) designed and developed by author s laboratory. It is designed for multimedia and wireless application. To develop application