DE0_SOPC_05_2010
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1 DE0 软硬件硬件协同设计 杨志方武汉工程大工程大学 1
2 课程目程目标 : 让学员可以 快速设计 SOPC 硬件系统 设计 SOPC C/C++ 软件系统 学员基础需求 : -Quartus II 基本操作与基本 Verilog 概念 -C Programming 基本概念 2
3 Development Tools HW: Quartus II + SOPC Builder SW: NIOS II IDE 3 3
4 Basic Development Flow Quartus II <User RTL Code> + SOPC Builder <System RTL Code> FPGA Board NIOS II IDE <C/C++ Program> 4 4
5 硬件开发开发流程 Quartus II Development Flow New Project (.qpf) SOPC Builder Add Processor Add Controllers Component Connect Code Generate (.v) Top Design (.v) Pin Assignment (.qsf) Compile (.sof).ptf 硬件描述文件 FPGA Board 软件开发开发流程 NIOS II IDE New Project Project Configure Coding (.c/.cpp) Compile/Linker HAL & system.h Execute Code (.elf) 5 5
6 PART 1-A: Hardware Design by SOPC Builder Tool User Guide SOPC-Builder IP 6
7 SOPC Builder SOPC: System On a Programmable Chip Quartus 附属工具之一 图形操作接口, 可快速 ( 几分钟!) 建立自定制 SOPC 内建 60 个以上的 IP, 含 Processor 自动产生 SOC 的 RTL code 7 7
8 Examples System 8 8
9 System On Board 9 9
10 Component Connections Memory-Mapped IF. Master & Slave Ports Streaming IF. Source & Sink Ports 1010
11 Slave Interface Signal Example Basic Write Transfer 1111
12 Streaming Interface Signal Example 1212
13 SOPC Builder 人机界面 1313
14 System Example P.S. CPU 不是必要的 1414
15 SOPC-Builder Operation New/Open SOPC Project Clock Settings Add/Remove/Enable/Disable Components Rename/Edit Component Component Clock Setting Add/Remove Connections Address/IRQ Assignment Arbitration Value Setting Generate System RTL Code 15
16 New/Open SOPC Project System Name (DE0_SOPC): Top filename of system RTL code (For Quartus) PTF (For NIOS II IDE) 1616
17 Clock Setting 外部 Import 的 Clock 与 SOPC 内部 PLL 产 出的 Clock 会显示于 Clock Setting 窗口 Add/Remove imported Clock ( 至少 1 个 ) Edit Clock Name & Value (import only) 1717
18 Add Component 于左方选择 IP, 然后按 ADD (or doubel click 该 IP) 即可将 component 加入 SOPC 加入前, 会有一个设定窗口询问组件相关设定 1818
19 Remove Component 以鼠标点选 component, 然后按 keyboard Delete, 立即删除该组件 1919
20 Enable/Disable Component 将鼠标移到组件左侧的 Check Box, 做点选, 可立即 Enable/Disable Component 2020
21 Rename Component 将鼠标移到该 Component, 按鼠标右键, 跳 出选单, 并选 Rename 2121
22 Edit Component ( 修改参数 ) 将鼠标移到该 Component, 按鼠标右键, 跳 出菜单, 并选 Edit (or double click 该 component) 2222
23 Component Clock Setting 鼠标点选 Component 右方的 Clock 下拉选单 并选取 Clock 2323
24 Add/Remove Connections 将鼠标移到 Slave 组件左端的 connection 点, 按鼠标左键, 可立即 connect/disconnect master-slave 之间的 connection ( 实心圆表示 connected) 2424
25 Address Assignment 目的 : Slave Address 不可重叠 方法 : Auto Assignment Manual Assignment 2525
26 IRQ Assignment 目的 : Slave IRQ Number 不可重叠 方法 : Auto Assignment Manual Assignment 2626
27 Generate System RTL Code 2727
28 Output File Verilog (or HDL) File for System. Top filename DE0_SOPC.v PTF File: 使用于建立 NIOS II C/C++ project 2828
29 Integrate SOPC Sub-System Into top level design in Quartus II using either HDL code or schematic entry tool SOPC Builder Logic 2929
30 Verilog Instantiation in Top 3030
31 SOPC-Builder IP NIOS II Processor On-Chip Memory JTAG-UART System ID 31
32 NIOS II Processor Altera s 第二代 Soft-Core 32 Bit RISC Microprocessor Harvard Architecture 支持所有 Altera FPGA 3232
33 NIOS II Processor Block Diagram 3333
34 NIOS II Version 3434
35 NIOS II Clock(1) 3535
36 NIOS II Clock(2) 3636
37 CPU Core 3737
38 CPU Reset/Exception Vector 3838
39 CPU Cache 3939
40 On-Chip Memory Embedded to.sof Step: 1. Build SOPC 2. Build NIOS 3. Build Quartus 4040
41 JTAG-UART Block Diagram 4141
42 JTAG-UART IP 4242
43 System ID rename: sysid 4343
44 LAB 1-A Hello Program Hardware 1_NIOS_HELLO 44
45 Create Quartus Project 4545
46 Create NIOS Project 4646
47 Empty SOPC 4747
48 Rename Clock 4848
49 ADD: NIOS II Processor 4949
50 ADD: JTAG-UART 5050
51 ADD: On-Chip Memory 5151
52 ADD: System ID 5252
53 Rename Component 5353
54 Hello SOPC System 5454
55 Auto Base Address 5555
56 Edit Component 5656
57 Reset/Exception Vector 5757
58 Valid SOPC Design 5858
59 Generate SOPC 5959
60 Exit SOPC Builder 6060
61 Create Quartus Top 6161
62 Edit Quartus Top 6262
63 Save Quartus Top 6363
64 Pin Assignment 6464
65 Create Timing Constrain File 6565
66 Edit Timing Constrain File 6666
67 Save Timing Constrain File 6767
68 Timing Analysis Setting 6868
69 Compile and Download.SOF 6969
70 PART 1-B Software Design by NIOS II IDE NIOS II IDE Users Guide Programming Guide 70
71 NIOS II IDE NIOS II C/C++ 整合开发环境 Editor/Compile/Linker/Loader Debug Break Point C/C++ Trace C/C++ 变数 Inspect 根据硬件描述文件.PTF, 自动产生 IP 对应之 Driver, HAL API, Standard C Library System.h, 定义硬件组件地址, 名称, IRQ 等信息 7171
72 Software Support OS None (single-thread) MicroC/OS-II Software Component Standard C Library TCP/IP Stack Zip Read-Only File System Host Based File System 7272
73 NIOS II System Software Stack User Generated NIOS II IDE Generated SOPC Generated 7373
74 NIOS II System Boot Sequence CRT0.S RESET Initialise caches, BSS, stack pointer, global pointer alt_main Initialize interrupt system and setup call to main alt_sys_init Initialize HAL devices main() Application Code 7474
75 NIOS II IDE 人机界面 (C/C++) 7575
76 启动 NIOS II IDE 从 SOPC Builder 选单 从 Windows Start 选单 7676
77 Switch Workspace 若该 workspace 有之前建立的 project, 该 project 会被开启 7777
78 New C/C++ Application Project 7878
79 Project Setting 7979
80 Hello Project 8080
81 System Library Project Properties 8181
82 Memory Partitioning 8282
83 Library/Driver Setting 8383
84 Software Compilation Compile status 会出现于 console window 8484
85 Compile & Run Run 之前要记得先下载.sof 第一次 run, 会要求设定硬件 8585
86 硬件设定 (JTAG Cable) 8686
87 Compile & Debug Debug 会停在 main 的第一个执行行 8787
88 Debug Mode 人机界面 8888
89 Trace Command 8989
90 查看变量值 也可以从变量窗口直接察看 9090
91 回到 C/C++ Mode 人机界面 9191
92 Flash Programming 9292
93 NIOS II Programming 93
94 Header File system.h stdio.h; stdlib.h alt_types.h io.h; altera_avalon_pio_regs.h sys/alt_irq.h sys/alt_alarm.h; sys/alt_timestamp.h unistd.h 9494
95 alt_types.h: Altera Data Type alt_32: singed 32-bit integer alt_u32: unsigned 32-bit integer alt_16: singed 16-bit integer alt_u16: unsigned 16-bit integer alt_8: singed 8-bit integer alt_u8: unsigned 8-bit integer 9595
96 SYSTEM.H System.h
97 SYSTEM.H Location 9797
98 SYSTEM.H SOPC Builder 9898
99 Access Hardware Access Memory: Pointer (Data Cache Enabled) Access Device Register: IORD, IOWR (Data Cache Disabled) Access by HAL API: open, write, read, close (and fcntl) alt_xxx 9999
100 Printf Example #include <stdio.h> int main() { printf("hello from Nios II!\n"); return 0; } 100
101 Reference Quartus Handbook Volume 4: SOPC Builder Volume 5: Embedded Peripherals NIOS II Software Developer s Handbook
102 LAB 1-B Hello Program Software 1_NIOS_HELLO 102
103 Select Workspace 103
104 Create NIOS II Project 104
105 NIOS II Project Setting 105
106 Create system library 106
107 Hello Project 107
108 Execute Hello Project 108
109 Compile, Error 109
110 Project Property Setting 110
111 Compile Success 111
112 Hello Execute Switch 切到 Run Mode.SOF 要先下载 下载.ELF Console Window: 112
113 Result 113
114 Part 2 More SOPC IP PIO Timer UART 16x2 Character LCD 114
115 PIO Block Diagram (Bi-direction) 115
116 PIO - LED/SEG7 116
117 PIO - KEY/SWITCH 117
118 PIO - KEY/SWITCH Interrupt 118
119 Timer IP 119
120 UART-IP Block Diagram 120
121 UART IP 121
122 Character LCD Block Diagram 122
123 Character LCD IP 123
124 LED 闪烁 PIO-LED Example Void test1_led(void){ alt_u32 led_mask=0; while(1){ // green led control IOWR_ALTERA_AVALON_PIO_DATA( LED_BASE, led_mask); // toggle led led_mask ^= 0xFFFFFFFF; // sleep 0.2 second usleep(200*1000); } // while } // LED_BASE defined in system.h 124
125 PIO-SWITCH Example Switch 状态显示 Void test2_switch(void){ alt_u32 mask; while(1){ // (switch up) active-high mask =IORD_ALTERA_AVALON_PIO_DATA(SWITCH_BASE); // high-active IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE, mask); } } 125
126 PIO: Software Hardware 126
127 Time Measurement Timer Example void test_timer(void){ alt_u32 time_start, time_elapsed, ticks_per_second; // check hardware ticks_per_second =alt_ticks_per_second(); if (ticks_per_second == 0){ printf("timer hardware not works well\n"); return; } // measure time time_start =alt_nticks(); usleep(1*1000*1000); // sleep 1 second time_elapsed =alt_nticks()- time_start; printf("[timer test]time elapsed:%.3f seconds\n", (float)time_elapsed/(float)ticks_per_second); } 127
128 Character LCD Example Display Hello in LCD void lcd_test(void){ char szhello[] = "Hello\nI am Richard"; static FILE *lcd; } //===== lcd display lcd =fopen(lcd_name, "w"); if (!lcd){ printf("failed to open LCD driver\n"); }else{ fwrite(szhello, strlen(szhello), 1, lcd); } 128
129 Lab 2 PIO Timer 16x2 Character LCD 129
130 Add: LED PIO 130
131 Add: Key PIO 131
132 Add: Switch PIO 132
133 Add: Timer 133
134 Add: Character LCD 134
135 Finished SOPC Auto-Assign Address/IRQ, Rename 135
136 Instantiation in Quartus TOP 136
137 System Library Properties 137
138 LED Control // LED is high-active void test_led(void){ alt_u32 led_mask = 0x01; alt_u8 right_to_left = 1; const alt_u32 left_boundary = 0x01 << (LED_DATA_WIDTH-1); const alt_u32 right_boundary = 0x01; while(1){ IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE, led_mask); if (right_to_left){ if (led_mask == left_boundary) right_to_left = 0; else led_mask <<= 1; }else{ if (led_mask == right_boundary) right_to_left = 1; else led_mask >>= 1; } usleep(200*1000); // 0.2 second } } 138
139 KEY Control // Key: active-low // Switch: up-high void test_led_key(void){ alt_u8 led_mask, key_mask, switch_mask; } while(1){ key_mask = ~IORD_ALTERA_AVALON_PIO_DATA(KEY_BASE) & 0x7; switch_mask = IORD_ALTERA_AVALON_PIO_DATA(SWITCH_BASE) & 0x7F; led_mask = key_mask (switch_mask << 3); IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE, led_mask); } 139
140 KEY-Interrupt Control 140
141 LCD Control 141
142 Part 3 PLL and SOPC Memory IP PLL SDRAM EPCS Flash Tristate Bridge 142
143 FLASH 143
144 Tristate Bridge Connect FLASH 144
145 SDRAM Block Diagram 注意 Control Clock & SDRAM Clock 145
146 SDRAM IP 146
147 PLL for SDRAM Clock Phase 147
148 Data Memory Access SDRAM: 以 pointer Read/Write Flash Read: 以 pointer Read Flash Write/Erase/Info.: System API ECPS Read/Write: System API 148
149 Lab 3 Memory SDRAM Tristate Bridge Flash 149
150 Add: PLL 150
151 PLL Input clk c0 151
152 PLL Output clk c0 152
153 PLL Output clk c1 153
154 PLL Finish 154
155 Clock Rename 155
156 Add: SDRAM 156
157 SDRAM Timing 157
158 Component Clock Setting 158
159 Add: Tristate Bridge 159
160 Add: FLASH 160
161 FLASH Timing 161
162 Finished SOPC 162
163 Instantiation in Quartus Top 163
164 Boot From FLASH 164
165 SDRAM Test 165
166 Run Program on SDRAM 166
167 Query Flash Size 167
168 Boot Your Application From FLASH Download.SOF Flash Programming 168
169 Flash Programming 169
170 Part 4 Custom SOPC Component 170
171 SEG7 Custom SOPC Component (Quartus 9.1) New SOPC Component Procedures: 1. Prepare HDL File 2. New Component Input HDL File Specify Signal Specify Interface Specify Information 3. Add Component to your SOPC 171
172 LAB 4 Custom SOPC Component SEG7 172
173 SEG7 HDL File HDL Code 要放在 Quartus Project 下的 ip 目录 173
174 Launch New Component Wizard 174
175 Import HDL File 175
176 Specify Signal 176
177 Specify Interface 移除多余的 interface 设定 Interface 对应之 Clock 177
178 Component Information 178
179 MY SOPC Component Available 179
180 SOPC Including SRAM 180
181 SEG7 Driver 181
182 Test SEG7 int test_seg7 { int i; for(i = 0; i!= 100; i++) { usleep(1 * 1000 * 1000); SEG7_Hex(i, 0x10); } } 182
183 Part 5 SDCARD Case Study Controller Driver 183
184 SDCARD Driver Based on NIOS II 以 PIO Controller 来驱动 SDCARD Pin: CMD(inout) DAT(inout) CLK(output) PIO Controller 由 NIOS II 来控制 产生 CLK (sdcard protocol 的 clock) Pin Direction Input: 读取来自 SDCARD DAT & CMD 上的讯号 Output: 输出 DAT & CMD 讯号至 SDCARD 184
185 SDCARD - SOPC 185
186 SDCARD - Driver 186
187 Lab 5 Execute SDCARD Example 187
188 THANK YOU! 188
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