(91 _ (91 91 1 7 A08-91A E-mail : mail@mail.cycu.edu.tw / / (03456789-111 0912345678 (034567890 E-mail : d12345@cycu.edu.tw 1. 2. E-mail E-mail Research and design on phase locked loops for clock generator _ (a0.5um 2P2M CMOS _ (b0.18um 1P6M CMOS(_ TSMC I/O pad _ (c0.25um 1P5M CMOS( _ Artisn Cell Library, _ TSMC I/O pad _ (d0.35um 1P4M Silicide ( _ Avant! Cell Library, _ TSMC I/O pad (e0.35um 3P3M SiGe BiCMOS (a (b (c (1:(a(b CIC 2 cell-library( I/O pad 1.5 x 1.5 (mm 2 /(mm 2 /28 S/B =[ x + 8 x ]( ( ( IC No./ / ( CIC 1. U05-90D-#09 / / Partial Work 2. U05-90C-#20 / / Work 3. S35-90J-#02 /, / ( 1. 000069 ( CIC 2. : : pll.db : pll.sum _pll.lvs (*.SUM, *.LVS Apollo : 3. : pll.doc (Word-Format, 4. ftp CIC / S35-SiGe/03 5. ( CIC ** ( CIC CIC
(Phase Locked Loops, PLL PLL (Chipset PLL GHz 6M Hz 96M USB2.0 USB2.1 6M Hz [1][2]
PFD, Phase Frequency Detector Charge Pump Loop Filter (Voltage Controlled Oscillator (Divider 1 Divider(1/16 Phase Frequency Detector Charge Pump Voltage Controlled Oscillator Loop Filiter 1 PFD[4]CP VCO Divider[5] A 2
BCharge Pump 3 Charge Pump C 4 Voltage Controlled Oscillator D 5 Voltage Controlled Oscillator
HSPICE Transistor Level (Pre Simulation Cadence Tools (Post Simulation (Dead Zone Charge Pump 6 PFDCharge Pump + LP 7 PFDCharge PumpLP
5mV 6.5mV 2ns 8 (1 13µs (Lock-in Time13µs post-simulation 13µs Damping 20µs
9 (2 10 (3
11 (4 2.7V ~ 3.3V 100 M Hz 75 M Hz ~ 125 M Hz 1.0V ~ 2.0V 50M Hz/V 16 0.742 1.23 M Hz Lock-In Time 15 µs (Vdd=3.0V 10 mw (Jitter 400 ps Input Level Output Level TTL TTL No. of Output 4 t(phase error Max t(phase errormin 200 ps -200 ps
i. Function Generator 6M Hz DN ii. iii. UP OUT Lock-In Time Long-tern JitterShort-tern Jitter 100M Hz 12M RF I/O PAD Pd TFTR 150M Hz (Dead Zone Nature Frequency [1] Floyd M. Gardner, Charge-Pump Phase-Lock loops, IEEE Transaction On Communication, Vol. COM-28, pp. 1849-1858, November 1980 [2] Mark Van Paemel, Analysis of a Charge-Pump PLL : A New Model, IEEE Transaction On Communication, Vol. 42, No. 6, pp. 2490-2498, July 1994 [3] Ian A. Young,and Jeffrey K. Greason, and Keng L. Wong, A PLL Clock Generator with 5 to 100M Hz of Lock Range for Microprocessor, IEEE Journal of Solid State Circuit, Vol. SC-27, No.11, pp.1599-1607, November 1992 [4] Henrik O.Johansson, A Simple Precharged CMOS Phase Frequency Detector, IEEE Journal of Solid State Circuit, Vol. 33, No.2, pp. 295-299, February 1998 [5] Behzad Razavi, Design of Monolithic Phase-Locked Loops and Clock Recovery Circuit A Tutorial, Monolithic Phase-Locked Loops and Recovery Circuit, A Select Reprint Volume IEEE Solid-State Circuit Council, Sponsor, 1996
1. DRC : ---------------------------- OUTPUT CELL SUMMARY ----------------------------- CELL-NAME LAYER # ---------- W I N D O W ---------- DATATYPE # OF POLYGONS TEXTS (LINE SEGMENTS COB159 59/ 0 4.10 4.10 1555.90 1473.90 354959 0 pad error LATI364 64/ 0 823.90 412.85 1159.60 953.65 56 0 MOS OUTDISK PRIMARY CELL : OUTCHIP1 WINDOW : 4.10 4.10 1555.90 1473.90 ENDED AT TIME =14:01:22 DATE =28-DEC-2000 2. LVS : Dracula LVS pll.lvs FTP CIC MATCH
CAD DATA BASE MT INFORMATION 0.35um 3P3M SiGe( CUSTOMER : CONTACT ENG : DATE : 91/01/07 TEL. EXT. : (034567890-1111 MOBILE PHONE : 0912345678 TAPE NO. : 1. SEAL RING TSMC HAS TO ADD SEAL RING (VTSMC STANDARD ( CUSTOMER S SEAL RING : CUSTOMER ADDED SEAL RING ALREADY ( TSMC STANDARD ( CUSTOMER S SEAL RING 2.DATA TRANSFER BY : ( PHYSICAL TAPE SEND TO ( TAIWAN (VNETWORK FILE PATH AND NAME : S35-SiGe / 03 / pll.gds 3. WINDOW DESCRIPTION ( Layout DEVICE NAME WINDOW SIZE CAD DATA BASE WINDOW COORDINATES X= 1500 UM X_LB Y_LB X_RT Y_RT Y= 1500 UM 0 0 1500 1500 4. CAD DATA BASE DESCRIPTION 5. SHRINK & ORIENTATION PROECSS LAYER ID CKT PATTERN PROCESS KEY DATA TONE MIN. GRID DATA SHRINKAGE EBEAM SHRINKAGE CAD LEVEL CAD LEVEL TO 100 % TO 100 % NPLUSBL(138 179 - C 0.025 um (V 1X DATA ROTATE DIFF (120 3 - D 0.025 um ( 5X BASE BY TSMC DT(123 171 - C 0.025 um SINKER(102 181 - C 0.025 um ORIEN- (VNO PWELL (191 ** - D 0.025 um TATION F ( 90 DEGREE NWELL (192 2 - C 0.025 um ( 270 DEGREE RB(112 173 - D 0.025 um ( OTHER POLY1(130 13 - D 0.025 um PLDD(113 140 - C 0.025 um SB(137 105 - D 0.025 um LC(136 174 - C 0.025 um HS(126 175 - C 0.025 um BJTW(109 182 - C 0.025 um EMW(103 186 - C 0.025 um EPOLY(144 9 - D 0.025 um BPOLY(143 10 - D 0.025 um NIMP(198 8 - C 0.025 um PIMP(197 7 - C 0.025 um VARJIMP(122 176 - C 0.025 um CONT(156 15 - C 0.025 um METAL1 (160 16 - D 0.025 um VIA12 (178 17 - C 0.025 um CYM(182 67 - D 0.025 um METAL2 (180 18 - D 0.025 um VIA23 (179 27 - C 0.025 um METAL3 (181 28 - D 0.025 um PAD(107 19 - C 0.025 um RPO(155 34 - D 0.025 um NEPI N/A - C 0.025 um N_CELL N/A - D 0.025 um ** P-well (191 is reverse tone of N-well (192 7. SPECIAL DESCRIPTION * ROTATE BY COUNTER CLOCKWISE 6. FORMAT DESCRIPTION A. CALMA GDS-II FORMAT STRUCTURE NAME(top-cell name pll B. CALTECH CIF FORMAT (VERSION 2.0 CELL NAME
*** Chip Features CAD Tools *** CKT name : ( HSPICE Technology : 0.35um 3P3M SiGe BiCMOS( OPUS Package : 28 DIP ( Chip Size : 1.5 * 1.5 mm 2 ( mm 2 Transistor/Gate Count : 10CP / 6R / 630 MOS ( / Power Dissipation : 10mW ( mw Max. Frequency : 150Mz ( MHz Testing Results : function work partial work fail 25 vc 24 vco_ou 23 vco_ou 22 VDD 21 vco_ou 20 vco_ou 19 vco_ou 26 pllv2_v 27 pllv2_v 28 pllv1_o 1 pllv1_o 2 pllv1_o 3 pllv1_o 4 pllv1_r 18 pfd_ref 17 pfd_vc 16 pfd_vc 15 pllv2_r 14 pllv2_o 13 pllv2_o 12 pllv2_o 7 GND 11 pllv2_o
Side Braze 28L inner lead (Empty drawing 11 4 4 1 28 18 25
Tapeout review form tapeout,,, Tapeout Review Form, 1. 1-1. : 1-2. : A07-91A 1-3. : 3.3V 1-4. : 150 MHz 1-5. : 10 mw 1-6.?(2-1 (1-6-1 1-6-1. work performance? driving,,, 1-6-2.? 2. 2-1. +/-10%? SS,,TT,,FF 2-2.? 0~50 2-3.?,, +/-10% 2-4. IO PADBonding wire? yes. EM post layout simulation? yes HSPICE 3. Power Line 3-1. Power Line? 20um 3-2. power line current density? yes 3-3. Metal Line? yes 4. DRC,LVS 4-1. whole chip DRC LVS? yes 4-2. LVS,PIN match? yes match? 4-3. PAD PAD? 5. MT Form 5-1.? yes? yes (? yes? yes 5-2. (0,0? 5-3.? yes window size? yes 5-4.Layout layers GDS2 number? yes N/A 5-5. top cell name? yes 6. RF/MMIC 6-1? 6-2 6-3 (? 6-4 chip block (chip,? 6-5
6-5-1.? 8-5-2 via hole? 8-5-3? 8-5-4? 8-5-5 PAD? 8-5-6 PAD Bond-wire? 8-5-7 8-5-8 MIM design manual layout 8-5-9 donut shape layout 6-6 DRC,, PAD MOS DRC error 6-7 LVS,, LVS 6-8 on wafer, on PCB or in package? chip 28pin : :