/ http://www.cic.org.tw/login/login.jsp CIC Package Design with Allegro APD 104 IC 104 T50UHV Introduction to Conversational French - Syllabus Summer 2004 1
14 2 12 CMOS MorSensorMorFPGA DUO MorSensor 2
104 2 26 7 MorSensor8 3
Package Design with Allegro APD PCB IC Bare Die PCB PCB PCB IC PCBIC IC PCB PCB Cadence Allegro Package Designer Allegro APDPCB PCB Allegro APD PCB PCBBGA Package Symbol Bare Die Package Symbol Bare Die Wire Bond PCB PCB PCB Bare Die Wire BondPCB PCB PCB BGA Package Symbol PCB Allegro APD Allegro Allegro APD PCB BGA Package Symbol 1 PCB Allegro APDPCBSetup->CrosssectionPCB 4
TOP_COND VDD VSS BOT_CONDPCB WIREBOND PCB PCB Package Symbols TOP_CONDBare Die Package Symbol WIREBOND Bare Die Wire Bond PCB 2 BGA Package Symbol PCBBGA Package Symbol BGA Package Symbol BGA Symbol Add->BGA->BGA Generator Next BGA Package Symbol Pin Symbol BGA 26 x 26399 pins Symbol35mm x 35mm Pin Pitch 1.27mm Outer rings4 Core columns Core rows 66 x 6 pin Next BGA Package Symbol Signal Power Pin Signal pins 4/6 236 pins Power Ground Next BGA Pin 5
BGA Pin Next PCB BGA Package Symbol Pin Arrangement Pin Use Ratios Pin Numbering BGA Package Symbol Bare Die Package Symbol BGA Package Symbol Bare Die Package Symbol 1 Bare Die PAD Bare Die Package SymbolBare Die Layout PAD PAD Bare Die Layout PAD PAD 2 Bare Die Package Symbol Bare Die PAD Add->Standard Die->Die Text- 6
in WizardPAD PAD PAD Next Next File: C:/ D1_data.txt Date: Thu Sep 07 14:01:53 2006 Units: microns, 2 decimal places Name: DIE9600X9600 DEF Design: D1 RefDes: D1 DieType: Wirebond DieOrient: ChipUp Origin: (0.00 0.00) Rotation: 0.000 Extents: ((-5902.96-5903.98) (5902.96 5903.98)) Pin Number Padstack X Coord Y Coord Rotation Pin Use Net Name 1 DIE_PAD -5392.42-5863.34 0.000 IN VSS 2 DIE_PAD -5280.15-5863.34 0.000 IN VDD 3 DIE_PAD -5167.88-5863.34 0.000 IN BUS_DATA_SENSE_14_ 4 DIE_PAD -5055.62-5863.34 0.000 IN BUS_DATA_SENSE_12_ 5 DIE_PAD -4943.35-5863.34 0.000 IN BUS_DATA_SENSE_17_ 6 DIE_PAD -4831.08-5863.34 0.000 IN BUS_DATA_SENSE_15_ Bare Die PAD Fie Information Pin Information Bare Die Package Pad 60um x 60umPAD Next Next Bare Die Package Symbol 7
Padstack Information Package Information Bare Die Symbol Wire Bond Package Symbols Wire Bond Bare Die Package Pad Wire Bond PCB 1 Bare Die Package Symbol Power Rings Bare Die Power Ground PAD Bare Die Package Symbol Power Rings Power Rings Bare Die Fingers Bond Wires Power Rings Power Rings Power RingsRoute->Power/Ground Ring Generator Power Rings Number of Rings 2 2 Power ringsnext Power Ring Ring 8
P o w e r R i n g T O P _ C O N D L a y- ertop_condpower RingVSS Net VSS Next Power Ring Power Ring TOP_COND Layer TOP_COND Power RingVDD Net VDD NextPower Rings Ring count First Ring Second Ring <2> Guide Paths Wire Bond Wire Bond Bare Die Package Symbol Guide PathsRoute->Wire Bond->Add/Edit Guide Paths Die Package Symbol Add Guide C r e a t e g u i d e p a- th(s) Power Rings Guide Paths 9
Guide Paths Setting Guide Pahts <3>Wire Bond Constraints Guide Paths Wire Bond Wire Bond Bond Wire Bond Wire Fingers Route->Wire Bond->Settings View/Edit wire profilesbond Wire Feasibility modeview wire Bond constraintsbond Wire Fingers Constraints OK Wire Bond Settings 10
Wire Profile Editor Global Wire Bond Constraints <4>Wire Bond Wire Bond Route->Wire Bond->Add Bare Die Package SymbolWire Bond Package Pad Finger A d d BF300x90 Finger 300um x 90um OK Wire Bond Bare Die Pad Guide Paths Wire BondWired Bond Wire Bond Padstack Information 11
Wire Bond Complete PCB Wire Bond Die Package Symbol BGA Package SymbolPCB Layout 1 Auto Assign Net Logic->Auto Assign Net Automatic Net Assignment S o u r c e D i e D e s t i n a t i o n Package Assign new connections Ok Die BGA Package Symbols PCB Layout <2> Auto Assign Net PCB Layout Allegro APD Route->Spider RouterPackage Routing Parameters OK Allegro APD Die BGA Package Symbols 12
PCB Layout <3> PCB Layout Gerber PCBPCB 4 Wire Bond PCB Bare Die Allegro APD DXF File->Export->DXF DXF output file Layer conversion fileedit Select all Use layer names generated from class and subclass namesmap OK Layer Mapping DXF Exportdie.dxf die_l.cnv 13
DXF Out Conversion File PCB PCB PCB ICBare Die PCB IC PCB [1] Cadence http://www.cadence.com [2] Allegro Package Designer v16.6, Cadence Training Courses. 14
IC 102IC IC IC IC IC IC IC 104 IC 3/11 104/03/11 IC http:// www.cic.org.tw/icdesign 104/03/20~ 104/04/10 1. 2. (1) (2) 3. E-mail 104/04/20~ 104/05/01 1. 2. 3. 15
104/05/02( ) 1. 2B 2. 3. 104/06/05 104/06/22 104/07/06 http://www.cic.org.tw/icdesign 03-5773693*22503-5774064 icdesign@cic.narl.org.tw 300 26 7 IC 16
104 T50UHV TSMC 0.50 UM CMOS High Voltage Mixed Signal Based LDMOS Al_USG Polycide 2P3M 5/20/450/600/700/800V T50UHV 104 5 CMOS 5V 20~60V 400~800V 1. CMOSPIP capacitor Schottky and Zener diodes 450/600/700/800V MOSFET 2. N+ Isolation ring HV Junction Termination 3. T50UHV https://www.cic.org.tw/fab_services/index.jsp?menu=aet 4. EDA Cloud LAKERVirtuoso IC Layout Cloud PDK T50UHV-104A 2015/04/27 2015/05/04 2015/05/11 06-2087971 ext. 215 E-Mail cfsu@narlabs.org.tw 17