The BIST Scheme for Digital-to Analog converters
. :... 03.DAC :... 05. :... 08 ( ) :... 08 ( ) :... 08. :... ( ) OP AMP... ( ) Charge Pump Circuit... 3 ( ) Analog Summer Circuit... 4 ( ) CMOS Schmitt trigger Circuit... 5 ( ) The OP-Amp Integrator... 6. :... 8 ( ) OP AMP... 8 ( ) Charge Pump Circuit... 9 ( ) The OP-Amp Integrator Circuit... 0 ( ) CMOS Schmitt trigger Circuit.... :... :... 3
Fig.. Integral nonlinearity of the DAC... 5 Fig.. Differential nonlinearity of the DAC... 6 Fig..3 Offset error of the DAC... 6 Fig..4 Gain error of a DAC... 7 Fig.3. Configuration of the proposed BIST architecture... 8 Fig.3. BIST Circuit... 9 Fig.3.3 The analyzed waveforms at nodes,4 and 7 of BIST circuit... 0 Fig.3.4 Linear relationship between A and TH... Fig.4. The Basic OP AMP... Fig.4. (a) The detailed circuit of the Charge Pump... 3 Fig.4. (b) Heap Pump... 3 Fig.4.3 Configuration of analog summer... 4 Fig.4.4 The redesigned CMOS Schmitt trigger Circuit... 5 Fig.4.5 The OP-AMP Integrator Circuit... 6 Fig.5. OP AMP... 8 Fig.5. Charge Pump Circuit... 9 Fig.5.3 The OP AMP Integrator... 0 Fig.5.4 The CMOS Schmitt trigger Circuit... 3
. : LSI( ) analog/mixed circuits (analog/mixed circuits) (built-in self-test. BIST) BIST (Digital-to-Analog converter. DAC) BIST DAC BIST DAC DAC DC clock feed through DAC INL(Integral nonlinearity) [3] INL(Integral nonlinearity) BIST 4
DACs ADCs 5% LSB linear ramp generator linear ramp DACs ADCs BIST DAC OP DAC BIST [] OP AMP CMOS Schmitt rigger Charge Pump Analog summer OP ICFB BIST DAC ( ) BIST BIST 5
.DAC : INL (Integral nonlinearity) DNL(Differential nonlinearity) offset- error Gain-error ( ) Integral nonlinearity: Fig.. Integral nonlinearity(inl) error of a DAC. Integral nonlinearity offset error gain error best straight line nonlinearity best-fit straight line 6
( ) Differential nonlinearity: Fig.. Differential nonlinearity (DNL) error of a DAC. DAC LSB DNL error LSB DNL ( ) Offset- error: Fig..3 Offset error of the DAC. 7
DAC Offset error E 0 0 off E = off ( DAC ) LSB 0...0 ( ) Gain-error Fig..4 Gain error of a DAC. Gain error Offset error 0 DAC gain error E gain(dac) LSB E N ( ) gain( DAC) = LSB... LSB 0...0 8
. : ( ) Fig.3. Configuration of the proposed BIST architecture. (analog summer circuit) DAC analog summer circuit CMOS Schmitt trigger DAC ( ). : BIST Fig.3. analog summer DAC 9
analog summer CMOS Schmitt trigger Fig.3. BIST circuit BIST linearity system ( ) analog summer ( ) charge pump integrator CMOS Schmitt trigger DAC DAC 0
A cm A Schmitt trigger (duty cycle) Fig.3 BIST 4 TH T H A 7 Fig.3.3 The analyzed waveforms at nodes,4 and 7 of BIST circuit A A TH A T H = 0 A = a b b 4 DD DD DD ref b A...()
DD b DD b DD ref + + I I I b a = = I C T L H P ) ( =...() ) ( ) ( ) ( ) ( 4 4 = L H a b H L L H a b P H T T () () )...(3 + = L H a ref P H A T T ref L H b a L H L H b a ref + + (3) H T A Fig.3.4 Linear relationship between A and TH
. : ( ) OP AMP Fig.4. The basic OP AMP CMOS OP LSI CMOS OP LSI CMOS OP (pf) OP Two-stage OP AMP ± 5 OP AMP 5 nmos 3 pmos OP AMP 4000 BW=MHZ 3
( ) Charge pump: Fig.4. (a) The detailed circuit of the charge pump Single Clock Charge Pump [5] 90% Fig.4.(a) Charge Pump Fig.4. (b) Heap Pump 4
ψ= M ON M P3 OFF G(MP) M P ON DD C P DD ψ=0 M OFF M P3 ON G(MP) M P OFF i CP CP = DD O = DD ( ) Analog summer: Fig.4.3 Configuration of analog summer analog summer 5
analog summer i.e. A DAC DAC dc ( ) CMOS Schmitt trigger: Fig.4.4 The redesigned CMOS Schmitt trigger circuit CMOS Schmitt trigger PMOS NMOS 6
Schmitt trigger BIST [] T T M3 M4 M5 M6 T > T < T M off M in T T M M in off 0 X DD > T M DD in in 0 M DD in T = T T + T T ( ) The OP-Amp Integrator Fig.4.5 The OP-Amp Integrator 7
OP AMP 0 0 plus 8
. : BIST BIST BIST ( ) OP AMP Fig.5. OP AMP Fig.4. OP AMP OP AMP OP OP AMP (voltage-follower ) (close loop gain ) A CL( F ) = 9
( ) Charge Pump Circuit Fig.5. Charge Pump Circuit Fig.4.(a) Charge pump DD 5 5 Charge pump 0
( ) The OP-Amp Integrator Fg.5.3 The OP AMP Integrator I C = I in 0 OP AMP 0 ( 5 ) 5-5 0 0 t = C i in
( ) CMOS Schmitt trigger Circuit Fg.5.4 The CMOS Schmitt trigger Circuit Fig.4.4 Schmitt trigger DC 00HZ ~ 0MHZ 5
. : BIST DAC BIST DAC SOC 3
: [] A New BIST Scheme Fro Digital-to-Analog converters [] Daejeong Kim, Joongsik Hih, and WonChan Kim, A New waveform-eshaping Circuit: An Alternative Approach to Schmitt Trigger 993 [3] Mark Burns and Gordon W. oberts, An Introduction to Mixed-signal IC Test and Measurement, ISBN: 0-9-5406-8 [4] Adel S. Sedra, Kenneth C. Smith, MICOELECTONIC CICUIT FOUTH EDITION, ISBN: 957-999-5-0 [5] Jongson KIM, Yongfong KIM and Shiho KIM, A heap-pump circuit for positive high voltage generators, IEICE Trans Electron, vol. e85-c, no. 3, pp. 859-86, March 00 4
5 The BIST Scheme for Digital-to Analog converters