Microsoft PowerPoint - STU_EC_Ch12_new.ppt
|
|
- 内 梁
- 4 years ago
- Views:
Transcription
1 樹德科技大學資訊工程系 Chapter 1: Signal Interfacing and Processing Shi-Huang Chen Fall Outline Digital Signal Processing Basics Converting Analog Signals to Digital Analog-to-Digital Conversion (ADC) Methods Digital-to-Analog Conversion (DAC) Methods The Digital Signal Processor (DSP) 1
2 Digital Signal Processing Basics ADC: Analog-to-Digital Conversion DSP: Digital Signal Processor DAC: Digitalto-Analog Conversion 3 Digital Signal Processing Basics Basic block diagram of a digital signal processing system 4
3 Sampling Most input signals to an electronic system start out as analog signals. For processing, the signal is normally converted to a digital signal by sampling the input. Before sampling, the analog input must be filtered with a low-pass anti-aliasing filter. The filter eliminates frequencies that exceed a certain limit that is determined by the sampling rate. Analog input signal Sampling pulses Sampling circuit Sampled version of input signal 5 Anti-aliasing Filter HAY NYQUIST NYQUIST THEOEM (198) To understand the need for an anti-aliasing filter, you need to understand the sampling theorem which essentially states: In order to recover a signal, the sampling rate must be greater than twice the highest frequency in the signal. Stated as an equation, f sample >f a(max) where f sample = sampling frequency f a(max) = highest harmonic in the analog signal If the signal is sampled less than this, the recovery process will produce frequencies that are entirely different than in the original signal. These masquerading signals are called aliases. 6 3
4 Anti-aliasing Filter The anti-aliasing filter is a low-pass filter that limits high frequencies in the input signal to only those that meet the requirements of the sampling theorem. Filtered Unfiltered analog analog frequency frequency spectrum spectrum Sampling frequency spectrum f Overlap causes c aliasing error f sample The filter s cutoff frequency, f c, should be less than ½ f sample. f 7 Analog-to-Digital Conversion (ADC) To process naturally occurring analog quantities with a digital system, the analog signal is converted to digital form after the anti-aliasing filter. The first step in converting a signal to digital form is to use a sampleand-hold circuit. This circuit samples the input signal at a rate determined by a clock signal and holds the level on a capacitor until the next clock pulse. A positive half-wave from 0-10 V is shown in blue. The sample-andhold circuit produces the staircase representation shown in red. 10 V 0 V 8 4
5 Analog-to-Digital Conversion The second step is to quantize these staircase levels to binary coded form using an analog-to-digital converter (ADC). The digital values can then be processed by a digital signal processor or computer. What is the maximum unsigned binary value for the waveform? 10 V = 1010 V. The table lists the quantized binary values for all of the steps. Peak = 10 V 10 V 0 V Anti-aliasing Filter Most signals have higher frequency harmonic and noise. For most ADCs, the sampling and filter cutoff frequencies are selected to be able to reconstruct the desired signal without including unnecessary harmonics and noise. An example of a reasonable sampling rate is in a digital audio CD. For audio CDs, sampling is done at 44.1 khz because audio frequencies above 0 khz are not detectable by the ear. What cutoff frequency should an anti-aliasing filter have for a digital audio CD? Less than.05 khz. 10 5
6 Sample-and-Hold and ADC Following the anti-aliasing filter, is the sample-and-hold circuit and the analog-to-digital converter. At this point, the original analog signal has been converted to a digital signal. Samples held for one clock pulse ADC Many ICs can perform both functions on a single chip and include two or more channels. For audio applications, the AD1871 is an example of a stereo audio ADC. 11 Analog-to-Digital Conversion Methods Flash (Simultaneous) Analog-to-Digital Conversion Dual-Slope Analog-to-Digital Conversion Successive-Approximation Analog-to-Digital Converter Sigma-Delta Analog-to-Digital Converter 1 6
7 The operational amplifier (op-amp) V V out in = f i (1) V () V in1 in1 V V in in < 0, V > 0, V out out = V = V sat sat 13 Analog-to-Digital Conversion Methods V EF Op-amp comparators Input from sampleand-hold The flash ADC: The flash ADC uses a series highspeed comparators that compare the input with reference voltages. Flash ADCs are fast but require n 1 comparators to convert an analog input to an n-bit binary number. Priority encoder EN Enable pulses D 0 Parallel D 1 binary output D How many comparators are needed by a 10-bit flash ADC?
8 Analog-to-Digital Conversion Methods The dual-slope ADC: 1. The dual-slope ADC integrates the input voltage for a fixed time while the counter counts to n.. Control logic switches to the V EF input.. A fixed-slope ramp starts from V as the counter counts. When it reaches 0 V, the counter output is latched. V in I I C SW -V 0 V A 1 A EF Variable Fixed time interval 0 0 t = n counts Variable Variable voltage V Fixed-slope V ramp HIGH Control logic CLK C n EN Counter Latches D 7 D 6 D 5 D 4 D 3 D D 1 D 0 15 Analog-to-Digital Conversion Methods The successive approximation ADC: 1. Starting with the MSB, each bit in the successive approximation register (SA) is activated and tested by the digital-to-analog converter (DAC).. After each test, the DAC produces an output voltage that represents the bit. 3. The comparator compares this voltage with the input signal. If the input is larger, the bit is retained; otherwise it is reset (0). Input signal V out Comparator CLK (MSB) D C DAC SA (LSB) The method is fast and has a fixed conversion time for all inputs. D 0 D 1 D D 3 Serial binary output Parallel binary output 16 8
9 Analog-to-Digital Conversion Methods The sigma-delta ADC: With sigma-delta conversion, the difference between two samples of the analog input signal integrated and quantized. The density of 1s at the output is proportional to the input signal. Analog input signal Summing point Σ Integrator 1-bit quantizer Quantized output is a single bit data stream. DAC 17 Analog-to-Digital Conversion Methods One option for the sigma-delta method is to count the onebit quantized output for a set interval. The output of the counter is latched with the parallel binary code. Analog input signal Summing point Σ Integrator 1-bit DAC 1-bit quantizer n-bit counter. Latch. Binary code output Sigma-delta ADCs can have high resolution and have advantages for rejecting noise signals (such as 60 Hz power line interference). They are available in ICs with internal programmable amplifiers. For these reasons, they are widely used in instrumentation applications. 18 9
10 Illustrations of ADC errors Missing code Incorrect codes Offset 19 Digital-to-Analog Conversion Methods Binary-Weighted-Input Digital-to-Analog Converter - Ladder Digital-to-Analog Converter 0 10
11 Digital-to-Analog Conversion Methods Binary-weighted-input DAC: The binary-weighted-input DAC is a basic DAC in which the input current in each resistor is proportional to the column weight in the binary numbering system. It requires very accurate resistors and identical HIGH level voltages for accuracy. The MSB is represented by the largest current, so it has the smallest resistor. To simplify analysis, assume all current goes through f and none into the op-amp. LSB D 0 D 1 D D 3 MSB 8 4 I 0 I 1 I I 3 I = 0 f I f V out Analog output 1 Digital-to-Analog Conversion Methods A certain binary-weighted-input DAC has a binary input of If a HIGH = 3.0 V and a LOW = 0 V, what is V out? 3.0 V 0 V 3.0 V 3.0 V 10 kω 60 kω 30 kω 15 kω f 10 kω Iout = ( I0 I1 I I3) 3.0 V 3.0 V 3.0 V = 0 V = 0.35 ma 10 kω 30 kω 15 kω V out = I out f = ( 0.35 ma)(10 kω) = 3.5 V V out 11
12 Digital-to-Analog Conversion Methods - ladder: The - ladder requires only two values of resistors. By calculating a Thevenin equivalent circuit for each input, you can show that the output is proportional to the binary weight of inputs that are HIGH. VS Each input that is HIGH contributes to the output: V = where V S = input HIGH level voltage n = number of bits i = bit number For accuracy, the resistors must be precise ratios, which is easily done in integrated circuits. Inputs D 0 D 1 D D out n i f = V out 3 Digital-to-Analog Conversion Methods An - ladder has a binary input of If a HIGH = 5.0 V and a LOW = 0 V, what is V out? D 0 D 1 D D V 5.0 V 0 V 5.0 V kω 4 50 kω 6 50 kω 8 50 kω 50 kω 5 kω 5 kω 5 kω f = 50 kω V out VS Apply Vout = to all inputs that are HIGH, then sum the results. n i 5 V 5 V Vout ( D0 ) = = V V ( 4 0 out D1 ) = = 0.65 V V Vout ( D3 ) = =.5 V Applying superposition, V 4 3 out = 3.43 V 4 1
13 esolution and Accuracy of DACs The - ladder is relatively easy to manufacturer and is available in IC packages. DACs based on the - network are available in 8, 10, and 1-bit versions. The resolution is an important specification, defined as the reciprocal of the number of steps in the output. What is the resolution of the BCN31 - ladder network, which has 8-bits? 8 1 = 55 1/55 = 0.39% The accuracy is another important specification and is derived from a comparison of the actual output to the expected output. For the BCN31, the accuracy is specified as ±½ LSB = 0.%. 5 D/A Conversion Errors 6 13
14 D/A Conversion Errors 7 The econstruction Filter The reconstruction filter smooths the output of the DAC. 8 14
15 The Digital Signal Processor (DSP) A digital signal processor (DSP) is optimized for speed and working in real time (as events happen). It is basically a specialized microprocessor with a reduced instruction set. After filtering and converting the analog signal to digital, the DSP takes over. It may enhance the signal in some predetermined way (reducing noise or echoes, improving images, encrypting the signal, etc.). The signal can then be converted back to analog form if desired. Analog signal Anti-aliasing filter Sample-andhold circuit ADC DSP DAC econstruction filter Enhanced analog signal 9 DSP Programming Because speed is important in DSP applications, assembly language is frequently used because in general it executes faster. Program cache/program memory (3-bit address, 56-bit data) CPU (DSP core) A general block diagram of the TMS30C6000 series DSP DMA EMIF Program fetch Instruction dispatch Instruction decode Data path A Data path B Control registers Control logic egister file A egister file B Test.L1.S1.M1.D1.D.M.S.L Evaluation Interrupts Data cache/data memory (3-bit address, 8-, 16-, bit data) Additional peripherals 30 15
Microsoft PowerPoint - STU_EC_Ch08.ppt
樹德科技大學資訊工程系 Chapter 8: Counters Shi-Huang Chen Fall 2010 1 Outline Asynchronous Counter Operation Synchronous Counter Operation Up/Down Synchronous Counters Design of Synchronous Counters Cascaded Counters
More informationMicrosoft PowerPoint - STU_EC_Ch02.ppt
樹德科技大學資訊工程系 Chapter 2: Number Systems Operations and Codes Shi-Huang Chen Sept. 2010 1 Chapter Outline 2.1 Decimal Numbers 2.2 Binary Numbers 2.3 Decimal-to-Binary Conversion 2.4 Binary Arithmetic 2.5
More information2/80 2
2/80 2 3/80 3 DSP2400 is a high performance Digital Signal Processor (DSP) designed and developed by author s laboratory. It is designed for multimedia and wireless application. To develop application
More informationMicrosoft PowerPoint - STU_EC_Ch07.ppt
樹德科技大學資訊工程系 Chapter 7: Flip-Flops and Related Devices Shi-Huang Chen Fall 2010 1 Outline Latches Edge-Triggered Flip-Flops Master-Slave Flip-Flops Flip-Flop Operating Characteristics Flip-Flop Applications
More informationMicrosoft PowerPoint - STU_EC_Ch01.ppt
樹德科技大學資訊工程系 Chapter 1: Digital Concepts Shi-Huang Chen Sept. 2010 1 Chapter Outline 1.1 Digital and Analog Quantities 1.2 Binary Digits, Logic Level, and Digital Waveform 1.3 Basic Logic Operations 1.4
More informationOutline Speech Signals Processing Dual-Tone Multifrequency Signal Detection 云南大学滇池学院课程 : 数字信号处理 Applications of Digital Signal Processing 2
CHAPTER 10 Applications of Digital Signal Processing Wang Weilian wlwang@ynu.edu.cn School of Information Science and Technology Yunnan University Outline Speech Signals Processing Dual-Tone Multifrequency
More information<4D6963726F736F667420506F776572506F696E74202D20B5DAD2BBD5C228B4F2D3A1B0E6292E707074205BBCE6C8DDC4A3CABD5D>
Homeworks ( 第 三 版 ):.4 (,, 3).5 (, 3).6. (, 3, 5). (, 4).4.6.7 (,3).9 (, 3, 5) Chapter. Number systems and codes 第 一 章. 数 制 与 编 码 . Overview 概 述 Information is of digital forms in a digital system, and
More information穨control.PDF
TCP congestion control yhmiu Outline Congestion control algorithms Purpose of RFC2581 Purpose of RFC2582 TCP SS-DR 1998 TCP Extensions RFC1072 1988 SACK RFC2018 1996 FACK 1996 Rate-Halving 1997 OldTahoe
More informationMicrosoft PowerPoint - ATF2015.ppt [相容模式]
Improving the Video Totalized Method of Stopwatch Calibration Samuel C.K. Ko, Aaron Y.K. Yan and Henry C.K. Ma The Government of Hong Kong Special Administrative Region (SCL) 31 Oct 2015 1 Contents Introduction
More informationMicrosoft PowerPoint - CH 04 Techniques of Circuit Analysis
Chap. 4 Techniques of Circuit Analysis Contents 4.1 Terminology 4.2 Introduction to the Node-Voltage Method 4.3 The Node-Voltage Method and Dependent Sources 4.4 The Node-Voltage Method: Some Special Cases
More information1 1
1 1 2 Idea Architecture Design IC Fabrication Wafer (hundreds of dies) Sawing & Packaging Block diagram Final chips Circuit & Layout Design Testing Layout Bad chips Good chips customers 3 2 4 IC Fabless
More informationMicrosoft PowerPoint - Ch5 The Bipolar Junction Transistor
O2005: Electronics The Bipolar Junction Transistor (BJT) 張大中 中央大學通訊工程系 dcchang@ce.ncu.edu.tw 中央大學通訊系張大中 Electronics, Neamen 3th Ed. 1 Bipolar Transistor Structures N P 17 10 N D 19 10 N D 15 10 中央大學通訊系張大中
More informationEdge-Triggered Rising Edge-Triggered ( Falling Edge-Triggered ( Unit 11 Latches and Flip-Flops 3 Timing for D Flip-Flop (Falling-Edge Trigger) Unit 11
Latches and Flip-Flops 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with additional Inputs
More information1 VLBI VLBI 2 32 MHz 2 Gbps X J VLBI [3] CDAS IVS [4,5] CDAS MHz, 16 MHz, 8 MHz, 4 MHz, 2 MHz [6] CDAS VLBI CDAS 2 CDAS CDAS 5 2
32 1 Vol. 32, No. 1 2014 2 PROGRESS IN ASTRONOMY Feb., 2014 doi: 10.3969/j.issn.1000-8349.2014.01.07 VLBI 1,2 1,2 (1. 200030 2. 200030) VLBI (Digital Baseband Convertor DBBC) CDAS (Chinese VLBI Data Acquisition
More informationMicrosoft PowerPoint _代工實例-1
4302 動態光散射儀 (Dynamic Light Scattering) 代工實例與結果解析 生醫暨非破壞性分析團隊 2016.10 updated Which Size to Measure? Diameter Many techniques make the useful and convenient assumption that every particle is a sphere. The
More informationEmbargoed until May 4, 2004 EXPRESS 40 NI HQ 3000 1000 5000 ~ 500 10% / 500 85% NI LabVIEW 7 Express Express EXPRESS : #1 GPS Navigation PC/WWW/Email CD+RW Mobile Phone PDA DVD+RW Satellite Car Alarm/Radio
More informationuntitled
Portable Electrode B91901070 B91901133 量 ECG 路 更 量 路 performance RF 量 路 Portable Electrode 便利 量 portable electrode 路 濾 濾 行 electrode 類 FM modulation scheme ECG 類 數 RF RF demodulate 利 Elvis Labview ECG
More informationThe BIST Scheme for Digital-to Analog converters 1
The BIST Scheme for Digital-to Analog converters . :... 03.DAC :... 05. :... 08 ( ) :... 08 ( ) :... 08. :... ( ) OP AMP... ( ) Charge Pump Circuit... 3 ( ) Analog Summer Circuit... 4 ( ) CMOS Schmitt
More informationGH1220 Hall Switch
Unipolar Hall Switch - Medium Sensitivity Product Description The DH220 is a unipolar h all switch designed in CMOS technology. The IC internally includes a voltage regulator, Hall sensor with dynamic
More informationUDC Empirical Researches on Pricing of Corporate Bonds with Macro Factors 厦门大学博硕士论文摘要库
10384 15620071151397 UDC Empirical Researches on Pricing of Corporate Bonds with Macro Factors 2010 4 Duffee 1999 AAA Vasicek RMSE RMSE Abstract In order to investigate whether adding macro factors
More informationBC04 Module_antenna__ doc
http://www.infobluetooth.com TEL:+86-23-68798999 Fax: +86-23-68889515 Page 1 of 10 http://www.infobluetooth.com TEL:+86-23-68798999 Fax: +86-23-68889515 Page 2 of 10 http://www.infobluetooth.com TEL:+86-23-68798999
More informationMicrosoft Word - AP1515V02
Document No. Rev.: V0.20 Page: 1 of 9 Revision History Rev. DRN # History Initiator Effective Date V01 V02 Initial document 黃宗文 Add second package description 葉宗榮 2014/05/15 2015/09/08 Initiator: 雷晨妤 (DCC)
More informationPowerPoint Presentation
ITM omputer and ommunication Technologies Lecture #4 Part I: Introduction to omputer Technologies Logic ircuit Design & Simplification ITM 計算機與通訊技術 2 23 香港中文大學電子工程學系 Logic function implementation Logic
More information(baking powder) 1 ( ) ( ) 1 10g g (two level design, D-optimal) 32 1/2 fraction Two Level Fractional Factorial Design D-Optimal D
( ) 4 1 1 1 145 1 110 1 (baking powder) 1 ( ) ( ) 1 10g 1 1 2.5g 1 1 1 1 60 10 (two level design, D-optimal) 32 1/2 fraction Two Level Fractional Factorial Design D-Optimal Design 1. 60 120 2. 3. 40 10
More information专业主干课程与主要专业课程教学大纲(2009年、2011年).doc
... 1... 4... 9... 12... 16... 20... 23... 26... 30... 33... 36 Electric Circuits 00440021 64 0 0 4 1 2 Y- 3 4 ZYT H 5 Analog Electronic Technique 00440041 54 14 0 3.5 1. 2. 1. 2. 3. RC 4. 5. 1. 20 2.
More informationMCU DSP MSO MCU DSP MSO MSO MSO MCU/DSP I/O MSO 16 Microchip IC18 turn-on MSO chirp MCU I/O I 2 C
MSO MCU DSP MSO MCU DSP MSO MSO MSO MCU/DSP I/O MSO 16 Microchip IC18 turn-on MSO chirp MCU I/O I 2 C 03 Keysight MSO MSO MSO DSO holdoff infinite-persistence / de-skew MSO 1 MSO MSO MSO MSO MCU DSP 1
More informationiml88-0v C / 8W T Tube EVM - pplication Notes. IC Description The iml88 is a Three Terminal Current Controller (TTCC) for regulating the current flowi
iml88-0v C / 8W T Tube EVM - pplication Notes iml88 0V C 8W T Tube EVM pplication Notes Table of Content. IC Description.... Features.... Package and Pin Diagrams.... pplication Circuit.... PCB Layout
More informationIP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I
2004 5 IP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I Abstract The techniques of digital video processing, transferring
More informationMicrosoft PowerPoint - CA_03 Chapter5 Part-II_multi _V1.ppt
Chapter5-2 The Processor: Datapath and Control (Multi-cycle implementation) 臺大電機系 吳安宇教授 V1. 03/27/2007 For 2007 DSD Course 臺大電機吳安宇教授 - 計算機結構 1 Outline 5.1 Introduction 5.2 Logic Design Conventions 5.3
More informationAN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING
AN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING 前言 - Andrew Payne 目录 1 2 Firefly Basics 3 COMPONENT TOOLBOX 目录 4 RESOURCES 致谢
More informationMicrosoft Word - LR1122B-B.doc
UNISONIC TECHNOLOGIES CO., LTD LOW NOISE ma LDO REGULATOR DESCRIPTION The UTC is a typical LDO (linear regulator) with the features of High output voltage accuracy, low supply current, low ON-resistance,
More informationPin Configurations Figure2. Pin Configuration of FS2012 (Top View) Table 1 Pin Description Pin Number Pin Name Description 1 GND 2 FB 3 SW Ground Pin.
Features Wide 3.6V to 32V Input Voltage Range Output Adjustable from 0.8V to 30V Maximum Duty Cycle 100% Minimum Drop Out 0.6V Fixed 300KHz Switching Frequency 12A Constant Output Current Capability Internal
More informationCube20S small, speedy, safe Eextremely modular Up to 64 modules per bus node Quick reaction time: up to 20 µs Cube20S A new Member of the Cube Family
small, speedy, safe Eextremely modular Up to 64 modules per bus de Quick reaction time: up to 20 µs A new Member of the Cube Family Murrelektronik s modular I/O system expands the field-tested Cube family
More informationImproved Preimage Attacks on AES-like Hash Functions: Applications to Whirlpool and Grøstl
SKLOIS (Pseudo) Preimage Attack on Reduced-Round Grøstl Hash Function and Others Shuang Wu, Dengguo Feng, Wenling Wu, Jian Guo, Le Dong, Jian Zou March 20, 2012 Institute. of Software, Chinese Academy
More informationChroma 61500/ bit / RMS RMS VA ()61500 DSP THD /61508/61507/61609/61608/ (61500 ) Chroma STEP PULSE : LISTLIST 100 AC DC
MODEL 61509/61508/61507/ 61609/61608/61607 PROGRAMMABLE AC POWER SOURCE MODEL 61509/61508/61507/ 61609/61608/61607 61509/61609: 6kVA 61508/61608: 4.5kVA 61507/61607: 3kVA : 0-175V/0-350V/Auto : DC, 15Hz-2kHz
More information(02)2809-4742 (02)2809-4742 27 28 (02)2809-4742 85 3 (02)3343-3300 156 12 (02
3475 http://mops.tse.com.tw http://www.ic-fortune.com (02)2809-4742 denis.lee@ic-fortune.com (02)2809-4742 nanhui.lee@ic-fortune.com 27 28 (02)2809-4742 85 3 (02)3343-3300 http://www.fhs.com.tw 156 12
More informationSuperMap 系列产品介绍
wuzhihong@scu.edu.cn 3 / 1 / 16 / John M. Yarbrough: Digital Logic Applications and Design + + 30% 70% 1 CHAPTER 1 Digital Concepts and Number Systems 1.1 Digital and Analog: Basic Concepts P1 1.1 1.1
More informationuntitled
Co-integration and VECM Yi-Nung Yang CYCU, Taiwan May, 2012 不 列 1 Learning objectives Integrated variables Co-integration Vector Error correction model (VECM) Engle-Granger 2-step co-integration test Johansen
More information國 立 政 治 大 學 教 育 學 系 2016 新 生 入 學 手 冊 目 錄 表 11 國 立 政 治 大 學 教 育 學 系 博 士 班 資 格 考 試 抵 免 申 請 表... 46 論 文 題 目 申 報 暨 指 導 教 授... 47 表 12 國 立 政 治 大 學 碩 博 士 班 論
國 立 政 治 大 學 教 育 學 系 2016 新 生 入 學 手 冊 目 錄 一 教 育 學 系 簡 介... 1 ( 一 ) 成 立 時 間... 1 ( 二 ) 教 育 目 標 與 發 展 方 向... 1 ( 三 ) 授 課 師 資... 2 ( 四 ) 行 政 人 員... 3 ( 五 ) 核 心 能 力 與 課 程 規 劃... 3 ( 六 ) 空 間 環 境... 12 ( 七 )
More information甄試報告1125.PDF
LabVIEW LabVIEW Laboratory Virtual Instrument Engineering Workbench G LabVIEW DAQ LabVIEW LabVIEW LabVIEW LabVIEW ph LabVIEW DAQ LabVIEW PZT LabVIEW / =2 10-8 1 LabVIEW DAQ LabVIEW DAQ DAQ LabVIEW DAQ
More informationr_09hr_practical_guide_kor.pdf
PRACTICAL GUIDE TO THE EDIROL R-09HR 3 4 PRACTICAL GUIDE TO THE EDIROL R-09HR 5 Situation 1 6 1 2 3 PRACTICAL GUIDE TO THE EDIROL R-09HR WAV MP3 WAV 24 bit/96 khz WAV 16 bit/44.1 khz MP3 128 kbps/44.1
More information致 谢 开 始 这 篇 致 谢 的 时 候, 以 为 这 是 最 轻 松 最 愉 快 的 部 分, 而 此 时 心 头 却 充 满 了 沉 甸 甸 的 回 忆 和 感 恩, 一 时 间 竟 无 从 下 笔 虽 然 这 远 不 是 一 篇 完 美 的 论 文, 但 完 成 这 篇 论 文 要 感 谢
中 国 科 学 技 术 大 学 博 士 学 位 论 文 论 文 课 题 : 一 个 新 型 简 易 电 子 直 线 加 速 器 的 关 键 技 术 研 究 学 生 姓 名 : 导 师 姓 名 : 单 位 名 称 : 专 业 名 称 : 研 究 方 向 : 完 成 时 间 : 谢 家 麟 院 士 王 相 綦 教 授 国 家 同 步 辐 射 实 验 室 核 技 术 及 应 用 加 速 器 物 理 2006
More informationMicrosoft Word - TIP006SCH Uni-edit Writing Tip - Presentperfecttenseandpasttenseinyourintroduction readytopublish
我 难 度 : 高 级 对 们 现 不 在 知 仍 道 有 听 影 过 响 多 少 那 次 么 : 研 英 究 过 文 论 去 写 文 时 作 的 表 技 引 示 巧 言 事 : 部 情 引 分 发 言 该 生 使 在 中 用 过 去, 而 现 在 完 成 时 仅 表 示 事 情 发 生 在 过 去, 并 的 哪 现 种 在 时 完 态 成 呢 时? 和 难 过 道 去 不 时 相 关? 是 所 有
More informationJOURNAL OF EARTHQUAKE ENGINEERING AND ENGINEERING VIBRATION Vol. 31 No. 5 Oct /35 TU3521 P315.
31 5 2011 10 JOURNAL OF EARTHQUAKE ENGINEERING AND ENGINEERING VIBRATION Vol. 31 No. 5 Oct. 2011 1000-1301 2011 05-0075 - 09 510405 1 /35 TU3521 P315. 8 A Earthquake simulation shaking table test and analysis
More information<4D6963726F736F667420576F7264202D205F4230365FB942A5CEA668B443C5E9BB73A740B5D8A4E5B8C9A552B1D0A7F75FA6BFB1A4ACFC2E646F63>
運 用 多 媒 體 製 作 華 文 補 充 教 材 江 惜 美 銘 傳 大 學 應 用 中 文 系 chm248@gmail.com 摘 要 : 本 文 旨 在 探 究 如 何 運 用 多 媒 體, 結 合 文 字 聲 音 圖 畫, 製 作 華 文 補 充 教 材 當 我 們 在 進 行 華 文 教 學 時, 往 往 必 須 透 過 教 案 設 計, 並 製 作 補 充 教 材, 方 能 使 教 學
More informationMicrosoft PowerPoint - STU_EC_Ch04.ppt
樹德科技大學資訊工程系 Chapter 4: Boolean Algebra and Logic Simplification Shi-Huang Chen Fall 200 Outline Boolean Operations and Expressions Laws and Rules of Boolean Algebra DeMorgan's Theorems Boolean Analysis
More information邏輯分析儀的概念與原理-展示版
PC Base Standalone LA-100 Q&A - - - - - - - SCOPE - - LA - - ( Embedded ) ( Skew ) - Data In External CLK Internal CLK Display Buffer ASIC CPU Memory Trigger Level - - Clock BUS Timing State - ( Timing
More informationiml v C / 0W EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the current flowin
iml8683-220v C / 0W EVM - pplication Notes iml8683 220V C 0W EVM pplication Notes Table of Content. IC Description... 2 2. Features... 2 3. Package and Pin Diagrams... 2 4. pplication Circuit... 3 5. PCB
More informationComputer Architecture
ECE 3120 Computer Systems Assembly Programming Manjeera Jeedigunta http://blogs.cae.tntech.edu/msjeedigun21 Email: msjeedigun21@tntech.edu Tel: 931-372-6181, Prescott Hall 120 Prev: Basic computer concepts
More informationMicrosoft PowerPoint - talk8.ppt
Adaptive Playout Scheduling Using Time-scale Modification Yi Liang, Nikolaus Färber Bernd Girod, Balaji Prabhakar Outline QoS concerns and tradeoffs Jitter adaptation as a playout scheduling scheme Packet
More informationiml v C / 4W Down-Light EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the cur
iml8683-220v C / 4W Down-Light EVM - pplication Notes iml8683 220V C 4W Down Light EVM pplication Notes Table of Content. IC Description... 2 2. Features... 2 3. Package and Pin Diagrams... 2 4. pplication
More information幻灯片 1
Digital Signal Processing(DSP) : 203 : 0531-88364509 Email: jiangmingyan@sdu.edu.cn : ---- ---- JMY Copyright Reserved, SDU, 1 / 69 : (,, 2007 64 48 16 1 8 1. 2 2. 6 3. 6 4. 8 5., FFT 8 6. 6 7. 8 8. 4
More informationHC50246_2009
Page: 1 of 7 Date: June 2, 2009 WINMATE COMMUNICATION INC. 9 F, NO. 111-6, SHING-DE RD., SAN-CHUNG CITY, TAIPEI, TAIWAN, R.O.C. The following merchandise was submitted and identified by the vendor as:
More informationa b c d e f g C2 C1 2
a b c d e f g C2 C1 2 IN1 IN2 0 2 to 1 Mux 1 IN1 IN2 0 2 to 1 Mux 1 Sel= 0 M0 High C2 C1 Sel= 1 M0 Low C2 C1 1 to 2 decoder M1 Low 1 to 2 decoder M1 High 3 BCD 1Hz clk 64Hz BCD 4 4 0 1 2 to 1 Mux sel 4
More informationSerial ATA ( Silicon Image SiI3114)...2 (1) SATA... 2 (2) B I O S S A T A... 3 (3) RAID BIOS RAID... 5 (4) S A T A... 8 (5) S A T A... 10
Serial ATA ( Silicon Image SiI3114)...2 (1) SATA... 2 (2) B I O S S A T A... 3 (3) RAID BIOS RAID... 5 (4) S A T A... 8 (5) S A T A... 10 Ác Åé å Serial ATA ( Silicon Image SiI3114) S A T A (1) SATA (2)
More information2015年4月11日雅思阅读预测机经(新东方版)
剑 桥 雅 思 10 第 一 时 间 解 析 阅 读 部 分 1 剑 桥 雅 思 10 整 体 内 容 统 计 2 剑 桥 雅 思 10 话 题 类 型 从 以 上 统 计 可 以 看 出, 雅 思 阅 读 的 考 试 话 题 一 直 广 泛 多 样 而 题 型 则 稳 中 有 变 以 剑 桥 10 的 test 4 为 例 出 现 的 三 篇 文 章 分 别 是 自 然 类, 心 理 研 究 类,
More informationLH_Series_Rev2014.pdf
REMINDERS Product information in this catalog is as of October 2013. All of the contents specified herein are subject to change without notice due to technical improvements, etc. Therefore, please check
More informationMicrosoft PowerPoint - Performance Analysis of Video Streaming over LTE using.pptx
ENSC 427 Communication Networks Spring 2016 Group #2 Project URL: http://www.sfu.ca/~rkieu/ensc427_project.html Amer, Zargham 301149920 Kieu, Ritchie 301149668 Xiao, Lei 301133381 1 Roadmap Introduction
More informationMicrosoft PowerPoint - elec_06_diode [相容模式]
CHAPTER 7 半 導 體 (semi-conductor) 與 二 極 體 (diode) CHAPTER 8 二 極 體 的 應 用 圖 7-1 矽 (a) 與 鍺 (b) 的 原 子 結 構 圖 7-2 矽 原 子 的 共 價 鍵 結 圖 7-3 73 溫 度 升 高 導 致 自 由 電 子 增 加, 原 來 的 位 置 形 成 電 洞 如 圖 7-3, 當 溫 度 增 加 時, 價 電
More informationBasic Properties of Digital Images
Cell Biology Application of Microscopy Class 13: Image Processing and Manipulation Pascale Lacor, Mature rat hippocampal neurons attacked by Alzheimer s related neurotoxins (100X) Basic Properties of Digital
More informationMicrosoft PowerPoint - ryz_030708_pwo.ppt
Long Term Recovery of Seven PWO Crystals Ren-yuan Zhu California Institute of Technology CMS ECAL Week, CERN Introduction 20 endcap and 5 barrel PWO crystals went through (1) thermal annealing at 200 o
More information9 什 么 是 竞 争 与 冒 险 现 象? 怎 样 判 断? 如 何 消 除?( 汉 王 笔 试 ) 在 组 合 逻 辑 中, 由 于 门 的 输 入 信 号 通 路 中 经 过 了 不 同 的 延 时, 导 致 到 达 该 门 的 时 间 不 一 致 叫 竞 争 产 生 毛 刺 叫 冒 险 如
FPGA 工 程 师 面 试 试 题 一 1 同 步 电 路 和 异 步 电 路 的 区 别 是 什 么?( 仕 兰 微 电 子 ) 2 什 么 是 同 步 逻 辑 和 异 步 逻 辑?( 汉 王 笔 试 ) 同 步 逻 辑 是 时 钟 之 间 有 固 定 的 因 果 关 系 异 步 逻 辑 是 各 时 钟 之 间 没 有 固 定 的 因 果 关 系 3 什 么 是 " 线 与 " 逻 辑, 要 实
More information國立中山大學學位論文典藏.PDF
I II III The Study of Factors to the Failure or Success of Applying to Holding International Sport Games Abstract For years, holding international sport games has been Taiwan s goal and we are on the way
More informationPLC Simulative Control of an Elevator by PLC POWER SUPPLY ii iii ABSTRACT In the modern time, elevator is very popular and based. Most techniques of elevator are owned by foreigners. A simple introduction
More informationOSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Prot
OSI OSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Protocol OSI OSI OSI OSI OSI O S I 2-1 Application
More informationHC20131_2010
Page: 1 of 8 Date: April 14, 2010 WINMATE COMMUNICATION INC. 9 F, NO. 111-6, SHING-DE RD., SAN-CHUNG CITY, TAIPEI, TAIWAN, R.O.C. The following merchandise was submitted and identified by the vendor as:
More information國家圖書館典藏電子全文
I Abstract II III ... I Abstract...II...III... IV... VI 1...1 2...3 2-1...3 2-2...4 2-3...6 2-4...6 3...8 3-1...8 3-2...10 4...12 5...15 5-1...15 5-2...17 IV 5-3...18 6...21 6-1...21 6-2...22 6-3...22
More information5 6 6 7 7 8 8 9 9 9 9 10 10 10 10 11 11 11 11 11 12 13 13 14 15 17 17 17 18 18 19 19 19 20 20 21 21 22 22 22 23 / 24 24 24 XY 24 Z 25 XYZ 25 25 26 26
5 6 6 7 7 8 8 9 9 9 9 10 10 10 10 11 11 11 11 11 12 13 13 14 15 17 17 17 18 18 19 19 19 20 20 21 21 22 22 22 23 / 24 24 24 XY 24 Z 25 XYZ 25 25 26 26 27 27 28 28 28 29 29 29 29 30 30 31 31 31 32 www.tektronix.com
More informationuntitled
數 Quadratic Equations 數 Contents 錄 : Quadratic Equations Distinction between identities and equations. Linear equation in one unknown 3 ways to solve quadratic equations 3 Equations transformed to quadratic
More information1.ai
HDMI camera ARTRAY CO,. LTD Introduction Thank you for purchasing the ARTCAM HDMI camera series. This manual shows the direction how to use the viewer software. Please refer other instructions or contact
More informationChapter 24 DC Battery Sizing
26 (Battery Sizing & Discharge Analysis) - 1. 2. 3. ETAP PowerStation IEEE 485 26-1 ETAP PowerStation 4.7 IEEE 485 ETAP PowerStation 26-2 ETAP PowerStation 4.7 26.1 (Study Toolbar) / (Run Battery Sizing
More information<4D6963726F736F667420576F7264202D2032303130C4EAC0EDB9A4C0E04142BCB6D4C4B6C1C5D0B6CFC0FDCCE2BEABD1A15F325F2E646F63>
2010 年 理 工 类 AB 级 阅 读 判 断 例 题 精 选 (2) Computer mouse How does the mouse work? We have to start at the bottom, so think upside down for now. It all starts with mouse ball. As the mouse ball in the bottom
More informationPowerPoint Presentation
Decision analysis 量化決策分析方法專論 2011/5/26 1 Problem formulation- states of nature In the decision analysis, decision alternatives are referred to as chance events. The possible outcomes for a chance event
More informationMicrosoft PowerPoint - Sens-Tech WCNDT [兼容模式]
X-ray data acquisition systems for NDT applications 技股份有限公司 先锋科技股份有限公司 科技股份有限公司 先锋科技股份有限公司 www Sens-Tech Ltd UK based company 40 Staff Specialise in detection and data acquisition systems for light and
More informationA VALIDATION STUDY OF THE ACHIEVEMENT TEST OF TEACHING CHINESE AS THE SECOND LANGUAGE by Chen Wei A Thesis Submitted to the Graduate School and Colleg
上 海 外 国 语 大 学 SHANGHAI INTERNATIONAL STUDIES UNIVERSITY 硕 士 学 位 论 文 MASTER DISSERTATION 学 院 国 际 文 化 交 流 学 院 专 业 汉 语 国 际 教 育 硕 士 题 目 届 别 2010 届 学 生 陈 炜 导 师 张 艳 莉 副 教 授 日 期 2010 年 4 月 A VALIDATION STUDY
More information52C-14266-5
逻 辑 分 析 仪 基 础 知 识 入 门 手 册 www.tektronix.com.cn/logic_analyzers 15 入 门 手 册 目 录 引 言 3-4 起 源 3 数 字 示 波 器 3 逻 辑 分 析 仪 4 逻 辑 分 析 仪 操 作 5-13 连 接 被 测 系 统 5 探 头 5 设 置 逻 辑 分 析 仪 7 设 置 时 钟 模 式 7 设 置 触 发 7 采 集 状
More informationTestNian
Fatigue Damage Mechanism in Very High Cycle Regime Nian Zhou 2012.5.24 Fatigue Low cycle fatigue N f 10 5 cycles Strain-controlled fatigue High cycle fatigue N f f 10 5 cycles Stress-based fatigue Endurance
More informationSystem Design and Setup of a Robot to Pass over Steps Abstract In the research, one special type of robots that can pass over steps is designed and se
8051 8051 System Design and Setup of a Robot to Pass over Steps Abstract In the research, one special type of robots that can pass over steps is designed and setup. This type of robot uses two kinds of
More information穨R _report.PDF
TERM PROJECT R88921002 Sigma-Delta Modulation (1), (A/D,D/A) (Quantization Error), Sigma-Delta Modulation, ADC, DAC Fractional N Frequency Synthesizer,,,, (2) Ó-Ä ADC cascaded integrator-comb filter( ),
More informationenews174_2
103 CMOS Seal-Ring 104 e-learning 104 104 / http://www.cic.org.tw/login/login.jsp CIC Introduction to Conversational French - Syllabus Summer 2004 1 4 21 CMOS MorSensor MorFPGA DUO 2 MorSensor 3 103 (
More informationMicrosoft Word - A200810-897.doc
基 于 胜 任 特 征 模 型 的 结 构 化 面 试 信 度 和 效 度 验 证 张 玮 北 京 邮 电 大 学 经 济 管 理 学 院, 北 京 (100876) E-mail: weeo1984@sina.com 摘 要 : 提 高 结 构 化 面 试 信 度 和 效 度 是 面 试 技 术 研 究 的 核 心 内 容 近 年 来 国 内 有 少 数 学 者 探 讨 过 基 于 胜 任 特 征
More informationMicrosoft Word - P SDV series.DOC
片式压敏电阻器 SDV 系列 Chip SDV Series Operating Temp. : -55 ~ +125 特征 SMD 结构适合高密度安装 优异的限压比, 响应时间短 (
More informationIntroduction to Hamilton-Jacobi Equations and Periodic Homogenization
Introduction to Hamilton-Jacobi Equations and Periodic Yu-Yu Liu NCKU Math August 22, 2012 Yu-Yu Liu (NCKU Math) H-J equation and August 22, 2012 1 / 15 H-J equations H-J equations A Hamilton-Jacobi equation
More informationGerotor Motors Series Dimensions A,B C T L L G1/2 M G1/ A 4 C H4 E
Gerotor Motors Series Size CC-A Flange Options-B Shaft Options-C Ports Features 0 0 5 5 1 0 1 0 3 3 0 0 SAE A 2 Bolt - (2) 4 Bolt Magneto (4) 4 Bolt Square (H4) 1.0" Keyed (C) 25mm Keyed (A) 1.0' 6T Spline
More informationNANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94
NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz 23 90 CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94/188GHz LC class-b 0.70 0.75 mm 2 pad 1 V 19.6 ma (ƒ
More information10384 19020101152519 UDC Rayleigh Quasi-Rayleigh Method for computing eigenvalues of symmetric tensors 2 0 1 3 2 0 1 3 2 0 1 3 2013 , 1. 2. [4], [27].,. [6] E- ; [7], Z-. [15]. Ramara G. kolda [1, 2],
More informationMicrosoft PowerPoint - CA_02 Chapter5 Part-I_Single _V2.ppt
Chapter5- The Processor: Datapath and Control (Single-cycle implementation) 臺大電機系吳安宇教授 V. 3/27/27 V2. 3/29/27 For 27 DSD Course 臺大電機吳安宇教授 - 計算機結構 Outline 5. Introduction 5.2 Logic Design Conventions 5.3
More informationTHE APPLICATION OF ISOTOPE RATIO ANALYSIS BY INDUCTIVELY COUPLED PLASMA MASS SPECTROMETER A Dissertation Presented By Chaoyong YANG Supervisor: Prof.D
10384 070302 9825042 UDC 2001.6. 2001.7. 20016 THE APPLICATION OF ISOTOPE RATIO ANALYSIS BY INDUCTIVELY COUPLED PLASMA MASS SPECTROMETER A Dissertation Presented By Chaoyong YANG Supervisor: Prof.Dr. Xiaoru
More informationA Study on Grading and Sequencing of Senses of Grade-A Polysemous Adjectives in A Syllabus of Graded Vocabulary for Chinese Proficiency 2002 I II Abstract ublished in 1992, A Syllabus of Graded Vocabulary
More informationMicrosoft Word doc
中 考 英 语 科 考 试 标 准 及 试 卷 结 构 技 术 指 标 构 想 1 王 后 雄 童 祥 林 ( 华 中 师 范 大 学 考 试 研 究 院, 武 汉,430079, 湖 北 ) 提 要 : 本 文 从 结 构 模 式 内 容 要 素 能 力 要 素 题 型 要 素 难 度 要 素 分 数 要 素 时 限 要 素 等 方 面 细 致 分 析 了 中 考 英 语 科 试 卷 结 构 的
More information声 明 本 人 郑 重 声 明 : 此 处 所 提 交 的 硕 士 学 位 论 文 基 于 等 级 工 鉴 定 的 远 程 考 试 系 统 客 户 端 开 发 与 实 现, 是 本 人 在 中 国 科 学 技 术 大 学 攻 读 硕 士 学 位 期 间, 在 导 师 指 导 下 进 行 的 研 究
中 国 科 学 技 术 大 学 硕 士 学 位 论 文 题 目 : 农 村 电 工 岗 位 培 训 考 核 与 鉴 定 ( 理 论 部 分 ) 的 计 算 机 远 程 考 试 系 统 ( 服 务 器 端 ) 的 开 发 与 实 现 英 文 题 目 :The Realization of Authenticating Examination System With Computer & Web for
More information5991-1117CHCN.indd
开 关 电 源 测 量 应 用 指 南 使 用 Agilent InfiniiVision 3000/4000 X 系 列 示 波 器 并 结 合 开 关 电 源 测 量 选 件 简 介 配 有 开 关 电 源 测 量 选 件 的 Agilent 3000 和 4000 X 系 列 示 波 器 能 够 提 供 一 个 快 速 且 方 便 的 方 法, 帮 助 您 分 析 开 关 电 源 的 可 靠
More information國 立 屏 東 教 育 大 學 中 國 語 文 學 系 碩 士 班 碩 士 論 文 國 小 國 語 教 科 書 修 辭 格 分 析 以 南 一 版 為 例 指 導 教 授 : 柯 明 傑 博 士 研 究 生 : 鄺 綺 暖 撰 中 華 民 國 一 百 零 二 年 七 月 謝 辭 寫 作 論 文 的 日 子 終 於 畫 下 了 句 點, 三 年 前 懷 著 對 文 學 的 熱 愛, 報 考 了 中
More informationChn 116 Neh.d.01.nis
31 尼 希 米 书 尼 希 米 的 祷 告 以 下 是 哈 迦 利 亚 的 儿 子 尼 希 米 所 1 说 的 话 亚 达 薛 西 王 朝 二 十 年 基 斯 流 月 *, 我 住 在 京 城 书 珊 城 里 2 我 的 兄 弟 哈 拿 尼 和 其 他 一 些 人 从 犹 大 来 到 书 珊 城 我 向 他 们 打 听 那 些 劫 后 幸 存 的 犹 太 人 家 族 和 耶 路 撒 冷 的 情 形
More informationGerolor Motors Series Dimensions A,B C T L L G1/2 M8 G1/ A 4 C H4 E
Gerolor Motors Series Size CC-A Flange Options-B Shaft Options-C Ports Features 0 0 12 12 1 1 0 0 2 2 31 31 0 0 SAE A 2 Bolt - (2) 4 Bolt Magneto (4) 4 Bolt Square (H4) 1.0" Keyed (C) 2mm Keyed (A) 1.0'
More information致 谢 本 人 自 2008 年 6 月 从 上 海 外 国 语 大 学 毕 业 之 后, 于 2010 年 3 月 再 次 进 入 上 外, 非 常 有 幸 成 为 汉 语 国 际 教 育 专 业 的 研 究 生 回 顾 三 年 以 来 的 学 习 和 生 活, 顿 时 感 觉 这 段 时 间 也
精 英 汉 语 和 新 实 用 汉 语 课 本 的 对 比 研 究 The Comparative Study of Jing Ying Chinese and The New Practical Chinese Textbook 专 业 : 届 别 : 姓 名 : 导 师 : 汉 语 国 际 教 育 2013 届 王 泉 玲 杨 金 华 1 致 谢 本 人 自 2008 年 6 月 从 上 海 外
More informationSHIMPO_表1-表4
For servo motor ABLEREDUCER L Series Features Coaxial shaft series L series Helical gears contribute to reduce vibration and noise. Standard backlash is 5 arc-min, ideal for precision control. High rigidity
More informationTX-NR3030_BAS_Cs_ indd
TX-NR3030 http://www.onkyo.com/manual/txnr3030/adv/cs.html Cs 1 2 3 Speaker Cable 2 HDMI OUT HDMI IN HDMI OUT HDMI OUT HDMI OUT HDMI OUT 1 DIGITAL OPTICAL OUT AUDIO OUT TV 3 1 5 4 6 1 2 3 3 2 2 4 3 2 5
More information穨良導絡值與驗診壓力之關聯研究
Study for the Effect of Applied Diagnosis Pressure to Ryodoraku Acupuncture Readings Study for the Effect of Applied Diagnosis Pressure to Ryodoraku Acupuncture Readings I II Abstract Ryodoraku Acupuncture
More informationHC70245_2008
Reliability Laboratory Page: 1 of 6 Date: September 5, 2008 WINMATE COMMUNICATION INC. 9 F, NO. 111-6, SHING-DE RD., SAN-CHUNG CITY, TAIPEI, TAIWAN, R.O.C. The following merchandise was submitted and identified
More information