103 CMOS Seal-Ring 104 e-learning 104 104 / http://www.cic.org.tw/login/login.jsp CIC Introduction to Conversational French - Syllabus Summer 2004 1
4 21 CMOS MorSensor MorFPGA DUO 2
MorSensor 3
103 ( CIC ) 103 4 22 3 18 Full-custom 30 Full-custom 31 Analog Circuit 23 FPGA 30 Cell Based Design 63 ESL 4 181 346 ESL Full-custom SPEC_SEL 175 C 135 C 160 C 120 C Image Sorting Engine cell-based design flow Coding Full-custom 2-bit 10 MHz FPGA CIC MorFPGA+ 4
IC IC 4 24 6 2 5
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CEA(Alternative Energies and Atomic Energy Commission) CEA(Alternative Energies and Atomic Energy Commission) Prof. Ahmed Jerraya Dr. Thomas Olivier Dr. Erdengiz Ali 104 4 28 7
Advantest 93000 4 24 5 8 5 13 IC IC 8
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CMOS Seal-Ring / CMOS IC Seal-Ring DRC Dummy Pattern Seal-Ring Full-Custom IC Seal-Ring Layout Sample Seal-Ring Chip Scribe Line P-Substrate Seal-Ring Seal-Ring Seal-Ring Seal-Ring Layout Sample Seal-Ring Seal-Ring IC Layout Sample Seal-Ring Seal-Ring Step1 Step2 Virtuoso or Laker Stream In Import Stream Seal-Ring Library Step3 Layout View Step2 Instance Top Cell Layout Step4 Step3 Flatten(one level) Seal-Ring Step5 Seal-Ring Instance Seal-Ring 10
0,0 Step6 DRC Stream Out GDSII Layout File Seal-Ring Layout Sample Seal-Ring Step1 RFMOS, RLC, GSG Pad DRC X*Y 750*550 um 2 Step2 Layout Editor Stream In Import Stream Seal-Ring Library Virtuoso Layout Editor-Stream In 11
Laker Layout Editor-Import Stream Step3 Layout View Virtuoso Instance Step2 The Layout View of Seal-Ring Step4~5 Seal-Ring Flatten Seal-Ring Side Cell Columns/Rows i.e. Single Cell Edge to Edge 12
Flatten of Layout View Flatten Layout View 13
Properties Side Cell Side Cell Pattern 14
Side Cell Pattern Single Cell Step6 15
Seal-Ring Seal-Ring Step7 Seal-Ring Instance Seal-Ring 0,0 16
Seal-Ring Step8. Whole Chip DRC Stream Out DRC Density Rules DRC OD/Poly/ Metal Dummy Pattern PDK Seal-Ring Layout Design Rules Time to Tape-Out 17
104 e-learning 103 EDA Cloud EDA Cloud EDA Cloud 104 6 22 104 6 22 104 9 6 CIC http://www.cic.org.tw/login/login.jsp 104 5 26 10:00 104 6 10 03-5773693 144 E-Mail: huyjen@cic.narl.org.tw EDA Cloud EDA Cloud EDA Cloud EDA EDA Cloud EDA (1) System Overview (2) Cell Based Design Flow on EDA Cloud (3) Full Custom Design Flow on EDA Cloud 18
104 6 6/13 ADC DAC IC SoC Encounter IC 6/27 Gate-level SoC Encounter 90% 19
Design Compiler IC ( ) 6/27 Verilog Verilog Code CHIP Performance Cell-Based Front-end Mixed-signal Flow Synthesizable-Verilog IC IP Digital IC Soft-Macro Cell-Based Back-end Layout SoC Encounter IC Compiler http://www.cic.narl.org.tw/els/els_main.jsp CIC 511 5,000 3,000 10,000 50% 70% 3 03-577-3693 144 E-Mail: huyjen@cic.narl.org.tw 20
1 Verilog CIC Verilog 12 05/16 05/23 09:00~16:00 2 Design Compiler IC CIC Logic Synthesis 18 05/30 06/06 06/ 13 09:00~16:00 3 12 06/13 06/27 09:00~16:00 4 SoC Encounter IC CIC SOC Compiler 12 06/27 07/04 09:00~16:00 5 Design Compiler IC CIC Logic Synthesis 18 06/27 07/04 07/ 11 09:00~16:00 6 12 07/04 07/11 09:00~16:00 7 IC Compiler IC CIC IC Compiler 12 07/11 07/18 09:00~16:00 8 IC CIC Full Custom 18 07/18 07/25 08/01 09:00~16:00 9 Design and Application of PLL/DLL 12 07/25 08/01 09:00~16:00 10 Nyquist-rate ADCs design 12 09/05 09/12 09:00~16:00 11 12 09/05 09/12 09:00~16:00 21
104 104 CIC 104 PDF CIC Step1 2. 104 http://www2.cic.org.tw/~cis/chipapply/doc/104.pdf CIC 104 http://www.cic.org.tw/fab_services/index.jsp?menu=tyr_common 104 CIC 104 http://www2.cic.org.tw/~cis/chipapply/doc/schedule_l.pdf 22
T25HVG2-104B ( ) T25HVG2-104B-A0004 O 2.640*1.900 T25HVG2-104B-A0006 O P 1.491*1.500 T25HVG2-104B-I0001 O pn 1.274*1.249 T25HVG2-104B-E0001 O 1.212*0.790 T25HVG2-104B-E0002 O 0.992*1.497 T25HVG2-104B-E0003 O 1.500*1.000 T25HVG2-104B-E0005 O 1.375*0.900 T25HVG2-104B-E0006 O 1.500*1.000 T25HVG2-104B-E0007 O 1.087*0.721 T25HVG2-104B-E0008 O VCO AC to DC 1.336*0.911 T25HVG2-104B-E0009a O 1.500*0.896 T25HVG2-104B-E0010 O 0.674*0.782 23
Wafer Mapping (IC ) 24
U18-104A U18-104A-A0002 O 0.765*0.765 U18-104A-A0003 O 2.4GHz 2.677*1.854 U18-104A-A0004 O 10GHz 1.028*1.290 U18-104A-A0007 O 0.612*0.662 U18-104A-A0008 O 1.147*0.858 U18-104A-A0009 O 60 GHz CMOS 0.390*0.500 U18-104A-A0011m O ESD 3D 1.510*1.400 U18-104A-A0013m O 2.455*1.449 U18-104A-A0014m O ASIC CMOS 1.433*1.433 U18-104A-A0015m O 0.521*0.481 U18-104A-A0016m O 0.523*0.555 U18-104A-A0018 O 1.806*1.133 U18-104A-A0019 O SAW 0.789*0.679 U18-104A-A0020m O 1.915*1.205 U18-104A-A0023 O 13.56MHz 0.574*0.356 U18-104A-A0024 O 2.000*2.000 U18-104A-A0025 O 0.919*1.228 U18-104A-E0001 O 寗 0.9 25MHz 0.865*0.665 U18-104A-E0002 O R-2R - 0.515*0.625 U18-104A-E0004 O 0.670*0.630 U18-104A-E0005 O 0.481*0.509 U18-104A-E0006 O 0.977*0.975 25
U18-104A-E0007 O 0.684*0.353 U18-104A-E0009 O, O 0.707*0.707 U18-104A-E0010 O 15 GHz 1.425*1.190 U18-104A-E0012 O 0.450*0.450 U18-104A-E0013 O CMOS 0.919*1.333 U18-104A-E0015 O 0.415*0.219 U18-104A-E0016 O 1 MHz PWM DCM CCM 0.902*0.907 U18-104A-E0017 O 100MHZ 1.309*0.998 U18-104A-E0019 O, O 0.807*0.707 U18-104A-E0020 O Class-C 0.994*0.949 U18-104A-E0021 O K-band 1.195*1.205 U18-104A-E0022 O 1.002*0.968 U18-104A-E0023 O MDLL 0.998*0.998 U18-104A-E0024 O, O 0.914*0.614 U18-104A-E0025 O, O 0.708*0.708 U18-104A-E0026 O 0.997*1.098 U18-104A-I0001 O 1.118*0.893 U18-104A-I0002a O, O, O, O, O, O 3.163*3.088 U18-104A-I0004 O 2.4GHz 1.660*1.343 26
Wafer Mapping (IC ) 27
SiGe18-104B SiGe18-104B-A0005 O MI- MO 0.578*0.828 SiGe18-104B-A0006 O 1.199*1.191 SiGe18-104B-A0007 SiGe18-104B-A0008 O O 30 GHz 20-Gsps SiGe / 0.725*1.000 1.467*0.882 SiGe18-104B-N0001 O BiCMOS 1.819*2.315 SiGe18-104B-E0004 O 2.4GHz 1.194*1.185 SiGe18-104B-E0006 O, O 1.194*1.199 SiGe18-104B-E0008 O 3 0.884*0.645 SiGe18-104B-E0009 O 3 1.178*1.199 SiGe18-104B-E0010 O 2 0.731*1.060 SiGe18-104B-E0011 O Class-C 0.695*0.830 SiGe18-104B-E0012 O, O 1.154*0.816 SiGe18-104B-E0013 O, O 1.193*0.850 SiGe18-104B-E0014 O ( 2) 0.984*1.082 SiGe18-104B-E0015 O, O 1.196*0.854 SiGe18-104B-E0016 O ( 3) 0.990*1.165 SiGe18-104B-E0017 O 1.120*0.843 SiGe18-104B-E0018 O 0.852*1.029 28
Wafer Mapping (IC ) 29
P15-104A ( )/ ( ) P15-104A-A0002 X/Ku-Band 1.000*1.000 P15-104A-A0003 ku-band 1.000*1.000 P15-104A-A0004, LC 1.500*1.000 P15-104A-A0005, 1.500*1.000 P15-104A-A0006, LC 1.500*1.000 P15-104A-A0007, 4-8 GHz - 1.000*1.000 P15-104A-A0008 1.6~5.2GHz 2.000*1.000 P15-104A-A0009 4~24GHz 2.000*1.000 P15-104A-A0010 1.500*2.000 P15-104A-A0014 W 2.000*1.000 Wafer Mapping (IC ) 30