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1 國立交通大學 電子工程學系電子研究所碩士班 碩士論文 採用行為模型設計方法之超寬頻射頻前端接收器設計 UWB RF Receiver Front-End Design by Using Behavior Model 研究生 : 洪志德 指導教授 : 溫瓌岸博士 共同指導 : 周美芬博士 Chih-De Hung Dr. Kuei-Ann Wen Dr. Mei-Fen Chou 中華民國九十五年六月

2 採用行為模型設計方法之超寬頻射頻前端接收器設計 UWB RF Receiver Front-End Design by Using Behavior Model 研究生 : 洪志德 Student :Chih-De Hung 指導教授 : 溫瓌岸博士 Advisor :Dr. Kuei-Ann Wen 共同指導 : 周美芬博士 Co-Advisor :Dr. Mei-Fen Chou 國立交通大學電子工程學系電子研究所碩士班碩士論文 A Thesis Submitted to Department of Electronics Engineering & Institute of Electronics College of Electrical & Computer Engineering National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Master in Electronic Engineering 中華民國九十五年六月

3 採用行為模型設計方法 之超寬頻射頻前端接收器設計 學生 : 洪志德 指導教授 : 溫瓌岸博士 共同指導 : 周美芬博士 國立交通大學電子工程學系電子研究所碩士班 摘 要 為了改善射頻電路設計流程以及系統驗證的效率, 本論文提出一個可用於寬頻放大 器的行為模型計設方法 此行為模型將一放大器分成輸入介面 增益級與輸出介面三個 部份, 並且可同時模擬輸入 / 輸出阻抗匹配 雜訊指數 頻率響應以及非線性失真等射 頻電路的特性 為了證明此方法的可行性, 本論文設計了一個寬頻放大器的行為模型, 並比較電晶體階層與型為模型的系統模擬結果, 其 EVM 的均方根值誤差小於 0.79%, 模 擬時間減少了 87% 此行為模型除了能夠用來模擬一個既有的電路外, 也能夠用來幫助 設計新的電路 本論文利用此行為模型設計了一個以電容性交錯藕合技術做為輸入阻抗 匹配的低雜訊放大器, 並將此放大器應用於超寬頻射頻前端接收器 經由 0.18-μm CMOS 製程進行電路實作, 此射頻前端接收器的模擬結果, 其頻寬範圍為 GHz, 消耗 功率為 11.4mW, 同時具有 20.9 db 的最大電壓增益 3.4dB 的最低雜訊指數和 -14.3dBm 的最大第三階互調線性度 i

4 UWB RF Receiver Front-End Design by Using Behavior Model Student:Chih-De Hung Advisor:Dr. Kuei-Ann Wen Co-Advisor:Dr. Mei-Fen Chou Department of Electronics Engineering Institute of Electronics National Chiao-Tung University ABSTRACT In order to improve RFIC design flow and facilitate system performance verification, an innovative behavior model of wideband amplifier is proposed. The proposed behavior model can simultaneously predict the characteristics of RF effect of input/output impedance matching, noise, frequency response and nonlinearity in one single model. To demonstrate the feasibility of the model, a wideband LNA has been designed with this model. The system simulation results show that the behavior model agrees well with the transistor level circuit ii

5 with RMS error less than 0.79%, and 87% reduction of simulation time is achieved. The proposed behavior model can not only model an existed circuit, but also can help to design a new circuit. In this thesis, a design example of wideband LNA with capacitive cross-coupling (CCC) technique for input matching is presented. And the LNA is utilized in a receiver front-end design for UWB application. A circuit implementation in 0.18-μm CMOS process shows a GHz bandwidth. The UWB receiver front-end provides a maximum voltage conversion gain of 20.9 db while drawing 11.4 mw from a 1.8-V supply. A double sideband noise figure as low as 3.4 db and a maximum IIP3 of dbm have been simulated. iii

6 誌謝 在這碩士研究兩年間的光陰, 首先要感謝的是 TWT 實驗室的大家長 - 溫瓌岸教授賦予了大家豐富的資源和環境, 周美芬教授與溫文燊教授, 給予精闢的教導並在研究上給予方向, 在三位教授細心的指導下, 完成了這篇碩士論文 另外, 感謝各位口試委員們 - 陳巍仁教授與郭建男教授, 提供寶貴的建議與指教 感謝實驗室的學長們的指導與照顧 : 陳哲生學長, 鄒文安學長, 趙晧名學長, 彭嘉笙學長及林立協學長等在研究上的幫助與意見, 讓我獲益良多 感謝實驗室的同學 - 懷仁 彥凱 俊憲 振威 俊閔 書瑋 彥宏, 在課業和日常生活上, 大家總是相互的扶持幫助, 以及在學業上的討論與切磋 還有實驗室的學弟 - 家岱 書旗 漢建 閎仁 函霖 昱瑞 建龍 義凱 翔琮 建喻, 讓整個實驗室充滿了歡樂的氣息 ; 同時也要感謝實驗室的助理 : 淑怡 怡倩 恩齊 慶宏, 有妳們幫忙處理實驗室的雜務, 才能讓我們能夠專心致力於研究 最後, 我要感謝我的家人, 他們無怨無悔的付出與鼓勵, 使我求學過程中無後顧之憂, 僅以此論文與我的家人及好友分享我的收穫與喜悅, 願他們永遠平安 順心 誌予 2006 洪志德 iv

7 Contents 摘要 i Abstract ii 致謝 iv Contents v List of Figures viii List of Tables xi Chapter 1 Introduction Motivation Specifications MB-OFDM Proposal Brief Architecture and Link Analysis Organization...8 Chapter 2 A Unified Behavior Model Design Design Motivation The Unified Behavior Model Modeling of Input and Output Interfaces Modeling of Gain Stage...15 v

8 2.2.3 Modeling of Noise A Simple Example of the proposed Behavior Model Modeling Flow Design Example of UWB LNA I/O Interface G m Core Noise Sources Nonlinearity Performance Results System Simulation Platform RF/Baseband Co-Simulation Environment System Level Performance...29 Chapter 3 Capacitive Cross-Coupling UWB LNA Design Consideration of Wideband LNA Basic Concerns Recent Research Reviews on Broadband LNA Summary of Wideband LNAs Capacitive Cross-Coupling Amplifier The First Gain Stage with CCC Technique The Second Gain Stage The Overall UWB LNA with CCC Technique Summary...52 Chapter 4 Receiver Design by Using Proposed Behavior Model Construct a Coarse Model of CCC LNA Input Interface Gain Stage...56 vi

9 4.1.3 Center and Output Interfaces Noise Sources Design a CCC LNA Performance Comparison between the Coarse Behavior Model and Transistor Level Modify the Behavior Model UWB Receiver Design with CCC LNA DC Offset Even-Order Distortion Flicker Noise Mixer Design Simulation Results Measurement Plan Summary...76 Chapter 5 Conclusions and Future Work Summary Recommendations for Future Work...78 Appendix 80 Bibliography 85 Publication List 87 Vita 88 vii

10 List of Figures Figure 1 Transmitter power spectral density mask in MB OFDM proposal 5 Figure 2 Direct-conversion architecture for UWB receiver. 6 Figure 3 UWB receiver specifications. 7 Figure 4 Receiver noise figure degradation. 7 Figure 5 The proposed design flow 12 Figure 6 UWB system simulation block diagram. 14 Figure 7 A simple model of common-source amplifier 17 Figure 8 Unified behavioral modeling flow. 19 Figure 9 Target UWB LNA circuit. 21 Figure 10 The UWB LNA Model. 22 Figure 11 Comparison of input impedance. 24 Figure 12 Comparison of output impedance. 24 Figure 13 Comparison of voltage gain and NF. 25 Figure 14 Comparison of input IP3 and P 1dB in the frequency band of interest. 26 Figure 15 Comparison of NF and gain with sweeping RF power at GHz. 26 viii

11 Figure 16 RF/Baseband co-simulation model. 28 Figure 17 RF and Analog receiver behavior model. 28 Figure 18 Comparison of UWB system EVM simulation results. 30 Figure 19 Distributed amplifier 33 Figure 20 A broadband noise-canceling CMOS LNA 34 Figure 21 Capacitive cross-coupling LNA 35 Figure 22 A wideband LNA with band-pass filter for input matching 36 Figure 23 Resistive-Feedback CMOS LNA 36 Figure 24 Gain stage of capacitive cross-coupling technique 41 Figure 25 Small signal model of CCC technique 41 Figure 26 CCC technique with shunt-peaking load 46 Figure 27 NF and S 11 v.s. g m 47 Figure 28 The second stage of the UWB LNA. 48 Figure 29 The overall UWB LNA with CCC technique for input matching. 51 Figure 30 The behavior model of UWB LNA with CCC technique 55 Figure 31 Simulation results of Behavior Model and Transistor Level, (a) voltage gain, (b) S 11, (c) noise figure. 59 Figure 32 Active inductor, (a) schematic, (b) small signal circuit. 60 Figure 33 The proposed CCC LNA 61 ix

12 Figure 34 The modified behavior model of UWB LNA with CCC technique 62 Figure 35 Simulation results of the modified Behavior Model and Transistor Level, (a) voltage gain, (b) S 11, (c) noise figure. 63 Figure 36 Self-mixing of (a) LO signal, (b) a strong interferer. 66 Figure 37 Effect of even-order distortion on interferes. 67 Figure 38 (a) Double-balance mixer, (b) output buffer 68 Figure 39 Circuit Layout of the UWB receiver front-end with CCC technique 70 Figure 40 Conversion Gain 70 Figure 41 Noise figure 71 Figure 42 Input return loss 71 Figure 43 Output return loss 72 Figure 44 Input IP3 and P1dB 72 Figure 45 Input IP2 73 Figure 46 Measurement Environment 75 Figure 47 (a) Model 5230B, (b) rate race coupler (c) ADT4-6WT 76 x

13 List of Tables Table 1. Band assignment in Multi-Band OFDM proposal. 5 Table 2. Receiver performance requirement in MB OFDM proposal. 6 Table 3. Flat frequency response methods. 38 Table 4. Broadband matching methods. 38 Table 5. Pre-simulation results of the UWB LNA with CCC technique. 64 Table 6. Comparison results 74 xi

14 Chapter 1 Introduction Recently, the Federal Communications Commission (FCC) in US has approved the use of ultra-wideband (UWB) technology for commercial applications in the GHz frequency band [1]. The newly unlicensed UWB opens doors to wireless high-speed communications and has been exciting tremendous academic research interest. UWB performs excellently for short-range high-speed uses, such as automotive collision-detection systems, through-wall imaging systems and high-speed indoor networking, and plays an increasingly important role in wireless personal area network (WPAN) applications. This technology will be potentially a necessity in our daily life, from wireless USB to wireless connection between DVD player and TV, and the expectable huge market attracts various industries. The main challenge of IC design nowadays is how to implement circuits with the minimum 1

15 chip area, power consumption and time to market. Demands on cost reduction for wireless multimedia applications have driven the integration of both analog/rf and digital/baseband building circuits into a wireless transceiver system on a chip (wireless SoC). By integrating the circuits on a single chip, the pads can be reduced, and the chip area therefore is reduced. For wireless SoC designs involving analog/rf circuit integration, the system performance must be verified by the system simulation which takes a lot of time. In order to reduce the time for verification, the analog behavior models are used in system simulation. The analog behavior models are difficult to implement due to the complex analog characteristics, especially for the wideband applications. The lack of behavior model for analog/rf circuits make the verification for the entire system performance very time consuming. The wideband analog/rf behavior models which have essential RF characteristics, such as frequency response, input/output impedance and NF, are required for UWB system verification. 1.1 Motivation The behavior models of analog circuit blocks are widely used in system co-simulation. Several behavior models were introduced to describe the RF effects: linear transfer functions represent frequency dependence [2], S-parameter data in Touchstone format characterize impedance mismatch and frequency response for linear small-signal amplifiers, and black box 2

16 models in Volterra series can model nonlinear distortion [3]. Nevertheless, these models describe RF characteristics individually without considering the impact of each other and are insufficient for system simulation. Besides, the top-down design methodology is preferred to refine the specifications of the building blocks of RF module circuits at the beginning stage for developing sophisticated wireless systems. The table-based or polynomial models can not support top-down design methodology due to the lack of circuit insights in these models. A behavior model, which can not only be used in system co-simulation, but also assist with circuit design is desired. The research goal of this thesis is to implement a behavior model which can achieve the above requirements. Then, implement a low-power receiver front-end in the low-cost CMOS technology for wireless UWB applications by using the proposed behavior model. 1.2 Specifications MB-OFDM Proposal Brief In the MB-OFDM proposal, the frequency band of UWB is divided into 14 bands, in where each band has a bandwidth of 528 MHz. As shown in Table 1, the 14 bands are categorized into 5 band groups. There are 3 bands in each band group except band group 5 which has only 3

17 2 bands. A time-frequency code (TFC) is utilized to interleave coded data over up to three frequency bands in each band group. There are 122 modulated and pilot subcarriers out of a total of 128 subcarriers of MHz. The QPSK modulation signals are used in the OFDM subcarriers. The subcarrier falling at DC (0th subcarrier) is omitted. Devices operating in band group #1 are denoted as Mode 1 devices. It is mandatory for all devices to support Mode 1 operation. Supporting other band groups operation is optional and can be added in the future. The transmission spectrum shall have a 0 dbr (db relative to the maximum spectral density of the signal) bandwidth not exceeding 260 MHz, -12 dbr at a 285 MHz frequency offset, and -20 dbr at a 330 MHz frequency offset and above. The transmitted spectral density shall fall within the spectral mask, as shown in Figure 1. The average power of the transmitted signal is -9.9 dbm. There are several data rates supported for a UWB system, they are list in Table 2. For a packet error rate (PER) of less than 8% with a PSDU of 1024 bytes, the minimum receiver sensitivity numbers for the various rates are listed in Table 2. The higher data rate must have higher sensitivity since the signal to noise ratio will become small when the data rate is increased. 4

18 Figure 1 Transmitter power spectral density mask in MB OFDM proposal Table 1. Band assignment in Multi-Band OFDM proposal. 5

19 Table 2. Receiver performance requirement in MB OFDM proposal Architecture and Link Analysis Direct-conversion is adopted in the system architecture as shown in Figure 2. The bulky image rejection filters are omitted and SoC integration is more accessible with this architecture. Beside, the power consumption can be reduced. Figure 2 Direct-conversion architecture for UWB receiver. The first building block in receiver path is LNA. It is a very important component in a receiver. If the gain of LNA is large enough, the noise from circuits behind LNA can be 6

20 ignored since the signal becomes very large. The LNA affects the sensitivity of the receiver. For UWB specification, the noise figure of the receiver after antenna must be lower than 6.6 db. If the loss of switch and RF filter is 1.7 db, the noise figure after filter must less than 4.9 db. Since the bandwidth of UWB is from 3.1 GHz to 10.6 GHz, the impedance matching, the flatness of gain, and noise matching are difficult to achieve. The specification of each block in the receiving path is shown in Figure 3, and the NF link budget analysis is shown in Figure 4. The gain and NF specification of the receiver front-end which includes LNA and mixer are 22 db and 3.82 db, respectively. Figure 3 UWB receiver specifications. Figure 4 Receiver noise figure degradation. 7

21 1.3 Organization The organization of this thesis is overviewed as follows. Chapter 2 describes the design flow for RF circuit design and proposes a unified behavior model. It also demonstrates a design example of UWB LNA. Chapter 3 reveals some examples of UWB LNA in recent researches, and chooses the capacitive cross-coupling (CCC) input matching technique for the UWB LNA design. A wideband LNA with CCC technique is designed by using the proposed behavior model in Chapter 4. The wideband LNA is also used in receiver front-end for ultra-wideband application. Chapter 5 concludes with a summary of contributions and suggestions for future work. 8

22 Chapter 2 A Unified Behavior Model Design In order to improve the efficiency of circuit design, a design flow is presented in this chapter. In order to design the circuit by the proposed design flow, a unified RF behavior model combining the RF effects of input/output impedance, noise, nonlinearity and frequency response simultaneously is proposed. Section 2.1 addresses the design motivation of the design flow and the behavior model. The proposed behavior model consisting of input/output impedance and G m suitable for the proposed design flow is presented in section 2.2. A Verilog-A behavior model for an ultra-wideband CMOS low noise amplifier is developed for fast and accurate system simulation in section 2.3. The analog performances of transistor level and behavior model are compared in section 2.4. The system co-simulation environment and results are presented in section Design Motivation The design efficiency can be improved by the proposed circuit design flow and decreasing 9

23 the system simulation time. In order to reduce the time of system verification, behavior models are used in system co-simulation. In this thesis, a proposed behavior model can be used not only in the proposed circuit design flow to assist with the RF circuit design but also reduces the time of system verification. In order to design a RF circuit efficiently, a valid design flow is required. Figure 5 shows the proposed design flow. To deign a circuit block of a system, it always needs to get the system specification first. The specification can tell us useful information about the system, and we can determine the system architecture by the information from specifications. The specifications of each building block can be calculated, once the system specifications and architecture are determined. In the traditional design flow, the circuit design starts with the defined specification of each building block for system co-simulation. The design can be treated as an IP (Intellectual Property) if the design can be used in the system. Actually, the RF circuitry usually consists of several circuit modules. Each circuit module has its assignments to assist the circuit design can meet the specifications. In the proposed design flow, the RF modules can be divided into three parts: input interface, output interface and G m stage. The proposed design flow determines the specifications of each part. Than, we develop the behavior models of each part, a system simulation will be accomplished by these behavior models. If the performance can meet the system specifications, we can choose the 10

24 circuit topology by using the behavior model which has been selected. In an amplifier, the input interface acts like the input matching circuit. The output interface likes the output matching and the load of the amplifier. The G m stage is the core of the amplifier, such as common source amplifier, common gate amplifier.etc. We can build up a database of all reference designs. If the database is large enough, the proposed behavior can assist in designing a new circuit. The suitable topologies of a new target circuit which has difference specifications can be searched in the enormous database. After choosing the circuit topology by the database and optimize the circuit, if the specification can t meet the system requirement, we can replace the part which has poor performance in the circuit from the database. This method is more suitable to IP application. Each part of a building block treats as an IP, and the circuit design becomes more flexible. Analog circuit design for communication system requires different levels of parameter abstraction. There are two ways to implement design flow. A top-down design starts with behavior models using the design flow to determine the most important characteristics and gradually modify each subsystem to increase the accuracy. A bottom-up design starts with a detailed specification and determines a behavior model which can be used in system co-simulation. 11

25 Figure 5 The proposed design flow In this chapter, we focus on the development of a behavior model and system verification of an existing design, therefore we pays attention to the bottom-up design flow. The entire transceiver is verified with BER (bit-error rate) or EVM (error vector magnitude) simulation. Simulation with full-chip RF transceiver in transistor-level SPICE netlists is time consuming and very inefficient. Performing system simulation with analog/rf circuit elements prior to 12

26 chip implementation is crucial and urgent for designers in designing complicated wireless systems nowadays and facing very tight time-to-market schedule. In order to reduce the simulation time, behavior models for analog/rf circuits with accurate prediction are required in system simulation. Typical characteristics must be considered and accurately modeled in RF designs including linearity, noise, gain, and frequency response. Traditionally, these characteristics are simulated with empirical models based on measurement. For example, n-port network parameter data in Touchstone format are used to characterize frequency response and noise performance. For nonlinear effect, either Taylor series or Volterra series are used instead to describe low-frequency or high-frequency distortion. The noise/frequency response and nonlinearity distortion are modeled separately without considering the impact of each other. Several kinds of behavior model are used in the different simulation environment. In this thesis, we propose a unified RF behavior model which combines the effects of input/output impedance, noise, nonlinearity and frequency response simultaneously and reduces the overall simulation time efficiently. 2.2 The Unified Behavior Model Here, we focus on the RF building blocks of two-port network, such as amplifiers and 13

27 filters. Mixers and switches are beyond the scope of this behavior model. As shown in Figure 6, the proposed behavior model consists of three modules: input interface module (H IF,i ) for the input impedance network, core module (H Gm ) for the gain stage, and output interface module (H IF,o ) for the output load impedance. The architecture is appropriate to the design flow which described in previous chapter. In a LTI system, the transfer function of the two port network is represented by H IF,i H Gm H IF,o in the system simulation platform. Detailed modeling approach for each module is described in the following section. Figure 6 UWB system simulation block diagram Modeling of Input and Output Interfaces The input/output impedance networks of a two-port circuit shape its frequency response 14

28 and bandwidth. Though Laplace transfer function can be used to model the frequency response [4], it only defines the voltage/current transfer relation and requires additional impedance networks for the loading effect. The additional impedance networks nevertheless also shape the overall frequency response and introduce iterations in modeling. Instead of using Laplace transfer function, the proposed model employs equivalent impedance networks to portray the frequency response and the impedance matching properties of input/output interfaces at the same time. An equivalent circuit consisting of resistors, inductors, and capacitors is established to model the input matching network and the input impedance of the active device. The capacitors and inductors are used to define the reactance of H IF,i, while the resistors to define the loss including the resistor loss as well as the inductor loss and the capacitor loss. Physically, regular resistors contribute not only loss but also thermal noise. However, the equivalent resistors in H IF,i are not the actual thermal noise sources, and are intended to model the loss only. Similarly, the load impedance and the output impedance of the active device are modeled as a network of noiseless resistors, inductors, and capacitors Modeling of Gain Stage The gain stage can be simply modeled by a controlled signal source, depending on the input and output signal types of the active circuit topology. For example, it can be a 15

29 voltage-controlled current source (VCCS) for a common source amplifier or a current-controlled current source (CCCS) for a common-emitter amplifier. Since the input impedance of the controlled signal sources have been considered in the input interface module, H IF,i, and the output impedance of the controlled signal source can also be absorbed into the output load module, H IF,o, the controlled signal source in H Gm is ideal and defines the input and output voltage/current relation either linear or nonlinear Modeling of Noise The noise effects are lumped into an equivalent noise source instead of a noisy resistor as [4]. Hence the RF effects are modeled incrementally with iteration reduced. The noise effects of a two-port network are modeled by three equivalent noise sources i n,if,i, i n,gm and i n,if,o for the input interface, core and output interface modules, respectively. For easy extraction of noise and model consistency, i n,if,i, i n,gm and i n,if,o are all placed at the output node of each module. The explicit input noise source of the active device, for example, is absorbed to i n,if,i in the preceding module. 16

30 2.2.4 A Simple Example of the proposed Behavior Model Figure 7 A simple model of common-source amplifier Figure 7 shows a simple model example of common-source amplifier. The G m stage of this model which can determine the gain and the nonlinearity is the type of VCCS due to the common-source topology. Input interface is defined by a resistor and a capacitor, and the output interface is defined by a resonance tank for RF application. The noise sources i n1 and i n2 are placed at the output of the input/output interface to model the noise performance of the circuit Modeling Flow A modeling flow is developed for the proposed unified RF behavior model as depicted in Figure 8. The two-port circuit is mapped into three behavior modules as mentioned above with RF characteristics relation equations in each module derived. This is a process of 17

31 abstracting the physical circuit topology into a simplified equivalent circuit and grouping the equivalent circuit elements into each module accordingly, which has a great influence on the iterations in later optimization processes. From the results of the transistor level simulation or measurement, the initial values for the model parameters in H IF,i, H Gm and H IF,o are extracted. The parameter extraction is followed by four optimization processes to fit the model parameters for RF characteristics of input and output impedance, frequency response, noise and nonlinear effects in sequence. The optimization is a complex task due to the correlation among the RF characteristics, and therefore proceeded incrementally by considering the noise and nonlinear effects. That is, for small input signal condition, the two-port circuit is regarded as a noiseless linear circuit in the first two optimization procedures and then a noisy linear circuit in the noise optimization. On the other hand, the circuit is considered as a noisy weak nonlinear network in the final optimization procedure. For reverse isolation concern, more iterations are required in the non-unilateral cases. The optimal model parameters are obtained if the root mean square error (RMSE) is smaller than a threshold value. Ultimately, a system simulation is performed to verify the accuracy and feasibility of the RF behavior model. 18

32 Figure 8 Unified behavioral modeling flow. 2.3 Design Example of UWB LNA In this section, a behavior modeling example of a wideband CMOS low noise amplifier for ultra wideband applications is presented according to the above modeling procedure. 19

33 The targeting UWB LNA was fabricated in 0.18-µm CMOS technology and the circuit schematic is illustrated in Figure 9. The LNA employs stagger tuning technique, which consists of two stacked common-source stages with different resonance frequencies [5]. The output buffer in Figure 9 is for measurement purpose only and omitted in the behavior model. The behavior model of the UWB LNA contains three interface modules, H IF,i, H IF,c and H IF,o, and two G m -core modules, H Gm,1 and H Gm,2, mapping the two amplification stages as shown in Figure I/O Interface A simple RLC parallel network can be used to model the interface modules for narrow band circuits. To model the input band-pass matching network and the input impedance of transistor M1 of the UWB LNA, ideal lump elements L 1,L 2,L 3,C 1,C 2,C 3 and R 1 are used in H IF,i. H IF,c and H IF,o add R C4, R L4, R C5, and R L5 in the RLC parallel network due to the low-q loads of the wide-band amplifier. It should be noted again that all resistors framed in Figure 10 are noiseless G m Core In an N-stage amplifier, N numbers of G m -core modules are exploited regardless its 20

34 topology. The partition of the RF behavior model is determined by the critical impedance components which contribute the poles or zeros in the frequency response of the RF circuits. Two G m cores G m,1 and G m,2, as a consequence, exist in the behavior model and their initial values are extracted from the small-signal transconductance values of transistors M 1 and M 2. Combining H Gm,1 and H Gm,2 with H IF,i, H IF,c, and H IF,o, the frequency response is optimized to portray the noiseless linear characteristic of the UWB LNA. Figure 9 Target UWB LNA circuit. 21

35 Figure 10 The UWB LNA Model Noise Sources The noise sources considered in the RF behavior model are only thermal noise contributed by the resistors and transistors of the RF amplifier while the flicker noise of MOSFET devices is not critical. The thermal noise of a MOSFET device includes gate noise and drain current noise [6]. For calculation simplicity, the drain current noise source stays in the module of G m -core and the gate noise source is, on the contrary, placed in the preceding interface module. The noise of H IF,c and H IF,o is also merged into the preceding G m -core modules. Consequently, three noise sources I n1, I n2 and I n3 are adopted to describe the noise performance Nonlinearity The UWB LNA is assumed weakly nonlinear and then modeled with Taylor series expansions for its transfer function [7]. Where x(t) and y(t) are the input and output signals. 22

36 yt () = α xt () + α x () t + α x () t + (3-1) In addition, the nonlinear effect is dominated in the second stage of the UWB LNA. Therefore, the nonlinearity is simply related to the third order coefficient (α 3 ) of Taylor series in H Gm,2 and its initial value is set to be 4 A α 3= (3-2) 3 A V 2 IIP3 2.4 Performance Results In this section, we compare the analog performance between transistor level circuit and behavior model. The Figure 11 and 12 shows the comparison results of input/output impedance (I/O interface) which include the real part and the image part. In order to predict the performance of system simulation, the input/output impedance characteristics of behavior model must be close to transistor level circuit in the pass band of the target amplifier which operates from 2.7 to 8.5 GHz. From Figure 11 and 12, we can observe that the input/output impedance between behavior model and transistor level circuit are consistency in the pass band for both real part and image part. In the pass band, the RMSE (root mean square error) are less than 1.75 Ohm and 1.59 Ohm for real part and image part of input impedance, and 0.86 Ohm and 0.82 Ohm for real part and image part of output impedance. 23

37 Figure 11 Comparison of input impedance. Figure 12 Comparison of output impedance. 24

38 Figure 13 Comparison of voltage gain and NF. The comparison of voltage gain and NF are shown in Figure 13. The RMSE in pass band is less than 0.12 db and 0.17 db for NF and voltage gain, respectively. The nonlinearity simulation of the UWB LNA is performed by a two-tone test with a MHz spacing. The α 3 was selected to be -1.8, so the input IP3 and P 1dB agree with the transistor level simulation. The α 3 is optimized in the second amplification stage, and the nonlinearity performance versus frequency has the same trend with the transistor level simulation. From Figure 14, we can find the RMSE variation of the input IP3 and P 1dB are less than 1.05 db and 0.91 db. 25

39 Figure 14 Comparison of input IP3 and P 1dB in the frequency band of interest. Figure 15 Comparison of NF and gain with sweeping RF power at GHz. We also sweep the input power to observe the gain and NF performance at GHz. 26

40 Figure 15 shows the gain and NF are consistency if the input power is less than input P 1dB. It means that the behavioral model can be used before the large signal starts to degrade the performance. Since the input power of UWB LNA is always chosen to be small, the behavior model is suitable to the system simulation. 2.5 System Simulation Platform RF/Baseband Co-Simulation Environment Since the analog performance of behavior model agrees well with the transistor level, we replace the transistor level circuit with the behavior model in system co-simulation. Figure 16 shows the RF/Baseband co-simulation environment which is supported by the Multi-Band OFDM UWB design library in Agilent ADS platform. The Baseband Amplifier in Figure 16 is an ideal amplifier which can be used in baseband simulation environment. An analog circuit can be used in this environment for RF/Baseband co-simulation when we enable the Analog Amplifier and disable the Baseband Amplifier. The target UWB LNA can be utilized in the block of Analog Amplifier. Figure 17 shows the circuit of Analog Amplifier. We can choose either behavior model or transistor level in the block of Analog Amplifier to compare the UWB LNA system performance with the transistor level and 27

41 behavior model. The gain of the variable gain amplifier (VGA) is regulated to normalize the input power of UWB receiver. Figure 16 RF/Baseband co-simulation model. Figure 17 RF and Analog receiver behavior model. 28

42 2.5.2 System Level Performance Error vector magnitude (EVM) simulation is performed based on the platform in figure 16 with the Multi-Band OFDM UWB design library in Agilent ADS and the unified RF behavior model. Using the circuit envelope simulator, the platform allows cosimulating the baseband algorithms and RF Verilog-A models. The input signal is 480-Mbps OFDM modulated at GHz with power level sweeping from 72.8 to 27.8 dbm. The simulation results shown in Figure 18 agree well with those of the transistor-level LNA with EVM RMS error less than 0.79% and the simulation time for all power sweeps is reduced 87%. The simulation results verifies the accuracy of the unified RF behavior model and demonstrates great efficiency. The simulation time in transistor level becomes longer for the larger input power due to the nonlinearity in transistor level circuit becomes severe, and increases the iteration of the simulator. The behavior model, on the other hand, doesn t show the same increase of iteration. 29

43 Figure 18 Comparison of UWB system EVM simulation results. 30

44 Chapter 3 Capacitive Cross-Coupling UWB LNA A design example of broad band LNA with input matching using band pass filter is modeled in in previous chapter. The NF of the LNA in chapter 2 increases rapidly in high frequency, therefore the topology presented in chapter 2 is not suitable for UWB application. We propose a LNA topology which can achieve wideband matching, flat NF and gain from 3.1 to 10.6 GHz for UWB application. In this chapter, section 3.1 shows the design considerations and recent researches for wideband LNAs. The capacitive cross-coupling technique is chosen for UWB application, and we discuss this topology in section 3.2. Section 3.3 discusses the UWB LNA with CCC technique in the first gain stage. Section 3.4 shows the second gain stage of the UWB LNA. Section 3.5 discusses the performance of the overall UWB LNA with CCC technique. Section 3.6 summarizes this UWB LNA design. 3.1 Design Consideration of Wideband LNA The LNA is the first module in the receiver path, which affects the performance of signal 31

45 bandwidth and noise figure of the system directly. There are several kinds of wideband LNA design topologies proposed in these years [5], [8]-[11], [14]. A wideband LNA can be partitioned to three parts by our behavior modeling method. The optimal design topologies of the three parts can be chosen by using the proposed behavior modeling method Basic Concerns In designing a LNA, noise optimization and input impedance matching are usually more explored. In LNA circuits, noise sources close to the input have more contribution since they are amplified by the circuits and then appear at the output. That is the reason why the input network and the input devices are the main targets in noise reduction. Resistors are not good for input matching in LNA designs because they produce lots of thermal noise. While on-chip spiral inductors are widely used for impedance matching, they do generate thermal noise due to low quality factor; i.e. noticeable parasitic resistance. However, it is hard to accomplish the noise matching and input matching simultaneously especially, especially for a broadband LNA. Inductive source degeneration is widely employed for input match in the narrow-band design [7]. It provides a real term ω T L for the input impedance while generating little noise and consuming tiny voltage headroom, and the real term is independent of frequency. It is 32

46 also found in the broadband design when the input impedance is concluded in a band-pass filter [5], [8]-[9]. Common gate topology can easily achieve broadband matching. The input impedance will be 1/g m and equal to source resistor [7]. The input impedance is in series with source resistor. However, the minimum noise figure will be larger than 3 db. It s not suitable for UWB system Recent Research Reviews on Broadband LNA Figure 19 Distributed amplifier Several LNA design techniques had been reported for broadband communication applications. The well-developed distributed amplifier is known as its wide bandwidth. The wideband performance of the distributed amplifier is dependent on the same signal delay of each stage. However, as shown in Figure 19, it requires many stages to get wider bandwidth. Each stage of the distributed amplifier needs chip inductors and consumes DC power. For 33

47 UWB application, many stages consumes large area due to the many chip inductors and much power. [10]. Broadband matching can be achieved by employing common-gate topology. The drawback of common-gate is the poor noise performance. A common-gate LNA was proposed to cancel the noise contribution from the input of common-gate stage as shown in Figure 20 [11]. Shunt-peaking and stagger tuning techniques are used to have flat gain form 3.1~10.6 GHz. The noise canceling bandwidth is, however, limited when the load impedance is relative to frequency. Figure 20 A broadband noise-canceling CMOS LNA A capacitive cross-coupling technique was proposed to have the noise contribution form input MOSFETs [12]-[13], as shown in Figure 21. Since loads of the differential pair is 34

48 equivalent, the noise cancellation ability won t reduce even though the operation frequency is different. In this topology, if the noise parameter of the transistor, γ, is equal to 1, the minimum noise figure is larger than 1.76 db, and it is not good enough for some systems. V DD Z L Z L + V out - + V in - Figure 21 Capacitive cross-coupling LNA The LNA employing stagger tuning technique consists of two common-source stages with different resonant frequencies to extend the bandwidth. A current reuse topology is used in this LNA to reduce the DC power consumption. The inductive source degeneration is used together with a three-section band-pass Chebychev filter to provide broadband input match [5], as shown in Figure 22. The noise optimization used in narrow-band design is employed and in-band average noise figure is optimized. The design begins with narrow-band-like topology and results in good broadband performance. However, there are many inductors in 35

49 input matching circuit, and the chip area becomes large. Figure 22 A wideband LNA with band-pass filter for input matching Figure 23 Resistive-Feedback CMOS LNA A resistive feedback CMOS LNA is proposed to achieve DC to 8GHz bandwidth with large 36

50 gain and low noise figure [14], as shown in Figure 23. The chip area of this circuit is respectably small owing to no passive inductors in the circuit. The transistor M 3 is an active inductor, and the capacitor C PFB compensates for parasitic capacitance C L and increase bandwidth. The resistive feedback can not only provide for matching but also flat gain, but the bandwidth of resistive feedback is hard to achieve 3.1 GHz to 10.6 GHz for specification of UWB system Summary of Wideband LNAs Several LNA design techniques had been reported for broadband communication applications. Several methods to obtain wideband impedance matching, noise matching and flat frequency response described above. We summarize the techniques for wideband operation in Table 3 and wideband matching in Table 4. We can have a flat frequency response by combining more than one method in Table 3, but the matching method in a circuit must be only one. To choose a suitable topology for matching circuit can dominate the performance of the LNA. 37

51 Table 3. Flat frequency response methods. Techniques of Flat Frequency Response Shunt-Peaking Feedback Stagger Tuning Distributed Amplifier Drawbacks Consumes DC power in resistor Consumes large DC power Use more than one inductors Large area and DC power Table 4. Broadband matching methods. Topology Broadband Impedance Matching NF min NF (3.1~10.6GHz) Power Consumption Area LC-Ladder Good Good Bad Good Large Feedback Bad Good Moderate Bad Small Capacitive Cross-Coupling Common Gate with Noise Canceling Distributed Amplifier Good Bad Good Moderate Small Good Good Moderate Moderate Small Good Bad Moderate Bad Large From Table 4, we can find that the capacitive cross-coupling topology can achieve wideband matching easily with moderate DC power and small chip area consumption. Especially, this topology has a flat NF from 3.1 to 10.6 GHz. It is, therefore suitable for UWB 38

52 applications. Once the input matching topology is determined, the circuit can use the shunt-peaking and stagger tuning techniques to achieve a flat gain from 3.1 to 10.6 GHz. 3.2 Capacitive Cross-Coupling Amplifier In these years, common source and common gate gain stages are widely used in LNA design. In common-source gain stage, a source degenerate inductor can offer the resistive impedance, and the series gate inductor can cancel the capacitive impedance to achieve narrow band input matching [7]. For wideband input matching, the reactive part of input impedance must be cancelled within a wide frequency range. We can use the band pass filter, such as LC-Ladder filter which we present last section to cancel the reactive impedance over a wide bandwidth. The NF of common-source LNA will be better if the input quality factor, Q, is increased. The NF is constrained by the low Q on-wafer inductors. The common-gate gain stage can not only achieve the g m stage of an amplifier but also accomplish the input matching. The main drawback of common-gate amplifiers is the relatively high noise figure. Ignore the noise sources which generate from the passive components, a common gate LNA has the minimum noise factor [7]: Noise Factor = 1+ γ (3.1) Where γ is the coefficient of channel thermal noise. When the input impedance of 39

53 common-gate topology is matched to 50 Ohm, the NF is usually larger than 3dB. This topology is easy to perform wideband matching, but difficult to meet the noise requirement for UWB applications. The capacitive cross-coupling (CCC) can be used for input matching and gain enhancement [12]-[13]. The noise factor of an amplifier is expressed as: Total noise output Noise Factor = (3.2) Noise power@ output due to source only Since the noise sources from the MOSFETs in CCC are the same as common-gate gain stage, the gain enhancement characteristic can reduce the NF due to the output noise which is contributed from source noise becomes larger. The detail will be discussed latter. In this section, the input matching, gain and noise performances will be demonstrated. A differential common-gate input gain stage with CCC is shown in Figure 24. I n1 and I n2 are the thermal noise from M 1 and M 2. Assume that C1 and C2 are large enough and we can ignore its impedance, the small signal of Figure 24 can be simply presented as shown in Figure

54 Figure 24 Gain stage of capacitive cross-coupling technique Figure 25 Small signal model of CCC technique Let Z L1 = Z L2 = Z L, g m1 = g m2 = g m, R S1 = R S2 = R S and I n1 = I n2 = I n = 4 ktγg m, where the 41

55 Boltzmann constant k = J/K, and T is the absolute temperature. We only consider the thermal noise in MOSFETs in Figure 25. The input impedance is equal to (detailed analysis shows in Appendix): Z in 1 = (3.3) g m When g m =1/2R S, typically is 0.01 A/V, the input matching can be achieved. The voltage gain of the CCC topology is given by (detailed analysis shows in Appendix): 1 V V V 2g Z A = = = 2g Z = g out o1 o2 m L V m L Vin Vin 1 Vin2 RS + RS + gm m (3.4) The noise contribution from source noise and I n at output can be expressed as (3.5) and (3.6) (detailed analysis shows in Appendix): 1 2g R V Z kt R 1 2gm + R m S nout,, RS = 2 L 4 S S 2 (3.5) 1 R V = 2 Z 4kT γ g 1 2gm + R S nout,, In L m S 2 (3.6) The coefficient 2 in equation (3.5) and (3.6) represents the sum of the two noise sources from I n and R S in Figure 25. The noise factor can be calculated by equation (3.2): 42

56 1 RS 2 ZL 4kT γ g 1 2gm + RS Noise Factor = gm RS 2 ZL 4kT RS 1 2gm + R γ = 1+ 4 g R m S S 2 m (3.7) If the input impedance matching is considered, the g m is equal to 1/2R S, so the equation (3.7) can be represented by: γ Noise Factor = 1+ (3.8) 2 From equation (3.8), we can find that the noise contribution from the thermal noise of MOSFETs is reduced to half. The CCC technique can minimize the thermal noise from the input MOSFETs in a common-gate topology. The common-gate topology with noise canceling architecture can also cancel the thermal noise from the input MOSFETs [11], but the noise canceling ability will become poor due to the load impedance is varied with frequency. In CCC technique, the noise canceling mechanism is independent to frequency. 3.3 The First Gain Stage with CCC Technique The gain stage with CCC topology can achieve wideband matching and low noise. In order to use this topology for UWB application, the gain flatness from 3.1 GHz to 10.6 GHz must 43

57 be achieved. When the CCC technique is used in the UWB LNA gain stage, the flat frequency response methods listed in Table 3 can be employed. The proposed CCC LNA uses the shunt-peaking and stagger tuning methods to achieve the flat frequency response from 3.1 GHz to 10.6 GHz. The first gain stage is very critical for a LNA. The input matching is determined by the first gain stage, and the NF is also dominated by this stage. The CCC technique is used in the first stage owing to its excellent input matching ability and the relative low NF compared with general common-gate topologies. The CCC topology can have flat and wide frequency response if the wideband load is used. In the proposed CCC UWB LNA, we use the shunt-peaking technique to perform the wideband load, and the frequency response will be more flat than a single inductor. The Z L1 and Z L2 in Figure 24 are replaced by the shunt-peaking load, as shown in Figure 26. The R LS and L S are used as the shunt-peaking load. C P and R P are the parasitic capacitors at drain node of the MOSFETs. The parameter R P is usually the output resistance of MOSFET, r o, which doesn t generate any noise. Assume Z L1 = Z L2 = Z L, it means that all parameters in Z L1 and Z L2 are the same, the noise factor of the CCC topology can be written by equation (3.9). The noise factor is simplified to equation (3.10) when g m = 1/2R S. From equation (3.9) and (3.10), we can find that the NF of the CCC topology is independent to R P and C P. Only the shunt-peaking components affect the NF. The NF can be minimized, if the R LS and sl S are infinity. Unfortunately, the R LS and sl S in the 44

58 circuit can t be arbitrary large. The sl S is limited by the resonance frequency. The impedance of L S starts to decrease when the operation frequency is higher than the resonance frequency. The R LS is limited by the headroom of the circuit. γ Noise power@ output due to RLS Noise Factor = g R Noise output due to source m S 1 RP // scp 2 4kT RLS 1 ( RLS + sls) + RP // γ scp = gmrs 2gm 2 4kT RS ZL 1+ 2g R ZL 2 4kT RLS γ ( RLS + sls) = gmrs 2gm 2 4kT RS Z 1+ 2g R ( 1+ 2g R ) ( + ) γ R = g R 2 g R sl R 2 m m S LS m S m LS S S γ 2RLS Noise Factor = g R + sl ( ) 2 m LS S S m 2 L S 2 2 (3.9) (3.10) Equation (3.9) shows that the NF will be improved as g m increased. There is a trade-off between NF and input matching. Figure 27 illustrates the NF and input matching of the first stage vs. g m of the input transistors. The R LS and sl S are chosen to 400 Ohm and 30 Ohm in this figure. The NF improves with the increase of sl S. The L S must be larger than 1.54 nh in 3.1 GHz. This inductance is feasible for chip inductors. For input matching, the best value of g m is equal to 1/2R S, where R S is 50 Ohm. So the g m must be equal to 10 ma/v. Besides the g m, the parasitic capacitance at the input node will affect the input matching, too. Especially at high frequency, the effect of the parasitic capacitance is crucial. A parasitic capacitance is 45

59 considered at 10.6 GHz, and the comparison of the variance g m and input matching is shown in Figure 27. As shown in Figure 27, once we choose the gm value to 14 ma/v, the NF is low and S11 will less than -10 db. Figure 26 CCC technique with shunt-peaking load When the g m is determined, the size of the input transistors can be determined. Since the smaller size of transistors owning smaller parasitic capacitors, we can increase the overdrive voltage to keep g m equal to the determined value. But the higher overdrive voltage will drive MOSFETs into velocity saturation region and makes its noise performance worse. A optimal width of the input transistor must be chosen. 46

60 Figure 27 NF and S 11 v.s. g m 3.4 The Second Gain Stage Although the first gain stage employs the shunt-peaking technique to extend the bandwidth of the UWB LNA, the bandwidth is still hard to meet the further wideband frequency range for UWB specification. As a consequence, we use the stagger tuning technique to extend the bandwidth. The schematic of the second stage is shown in Figure 28. The load of the second stage is equal to the first stage. The C P2 and R P2 are the parasitic capacitance and resistance at the output of the second stage. The R LS21 and L S21 are the shunt-peaking load for extend the bandwidth. 47

61 Figure 28 The second stage of the UWB LNA. The second stage has the differential pair with current source, I S2, which is performed by a NMOS transistor. There are some advantages in this topology. First, the noise contribution from the MOSFETs in the first stage can be reduced to half if the circuit is perfect matched. If the circuit mismatch occurred in the first stage and the second stage, the gain of the UWB LNA will decrease, and the noise contribution from the MOSFETs in the first stage will be larger than γ. When we cascade gain stages, the 2 mismatch will become more serious. The ideal current source has infinity output impedance. When the current source is connected by the source of the differential pair, the source of the differential pair can be considered as virtual ground. The signal in each output of the second 48

62 stage has the component which is relative to V in2 + - V in2 -. The result means that the noise contribution from the MOSFETs in the first stage is determined in the second stage. The noise contribution from the input MOSFETs is only influenced by the mismatch due to the first and the second stages. The mismatch from the latter stages, like mixer, buffer, VGA or filter won t affect the noise canceling advantage by CCC technique. Second, the current source can bias the differential pair. Without the use of current source, there are two methods to bias the differential pair. One is to use the DC block to isolate the first and the second stage, and to bias the differential pair directly. The DC block must be implemented by the on-chip MIM capacitors. It must have some loss when the non-ideal capacitor is used to the DC block, the impedance of the non-ideal capacitor is not zero. In order to minimize the impedance of the MIM capacitor, the capacitor must be big enough. A problem occurs when the DC block is chosen as a large MIM capacitor, the parasitic capacitance becomes larger. The gain will be reduced at high frequency when the parasitic capacitance increased. There is another method to bias the differential pair. We can use the output voltage of the first stage to bias the differential pair. The drawback of this method is that the gate voltage of a MOS transistor is very sensitivity. Since the shunt-peaking technique is used in the load of the first stage, the problem becomes more serious. Because of the variation in the chip resistor is serious, the output voltage of the first stage has level shift when the load resistor is changed. The current of the differential pair may become much 49

63 larger or much smaller due to the variation of the resistor. The differential pair bias by the current source can overcome above disadvantages. Since the current source fixed the DC current of the differential pair, the source voltage of the differential pair is allowed to variation in a range. The variation of the load resistor in the first stage won t influence the bias of the differential pair. Although the output voltage of the first stage is variable, the V gs of the differential pair is fixed due to the flexible source voltage since the DC current is fixed by the current source. The second stage is not sensitive to the output of the first stage, and the linearity of the second stage becomes better. The DC block does not be used in this bias method. The first stage and the second stage can be connected directly. For the stagger tuning technique, the linearity is determined by the latter stage. It is a good advantage since the linearity is determined by the second stage. 3.5 The Overall UWB LNA with CCC Technique After understanding the characteristics of the first stage and the second stage, we can start to design the UWB LNA. The overall UWB LNA with CCC technique for input matching is shown in Figure 29. The bias tee is used to provide the dc current path and the ac signal path to M 11 and M 12. After cascading the first stage and the second stage, the noise factor and gain can be 50

64 expressed in equation (3.11) and (3.12). The effect of C 1, C 2, L in1 and L in2 are omitted in (3.11) and (3.12), and we assume that L S11 = L S12 = L S1, R LS11 = R LS12 = R LS1, L S21 = L S22 = L S2, R LS21 = R LS22 = R LS2. The g m1 is the transconductor of M 11 and M 12, and g m2 is the transconductor of M 21 and M 22. γ 2R 2γ 2R Noise Factor = LS1 2 LS gm 1 ( RLS1+ sl 1) gm 1gm2Z S L1 gm 1gm2ZL1( RLS2 + sls2) (3.11) A = g Z g Z (3.12) V m1 L1 m2 L2 Where γ 1 and γ 2 are the coefficient of channel thermal noise of M 11, M 12 and M 21, M 22. Figure 29 The overall UWB LNA with CCC technique for input matching. In equation (3.11), the parasitic capacitance won t affect the noise contribution from the 51

65 first stage, but it will increase the noise contribution from the second stage. It is because the voltage gain is decreased in high frequency due to the effect of the parasitic capacitances. The noise contribution from the second stage will be relative large if the gain of the first stage becomes smaller, and the NF will become poor. Equation (3.11) also tells us when sl S1 and sl S2 increased, the NF will be improved. The impedance of an ideal inductor will increase when the frequency is raised. Unfortunately, a practical inductor has resonance frequency due to the parasitic capacitor. When the operation frequency is higher than the resonance frequency of the inductor, the inductor will become to capacitive. The impedance of the inductor is no longer increased with the raised frequency. Since the NF will become poor in high frequency, we can choose the L S1 and L S2 which resonate at high frequency. The best resonance frequency is setting to the highest frequency of the UWB specification because the inductor has the largest impedance in the resonance frequency. The inductors can provide the gain of the UWB LNA in high frequency, and the gain in low frequency will be improved by the series resistors. 3.6 Summary In this chapter, the CCC technique is used to perform a LNA for UWB application. It has good noise performance from 3.1 to 10.6 GHz. The performance is suitable for UWB system. 52

66 A UWB LNA with CCC technique will design by using behavior model in next chapter. And it will be used in UWB receiver front-end. 53

67 Chapter 4 Receiver Design by Using Proposed Behavior Model The analysis of capacitive cross-coupling (CCC) LNA is described in the previous chapter. In this chapter, a design example for UWB LNA with CCC matching technique starts with behavior model is described. Section 4.1 discusses the structure of a coarse behavior model of CCC LNA. Section 4.2 discusses how to design a CCC LNA by using the behavior model, and modified the behavior model after the transistor level circuit is performed. Section 4.3 discusses the concept of receiver front-end. Section 4.4 explains the design of mixer. The simulation results of the receiver front-end are shown in Section 4.5. Section 4.6 shows the measurement consideration and environment. Section 4.7 summarizes this receiver front-end design work. 4.1 Construct a Coarse Model of CCC LNA A coarse behavior model can be easily constructed for a UWB LNA with CCC technique in 54

68 Figure 30. The structure of the behavior model is discussed as follows Input Interface We simply use the single input structure to simulate the differential pair of CCC topology. Input interface is easily presented by a parasitic capacitor and a resistor. Equation (3.3) presents the real part of input impedance only, the parasitic capacitance must be considered in high frequency and wideband condition. For differential input, the input impedance is equal to 1/g m1 for 100 Ohm input matching. Since the single input replaces the differential input, the input resistor R in in figure 30 is selected to 1/2g m1 for 50 Ohm impedance matching, and the value of C in is considered by the pad capacitor and C gs1, where g m1 and C gs1 are the transconductor and gate-source capacitor of the input transistor. Figure 30 The behavior model of UWB LNA with CCC technique 55

69 4.1.2 Gain Stage In order to obtain the flat frequency response, the stagger tuning technique is used in this circuit. There are two gain stages and three interfaces in this LNA. The first gain stage, H Gm,1, is CCC topology, which has common-gate and common-source characteristics simultaneous. In this model, we use the voltage controlled current source (VCCS) with positive gain to exhibit the gain of the first stage. The second stage, H Gm,2, is a simple common-source differential pair, a VCCS with negative gain can exhibit it. In order to maintain the gain to equation (3.4), the value of G m1 is chosen to 2g m1, and the value of G m2 is chosen to the g m of the differential pair Center and Output Interfaces The center and output interface are relation to the frequency response, and the output interface is also relation to output impedance. In order to achieve flat frequency response, shunt-peaking technique is used in center and output interfaces. In equation (3.11), the inductors of these two interfaces are chosen to resonant at high frequency due to achieve the flat NF in pass band. The parameters L S1, R LS1, C LS1, and L S2, R LS2, C LS2 are the parasitic parameters of inductors in the center and output interfaces. The parameters of R S1 and R S2 are chosen to extend the bandwidth of the load. We consider the parasitic capacitance, C P1 and 56

70 C P2, at the center and output interfaces. The best value of C P1 and C P2 can resonant with L S1 and L S2 at high frequency. The resistors of R S1 and R S2 provide the gain in lower frequency, and the L S1 and L S2 provide the gain in higher frequency. The frequency response can become flat from 3.1 GHz to 10.6 GHz Noise Sources The noise source in this model is different than that of the model in chapter 2. In chapter 2, the passive components in the model provide no noise, and use three noise sources to fit the noise performance. That is the method to model an existed circuit. In this chapter, we construct a behavior model first and using this behavior model to design a circuit. We must place the noise sources by physical viewpoint. The resistors, R S1, R LS1, R S2 and R LS2 generate noise power with value 4kTR. A noise source is placed at input, which retain to the NF like to equation (3.7). The noise source is chosen to 4kT/g m1. The noise source from differential pair is chosen to 4kTg m Design a CCC LNA After constructing and fine tune the coarse behavior model of CCC LNA in previous section, we can design the transistor level circuit. The coarse behavior model determines the 57

71 components parameters of transistor level Performance Comparison between the Coarse Behavior Model and Transistor Level Section shows the comparison of transistor level/behavior model. To achieve suitable input matching and good NF, the transconductors of the input transistors are chosen to 14.5 ma/v. After choosing the devices size from the coarse behavior model, the results are presented in figure 31. The UWB LNA is simulated with an ideal differential to single output buffer. In figure 31, we can find that the input matching results between behavior model and transistor level have different trends. There are some critical points which we didn t consider in input matching circuit. The input impedance can t be presented by a resistor and a parallel capacitor only. In the transistor level, input matching become worse at high frequency, we can add the series inductors at input to cancel the capacitive effect, and the S 11 will be large than -10 db. Besides the input matching, the estimated parasitic capacitance in the coarse model is smaller than transistor level. 58

72 Figure 31 Simulation results of Behavior Model and Transistor Level, (a) voltage gain, (b) S 11, (c) noise figure Modify the Behavior Model From figure 31 (b), we can find that there is a low-q resonance tank at 3 GHz. The information reveals that the inductance impedance appears in the input matching circuit. The impedance between drain and source of input transistors, C ds and r O, are not considered in 59

73 figure 25. These impedances provide a feedback loop between input and output of the first gain stage. After considering the impedances, the input impedance can be modified by: ZL Zin = 2 ( 1/ scds) + ( 1/2gm) + ro + 2 ro sc ds sc r + 1 ds O 1 + 2gm + ro (4.1) The first term of (4.1) can be approximated to 1/2g m since this impedance is relative small than others. Besides the term of 1/2g m, equation (4.1) shows that an impedance series to 1/2g m. From figure 31 (b), we can speculate that this term reveals the inductance impedance. Figure 32 Active inductor, (a) schematic, (b) small signal circuit. Figure 32 is the active inductor [15]. Assume R >> 1/g ml, Z out can be approximate to: Z out srcgs + 1 sc + g gs ml (4.2) where C gs and g ml are the gate-source capacitance and transconductor of the transistor. The values of the small signal circuit can be present to: 60

74 R = R 1/ g 1 R = 1/ g 2 ml ml ml Cgs L = R g g ( 1/ ) ml (4.3) Compare (4.2) with the second term of (4.1), we can find the second term of (4.1) has the component of inductance impedance. To contrast between (4.2) and the second term of (4.1), the parameters in the second term of (4.1) can be presented to: C r O ds C R gs 2g + 1/ r g m O ml (4.4) Unfortunately, the active inductor in (4.1) has a coefficient Z L /r O which is relative to the frequency. And we can t reveal this phenomenon by the simple RLC circuit. In order to express this phenomenon, the 1/2g m is series to a low-q inductor which value must be optimized to fit the S 11 of the transistor level. Figure 33 The proposed CCC LNA 61

75 Since the S 11 in figure 32 (b) can t meet specification (< -10 db) at high frequency, a series inductor can be placed at the input to cancel the capacitance impedance at high frequency and improve the input matching. The final circuit of the CCC LNA is shown in figure 33, and the modified behavior model is shown in figure 34. Figure 34 The modified behavior model of UWB LNA with CCC technique After fine tuning, the results between the modified behavior model and transistor level are shown in figure 35. We can find that the input matching of the behavior model can fit the transistor level when the low-q inductor is series to 1/2g m1. The input return loss is improved due to the series inductors, L in1 and L in2. The NF of transistor level is poor than behavior model at low frequency. It is because the behavior model only considers the thermal noise from the transistors and the series resistors. Other noise sources, like the gate noise and flicker noise of the transistors are not considered in behavior model due to design simplicity, and these noise elements are not the critical noise source for the NF performance in UWB system. 62

76 The analog characteristics of the transistor level can be fitted by the modified behavior model and can be used for system verification which mentions in chapter 2. The pre-simulation result of the UWB LNA is shown in Table 5. In Table 5, we can observe that the LNA can meet the specification in Figure 1. We can use this LNA to UWB application. Figure 35 Simulation results of the modified Behavior Model and Transistor Level, (a) voltage gain, (b) S 11, (c) noise figure. 63

77 Table 5. Pre-simulation results of the UWB LNA with CCC technique. Spec. CCC LNA (Pre-Simulation) Technology μm CMOS Power supply V Bandwidth 3.1 ~ 10.6 GHz 0.5 ~ 10.6 GHz Power consumption mw without buffer Voltage Gain 19 db 23.5 ~ 25.3 db S 11 < -10 < -11 db NF (3.1~10.6 GHz) < 3.7 db 2.72 ~ 3.53 db 4.3 UWB Receiver Design with CCC LNA A wideband differential LNA needs wideband RF differential to single output buffer for measurement purpose. Because the wideband RF differential to single output buffer is difficult to implement, we add the mixer to down-converter the signal to lower frequency. And a baseband transformer can be used to transfer the differential signal to single-end signal at low frequency. The system architecture is shown in figure 1. Since this circuit is designed for on-wafer measurement, the quadrature modulation can t be measured in this environment. The quadrature modulation is not used in this design. The direction-conversion architecture is used in this system. The advantages of direction-conversion architecture are presented in chapter 1.2. Here, we discuss the issues of 64

78 this architecture, such as DC offsets, even-order distortion, and flicker noise. The I/Q mismatch is also an issue of direction-conversion, since the quadrature modulation is not used in this design, we don t discuss the problem in this thesis DC Offset When the downconverted band extends to zero frequency, extraneous offset voltages can corrupt the signal and saturate the following stages. The main cause of DC offsets is the strong LO signal leaking to RF port through capacitive and substrate coupling and causing the self-mixing leaking as shown in Figure 36. The problem of offset gets worse if self-mixing varies with time. This happens when the LO signal leaks to the antenna and is radiated and subsequently reflected from moving objects back to the receiver. There are various means of offset cancellation. High pass filtering or capacitive coupling can be a good solution for wideband channels that contain little energy near DC. In the MB OFDM proposal, the subcarrier falling at DC (0th subcarrier) is not used, and the lower corner frequency can be higher than 2 MHz. 65

79 Figure 36 Self-mixing of (a) LO signal, (b) a strong interferer Even-Order Distortion Suppose two strong interferers close to the channel of interest enter the LNA, the second order intermodulation distortion of the LNA will induce a low-frequency beat at the LNA output as shown in Figure 37. The mismatch of differential switching transistor pair results in direct feedthrough from the RF input to the IF output which corrupts the baseband signal. The RF port of the mixer also suffers from the same even order distortion effect. To mitigate the even order distortion, the LNA and mixer should present good second-order nonlinearity performance characterized by the second-order intercept point (IP2). Since the input of our CCC LNA is differential topology, and the second-order nonlinearity performance is, 66

80 therefore, good. Figure 37 Effect of even-order distortion on interferes Flicker Noise Since the downcoverted spectrum extends to zero frequency, the 1/f noise of devices significantly corrupts the baseband signal. This is a severe problem in the circuits employing MOSFETs. Several means may be applied to reduce the flicker noise in the receiver. In baseband circuits, the PMOS devices can be used to lower 1/f noise. Devices with larger size also help. An on-chip AC coupling capacitor between the LNA and the succeeding mixers can effectively prevent the 1/f noise at the LNA output from entering the mixers. 67

81 4.4 Mixer Design A down-conversion mixer is used to convert the RF frequency to IF frequency. In the direct-conversion receiver structure, zero IF is required in the design. A double-balance passive mixer is used in this receiver front-end [16]. The passive mixer can be easily used in wideband application. The conversion gain of this passive mixer is equal to: 2 π T T Gc = sin π T T (5.3) where T is the equivalent turn-on time of the switch pair of the passive mixer, and T is the LO period. The conversion gain can increase due to the reduced equivalent turn-on time. When T <0.6T, the conversion gain becomes positive. An output buffer is designed for measurement purpose. A source follower topology is utilized in this buffer. The passive mixer and output buffer are shown in Figure 38. Figure 38 (a) Double-balance mixer, (b) output buffer 68

82 4.5 Simulation Results A UWB receiver front-end is performed by previous design consideration. The circuit layout of the UWB receiver front-end is shown in Figure 39. The area of this circuit is 1.1 mm 2, and the core area of this circuit is less than 0.5 mm 2. The results of post layout simulation are shown in figure 40 to 45. The conversion gain decreases and the NF increases with the increase of signal frequency higher than 8 GHz. The result is due to the parasitic capacitance of the circuit layout. The conversion gain and NF can be more flat with smaller inductors and resistors in the shunt-peaking load. There are some constraints for conversion gain and NF as shown in equations (3.11) and (3.12). The conversion gain and NF degrade with the reduction of the load. In order to meet the UWB system specs. in figure 2, the load values are chosen to meet the requirement of the conversion gain. The output buffer reduces the conversion gain of 7 db in this design. In SoC design, the output buffer is not used in the system. After compensating the loss of the output buffer, the conversion gain can meet the specification. In figure 41, when the IF frequency is near low frequency, the NF becomes higher which is due to the flicker noise. Input and output return losses are shown in figure 42 and 43. In pass band, the input return loss is less than db and output return loss is less than db. 69

83 Figure 39 Circuit Layout of the UWB receiver front-end with CCC technique Spec. 15dB Figure 40 Conversion Gain 70

84 NFdsb [db] Spec. 3.82dB Figure 41 Noise figure Spec. -10dB GHz Figure 42 Input return loss 71

85 Figure 43 Output return loss Figure 44 Input IP3 and P1dB 72

86 The IIP3 and input P1dB are shown in figure 44. In higher frequency, the circuit has better linearity, because the gain of the first stage of LNA is dropped in high frequency. Figure 45 Input IP2 In order to observe the performance of the second order distortion, we assume that there has 1% mismatching in the differential pair of the receiver front-end. And the results is shown in figure 45. The comparison results are shown in table 6. The proposed receiver front-end with CCC technique has a flat NF from 0.5 GHz to 10.6 GHz while consume power of 11.4 mw in CMOS 0.18μm fabrication. 73

87 Table 6. Comparison results Parameters Spec. This Work RFIC 2005 ISSCC 2006 Post-Simulation pp.343 [17] pp.128 [18] Technology um CMOS 0.25 um SiGe BiCMOS 0.18 um CMOS Power supply V 2.7 V 2.3 V Bandwidth 3.1 ~ 10.6 GHz 0.5 ~ 10.6 GHz 3.1 ~ 10.6 GHz 3.1 ~ 8 GHz Power 11.4 mw -- consumption without buffer 83.7 mw mw Conversion Gain ~ 21.6 db 20.6 ~ 21.8 db 12 ~ 22 db IIP ~ dbm IIP3 : IIP3 : -2.6 dbm IIP ~ dbm 29 dbm 33 dbm S11 < -10 < db < -10 db (3.8 ~ 6.6 GHz) < -5 db NF < ~ 4.6 db 4.1 ~ 6.2 db NF DSB NF DSB Circuits LNA + Mixer LNA + Mixer LNA + Mixer 5 ~ 6.5 db LNA + Mixer + Filter Architecture -- Homodyne Homodyne Heterodyne 4.6 Measurement Plan The receiver front-end is designed for on-wafer measurement. The RF differential input circuit is hard to measure, especially for wideband circuit. A wideband single to differential balun must be used for measurement. Figure 46 shows the measurement environment setting. Except the single to differential balun, the bias tees must be used at input, and the DC blocks are required for the input of LO. 74

88 The single to differential balun for RF input and LO input and differential to single transformer for IF output are shown in Figure 47. A broadband balun, Model 5230B, which can operate from 5 khz to 11 GHz, can be used at the input to provide the differential input signal in this circuit as shown in Figure 47 (a). The rate race coupler is used for single to differential balun of LO input as shown in Figure 47 (b). This technology can be used in narrow band. For UWB receiver front-end, each LO frequency of balun is required. The phase error of this balun can be tuned less than 1. The ADT4-6WT differential to single transformer can be used in IF output. The receiver front-end can be measured with the proper balun and transformer. The input balun will affect the gain and NF of the receiver front-end. A method can de-embedding the effect of input balun is discussed in [19]. Figure 46 Measurement Environment 75

89 Figure 47 (a) Model 5230B, (b) rate race coupler (c) ADT4-6WT 4.7 Summary The proposed behavior model can be used to assist circuit design. Since the circuit is designed by using the behavior model, the behavior model can be modified by the circuit of transistor level. And it can be used for system verification. A design example of UWB receiver front-end with CCC technology is demonstrated in this chapter by using behavior model. 76