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1 路 路 羅 立 論 了兩 類 類 切 行 類 了 切 行 路 聯 列 量 流 益 益 數 率 率 益 益 I

2 Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University Abstract In this thesis, two groups of dual band receiver are designed and fabricated. The first group consists of switched mode and parallel mode. The other group is composed of concurrent mode and wideband mode. The circuit design comprises 2.4 GHz and 5 GHz dual band receiver frontend for switched mode and parallel mode, and 2.4/5 GHz dual band receiver frontend for concurrent mode as well as wideband mode LNA. The chip implementations include a 5.25 GHz receiver frontend and a concurrent dual band LNA employing UMC 0.18µm 1P6M mixed-mode/rf CMOS process, RF device models, and QFN series package provided by Giga-solution and SPIL respectively. The experimental results show that the receiver drains 30 ma of current and achieves the voltage gain of 18 db, P1dB of -27 dbm, IIP3 of -12 dbm, IIP2 of -3 dbm, and NF of 6.4 db. The LNA has a power gain of 6.7 db at 2.4 GHz band, -7.2 db at 5 GHz band having power dissipation of 18 mw, while the maximum power gain of this LNA is 11.9 db at 2.74 GHz, -5.1 db at 5.25 GHz due to the shift of input matching. II

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4 Contents.I Abstract......II..III Contents...IV List of Tables.... VI List of Figures..... VII Chapter 1 Introduction Chapter 2 System Planning Standard Overview IEEE a IEEE b IEEE g Comparisons From Standard to System Specification Standard Requirement Design Parameters From Receiver Specification to Circuit Specification...17 Chapter 3 Receiver Architecture Switched Dual Band Architecture Comparisons of Receiver Architectures Concurrent Dual Band Architecture..36 Chapter 4 Device Characteristic and RF Modeling Device Characteristic Technology Comparisons RF Modeling MOSFET Modeling Noise Modeling Modeling of Passive Devices...58 Chapter 5 Circuit Design Low Noise Amplifier.71 IV

5 5.1.1 Topologies Power matching Noise matching Stability Mixer Active Mixer Passive Mixer Switched Dual Band Receiver Concurrent Dual Band Receiver Wideband LNA...91 Chapter 6 Chip Implementation Layout Consideration ESD Protection Package and Modeling Chapter 7 Measurement Testing Plan Matching Measurement Power Measurement Noise Measurement Experimental Results Packaged 5 GHz Band Receiver On-wafer 5 GHz Band Receiver Concurrent 2.4/5 GHz Dual Band LNA Discussion Chapter 8 Conclusions Conclusions Future Work Appendix-A Package Data Sheet Appendix-B PCB Data Sheet Bibliography V

6 List of Tables Table 2-1 WLAN standard overview Table 2-2 Receiver specification of IEEE a standard Table 2-3 Noise Figure versus Data Rate Table 2-4 IIP3 versus Data Rate Table 2-5 IIP2 versus Data Rate Table 2-6 System specification summaries Table 2-7 Receiver link budget calculation Table a/b/g receiver front-end specifications Table 5-1 The comparisons between common source and common gate topologies--73 Table 5-2 Comparisons of some published LNAs at 5 GHz ranges [17] Table 5-3 Comparisons between published papers and concurrent dual-band LNA --88 Table 5-4 The summaries of simulation between switched and concurrent dual-band receiver Table 5-5 Comparisons of the ideal and practical wideband LNAs Table 7-1 Comparisons between simulation and measurement of 5 GHz receiver frontend VI

7 List of Figures Fig. 2-1 Channel allocation and power levels of the IEEE a standard within the UNII band Fig. 2-2 IEEE a data rate versus modulation Fig. 2-3 IEEE b channel location for 2.4GHz ISM band Fig. 2-4 Receiving band distribution of WLAN in the range of 2.4~6 GHz Fig. 2-5 Adjacent channel rejection example Fig. 2-6 (a)ip3 curve (b)desired signal corrupted by third order intermodulation Fig. 2-7 Interference specification in WLAN b receiver Fig. 2-8 Out-of-band emission specification in WLAN b receiver Fig. 2-9 Out-of-band blocking specification in WLAN b receiver Fig Intermodulation specification in WLAN b receiver Fig Behavior simulation of a standard Fig Behavior simulation of b/g standard Fig. 3-1 Switched dual-band receiver (a)switched mode (b)parallel mode Fig. 3-2 Dual-IF heterodyne receiver Fig. 3-3 (a)image problem (b)the function of image reject filter Fig. 3-4 Conceptual architecture of a switched dual-band receiver [16] Fig. 3-5 (a)simple direct-conversion receiver (b)direct-conversion receiver with quadrature downconversion Fig. 3-6 DC offsets in direct conversion receiver Fig. 3-7 DC offset cancellation techniques Fig. 3-8 Effect of even-order distortion Fig. 3-9 Signal constellations due to gain and phase mismatch Fig Effect of I/Q phase imbalance on demodulated QPSK data Fig Power spectral density of flicker noise Fig The proposed switched dual-band architecture Fig Hartley image-reject receiver Fig Weaver image-reject receiver Fig Dual-band implementation of the Weaver architecture [13] Fig Dual-band direct-conversion architecture (wideband mode) [15] Fig Evolution process of two parallel receivers to a concurrent dual-band receiver [11] VII

8 Fig An architecture for the concurrent dual-band receiver employing image rejection [11] Fig Frequency-domain signal evolution of the concurrent dual-band receiver in Fig [11] Fig Evolution process of concurrent dual-band direct-conversion receiver Fig Block diagrams of concurrent dual-band direct-conversion receiver (concurrent mode) Fig Downconversion operation of concurrent dual-band direct-conversion receiver Fig. 4-1 The definition of ft Fig. 4-2 The definition of fmax Fig. 4-3 Comparison of ft and fmax versus Collector/Drain current and voltage[29]-47 Fig.4-4 The illustration of thermal noise Fig.4-5 The model of thermal noise Fig. 4-6 The illustration of shot noise Fig. 4-7 The illustration of shot noise Fig. 4-8 The characteristic of flicker noise Fig. 4-9 (a)noise model of BJT (b)noise model of MOSFET Fig Gain-to-DC power ratio plotted versus noise figure for 2-GHz LNA [29]--52 Fig Linearity versus DC power for 2-GHz LNA [29] Fig (a)distributed transmission line effect on the gate (b)channel induced gate resistance Fig Elmore non-quasi-static equivalent circuit Fig RF N/P MOSFET extension model of UMC 0.18µm mixed-mode/rf CMOS process Fig An equivalent circuit to illustrate the noise source in a MOSFET Fig Equivalent circuit of a well resistor Fig Layout and equivalent circuit of N+/P+ non-salicided poly resistor in UMC 0.18 m mixed-mode/rf CMOS process Fig Circuit model of resistors Fig Vertical cross section of a poly-poly capacitor structure Fig (a)top view of a fringe capacitor with fractal geometry and equivalent lumped circuit model (b)cross-section view of fringe capacitor using five metal layers Fig Cross section view of general MIM capacitor with equivalent circuit model VIII

9 Fig Cross section view of MIM capacitor with equivalent circuit model by UMC 0.18m CMOS process Fig Capacitance-voltage characteristics and circuit model of MOS capacitor--65 Fig Layout and equivalent model of spiral inductor Fig The illustration of eddy current Fig Two-layer stacked inductor [16] Fig Patterned ground shield Fig Monolithic transformer (a)physical layout (b)schematic symbol Fig (a)planar transformer layout (b)transformer model Fig Stacked transformer [17] Fig. 5-1 Commonly used single-band CMOS LNAs (a)common-gate (b)common-source with inductive degeneration Fig. 5-2 Inductively degenerated LNA Fig. 5-3 Trade off between power matching and noise matching Fig. 5-4 (a)single balanced mixer (b)double balanced mixer Fig. 5-5 Passive mixer Fig. 5-6 (a)time varying conductance model for passive mixer (b)thevenin model of (a) Fig. 5-7 Topologies of receiver frontend in this design Fig and 5 GHz LNA circuits Fig. 5-9 S-parameter and noise figure simulation of switched dual-band LNA Fig Compromise between gain and NF simulation of switched dual-band LNA Fig Stability factor of switched dual-band LNA Fig Linearity simulation of switched dual-band LNA Fig The simulation of 5 GHz mixer Fig Simplified receiver circuit Fig The simulation of switched dual-band receiver circuit Fig NF simulation of switched dual-band receiver circuit at IF=5 MHz Fig Simplified concurrent dual-band LNA Fig The S-parameter and NF simulation (concurrent dual-band LNA) Fig The input matching of differential RF and LO port (concurrent dual-band receiver) Fig The gain and P1dB simulation (concurrent dual-band receiver) Fig NF simulation of concurrent dual-band receiver at IF = 5 MHz Fig IP3 and IP2 simulation of concurrent dual-band receiver Fig The ideal wideband LNA covering 2.4 and 5 GHz IX

10 Fig Matching techniques of a wideband LNA Fig The S-parameter and NF simulation of the ideal wideband LNA Fig IP3 simulation of the ideal wideband LNA Fig Capacitor-tapped impedance transformation technique Fig The practical wideband LNA covering 2.4 and 5 GHz Fig S-parameter & NF simulation of the practical wideband LNA Fig IP3 simulation of the practical wideband LNA Fig. 6-1 Fabricated circuits in this thesis Fig. 6-2 Common centroid layout Fig. 6-3 (a)5ghz receiver frontend (packaged) (b)2.4/5ghz dual-band LNA(packaged) Fig. 6-4 Parasitic effects caused by microstrip discontinuities Fig. 6-5 The PCB layout technique Fig. 6-6 The EM simulation of a 180 balun Fig. 6-7 The phase and impedance measurements of a 180 balun Fig. 6-8 Board design of (a)5ghz receiver frontend (b)2.4/5ghz dual-band LNA Fig. 6-9 ESD protection circuits Fig I-V characteristic of gate-grounded NMOS Fig Package model Fig Pin-to-Pin isolation for package model Fig. 7-1 Measurement environment Fig. 7-2 Matching measurement setup Fig. 7-3 Power measurement setup Fig. 7-4 (a)the comparison between the two measurement conditions for packaged 5 GHz Rx (b)the comparison between the two measurement conditions for on-wafer 5 GHz Rx Fig. 7-5 Noise measurement setup Fig. 7-6 Gain & P1dB measurement of packaged 5 GHz receiver Fig. 7-7 (a)ip3 measurement of packaged 5 GHz receiver (b)ip2 measurement of packaged 5 GHz receiver Fig. 7-8 Noise figure measurement of packaged 5 GHz receiver Fig. 7-9 (a)rf port matching of differential 5 GHz receiver (b)lo port matching of differential 5 GHz receiver Fig Gain&P1dB measurement of on-wafer 5 GHz receiver X

11 Fig (a)ip3 measurement of on-wafer 5 GHz receiver (b)ip2 measurement of on-wafer 5 GHz receiver Fig Noise figure measurement of on-wafer 5 GHz receiver Fig S-parameter measurement of concurrent dual band LNA Fig Bond wire used as source inductor of LNA Fig Inductance of two wires as a function of spacing Fig Layout issues of on-wafer 5 GHz receiver Fig. 7-17(a) 3-port inductor (b) Monolithic transformer Fig Device modeling flow Fig. 8-1 IP-revise design mythology proposed in this thesis Fig. 8-2 The interconnection between 5 GHz receiver and 5 GHz synthesizer Fig. 8-3 The measurement of connecting 5 GHz receiver and 5 GHz synthesizer design Fig. 8-4 Embed VCO into receiver frontend XI