Section1_16bit Arc.ppt

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16-bit Elite Program 2009 Summer Section-1 Microchip 16-bit

2 MCU CPU (NOP),, (Data Memory), I/O CPU w. ALU/Working Reg. Data Mem. Data Bus Data Mem. Addr. Bus Data Memory Memory mapped I/O Program Data. Bus Instruction Fetch & Decode Program Addr. Bus Program Memory Microchip 16-bit MCU I/O Memory mapped Data Memory Program Counter Program Memory, CPU Microchip Technology Incorporated. All Rights Reserved GS5 Slide 2

3 Memory Mapped IO MCU / High/Low ( LED, ) ( SPII2CUART ) ( ADDA ) ( PWM ) MCU I/O, Memory I/O Memory Mapped IO Memory Mapped IO Special Function Register 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 3

4 Microchip 16-bit Microchip 16-bit Family dspic30f PIC24FJ PIC24HJ 16-bit DSP DSP /16 -bit MCU DSP 40 MIPs 16 -bit MCU DMA dspic33fj DSP, 40 MIPs DMA 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 4

5 Program & Data Memory Bus 16-bit microcontroller CPU Data Memory Bus 24-bit Instruction width OP Code & 24-bits, Data Transfer Mechanism between PM and DM (PSV) Program Memory Data Memory CPU Program Memory ( ) 16 bit window Program Memory (Up to 12MB) bit RISC CPU 16 Data Memory (Up to 64KB) 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 5

Microchip 16-bit MCU Data Memory (RAM) 32K x 16 bit DSP: dual access MCU: single access Instruction Pre-fetch & Decode DSP Engine Y AGU W Array 16 x 16 X AGU TABLE Access Cntrl Program Memory DSC

6 Microchip 16-bit MCU Data Memory (RAM) 32K x 16 bit DSP: dual access MCU: single access Instruction Pre-fetch & Decode DSP Engine Y AGU W Array 16 x 16 X AGU TABLE Access Cntrl Program Memory DSC ONLY MCU ALU Address Path MCU/DSP Data Path 23-bit PC Control DSP Data Path Program Data/Control Path 4M x 24 bit Linear 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 6

7 16-bit Architecture Programmers model MCU (ALU) Intel 8051 AB R0.. R7 PIC16F WREG & FSR PIC18F WERG, FSR0.. FSR2 Microchip 16-bit MCU WREG0.. WREG15 16 : Microchip 16-bit-MCU -Multiplier Barrel Shifter 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 7

8 16-bit Architecture Programmers model SFR TBLPAG PSVPAG DOSTART DOEND DCOUNT AccB AccA SPLIM RCOUNT STATUS REG CORCON ALU W 0 W 1 Near Memory Far Memory PCH W 13 W 14 W 15 PCL dspic only 16-bit devices 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 8

9 #1 (c = a + b;) w0 w1 w2 w3 w5 w15 CPU Registers a (copy) b (copy) c (copy). Data Memory (Variables) a b c temp i. ALU ALU can operate directly on variables stored in CPU Registers add w0, w1, w Microchip Technology Incorporated. All Rights Reserved GS5 Slide 9

10 # 2 (c = a + b;) w0 w1 w2 w3 w5 w15 CPU Registers a (copy) addr(b) addr(c). Data Memory (Variables) a b c temp i. ALU can operate directly or indirectly on variables stored in Data Memory Direct ALU add w0, [w1], [w2] Indirect 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 10

11 Program Memory Organization Reset Vector GOTO Main 0x Interrupt Vector Table Executable code starts at 0x100 or 0x200 Interrupts Reserved Alternate Interrupt Vector Table Main: User Program Flash Memory Midway point of Program Memory Unimplemented or Reserved for Configuration Memory Data EEPROM Upper Half of PM 24-bit 0x7FFFFE 0x xFFFFFE 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 11

12 Data Memory Organization* MS Byte Address 16-bits MSB LSB LS Byte Address 2 KB SFR Space 8 KB SRAM Space 0x0001 0x07FF 0x0801 0x17FF 0x1801 SFR Space X Data Ram 0x0000 0x07FE 0x0800 0x17FE 0x1800 Near Data Memory 8 KB Y Data Ram 0x1FFE 0x27FF 0x27FE 0x8001 0x8000 Optionally Mapped into Program Memory Unimplemented PIC24 DSP, X & Y Memory X & Y 0xFFFF 0xFFFE 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 12

IO PIC24FXXXGA1 2006 Microchip Technology

14 MCU Power On Disable, ADC, Power On AD Input Power On ( Comparator ) Initial Oscillator Debug 16-bit MCU 2 Debug Pins Debug Mode module 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 14

15 PIC30F Family Block Diagram KB Flash KB RAM Memory Bus 16/32-bit Timers WDT / Pwr Mgmt. 1 Msps A/D, 10-bit 30 MIPS 16-bit Core 16-bit ALU 17 x 17 MPY Working Register Array 2 Add. Gen. Units Interrupt Control Peripheral Bus 500 Ksps A/D,12-bit GP I/O UART - 2 I 2 C - 2 Multi-bit Shifter SPI - 2 CAN 1-2 DSP Engine 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 15

16 PIC24F Family Block Diagram KB Flash 8 KB RAM 16/32-bit Timers WDT / Pwr Mgmt. Memory Bus 500Ksps A/D,10-bit 16 MIPS 16-bit Core 16-bit ALU Working Register Array 17 x 17 MPY 1 Add. Gen. Units Interrupt Control Peripheral Bus GP I/O UART - 2 I 2 C - 2 SPI - 2 JTAG Interface Multi-bit Shifter RTCC PMP CRC 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 16

17 PIC24H Family Block Diagram KB Flash 8 16 KB RAM 8-chnl. DMA 16-/32-bit Timers WDT / Pwr Mgmt. Memory Bus 1 Msps A/D, 10-bit 40 MIPS 16-bit Core 16-bit ALU 17 x 17 MPY Working Register Array 1 Add. Gen. Units Interrupt Control Peripheral Bus 500 Ksps A/D,12-bit GP I/O UART - 2 I 2 C - 2 JTAG Interface Multi-bit Shifter SPI - 2 ECAN Microchip Technology Incorporated. All Rights Reserved GS5 Slide 17

18 PIC33F Family Block Diagram KB Flash 8 16 KB RAM 8-chnl. DMA 16-/32-bit Timers WDT / Pwr Mgmt. Memory Bus 1 Msps A/D, 10-bit 40 MIPS 16-bit Core 16-bit ALU 17 x 17 MPY Working Register Array 2 Add. Gen. Units Interrupt Control Peripheral Bus 500 Ksps A/D,12-bit GP I/O UART - 2 I 2 C - 2 JTAG Interface Multi-bit Shifter SPI - 2 ECAN 1-2 DSP Engine 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 18

19 CPU Reset, PC ( Program Counter) 0 CPU 0x0000,, Programmer Program memory CPU (CPU Instruction set ) Microchip 16-bit MCU 24 bits 2 words Instruction Word ( Single Instruction Word ) Instruction Words Call, goto PC ( PC + 2 ) CPU Call, goto BRA 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 19

20 Instruction cycle() = 2 Input Clocks CPU () PIC24F A 32Mhz clk = 16MIPS or Tcy = 62.5 ns PIC24H/dsPIC33 A 80Mhz clk = 40 MIPS or Tcy = 25 ns dspic30f Instruction cycle = 4 Input Clocks A 120Mhz clk = 30MIPS or Tcy = 33 ns FOSC Q1 Q2 Q3 Q4 FCY 1 Instruction cycle (TCY) 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 20

22 Microchip 16-bit MCU Vdd & AVdd RESET to MCLR Microchip 16-bit MCU Clock Input VDDCORE 10 uf Low ESR Debugger / Program Interface 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 22

Maximum 12MB 4M Instruction x 24-bit 23-bit PC ( PCH &

Vector at 0 Program Memory Interrupt Vector Table from

1FEh User 200h dspic30f ( 8+54 ), Table FEh.

Alternate Vector Table On Chip User Flash Memory Flash

reg 0 2006 Microchip Technology Incorporated.

23 Maximum 12MB 4M Instruction x 24-bit 23-bit PC ( PCH & PCL ) PC increments in words ( LSb always 0 ) Reset Vector at 0 Program Memory Interrupt Vector Table from 4h to FEh ( ) Alternate Vector Table from 104h to 1FEh User 200h dspic30f ( 8+54 ), Table FEh. User 100h PC<22:1> 0 Reset Vector Interrupt Vector Table Alternate Vector Table On Chip User Flash Memory Flash Config Words Config Registers Device ID 0 PSVPAG Source reg Microchip Technology Incorporated. All Rights Reserved GS5 Slide 23 Config Space User Space 23 0 TABPAG Source reg 0

24 16-bit MCU PC 23 bits 2^23 8 M Words Instruction Word 2 words, 4M Instruction words CPU 0x0004,, 0x0004 0x01FE User 0x200..0x0000 goto xxxx, xxxx 0x200 goto? Address Error Trap!! Trap 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 24

25 CPU Program Counter, X=Y+Z X, PayMoney = Cost * (1+Profit), Cost & Profit! Microchip 16-bit MCU Flash Self -Programming, ( Table Read & Table Write ) Program Memory Write Erase. Erase block (192 Bytes for PIC24FJ128GA006). Table Read/Write ( 2 cycles ). Table Read/Write. Data Memory - Program Memory Solution.. Read/Write ( 1 Cycle ) Microchip Technology Incorporated. All Rights Reserved GS5 Slide 25

26 PSV - Program Space Visibility From Data Space 15 SFR Space 0 0x x x Data Memory 0x x x8000 0x9000 0x x Data Memory 0xFFFE Program Memory 0x Microchip Technology Incorporated. All Rights Reserved GS5 Slide 26

27 PSV PSV? 1. (Mapping) - 2. (32K Words) - PSVPAG PSV Data Memory( PSV ) PSV : Using PSV for digital filters (FIR) Filter coefficients stored in PS -> PSV Data Memory Saves valuable in SRAM ( Data Memory ) Minimal performance impact (2 cycles/filter iteration) LCD Data Encryption algorithms 32KW Program mapping 32KB Data? Instruction word 24-bit, 2 Words Instruction word bit 0.. Bit 15 mapping.. 32KW 16KW mapping, 32 KB 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 27

28 Microchip 16-bit 76 instructions (PIC24) 84 instructions (dspic30/33) Most are one cycle except: Program Flow Changes Double Word Operations (32-bit) Program Memory Accesses Divide Operations (DIV instruction 18x) Most are one word (24 bit) except: CALL, GOTO instructions Byte (8-bit) and Double Word (32-bit) Operations 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 28

29 PIC24F Clock sources Primary Oscillator OSCI OSCO XT,HS Crystal OSC 4x PLL Post Scaler CPU Clock Fast RC 8.0 MHz Post Scaler Peripherals Clock Low Pwr RC 32KHz SOSCI SOSCO 32KHz Secondary Crystal OSC 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 29

31 On-Board Regulator 16-bit MCU, dspic30f Vdd 3.6V (3.3V) I/O CPU core 2.5V PIC24F VDDCORE 2.0V to 2.75V 3.3V PIC24F, PIC24H, dspic33f 2.5V output Regulator ENVREG Vdd Regulator disable CPU core Vddcore/ PIC24F Vdd = 2.2 V to 3.6V!! Vcap 2.5V regulator Low ESR cap VDDCORE 10µf recommended ENVREG pin (PIC24F) enable /disable 2.5V regulator 3.3V Vdd Regulator CPU 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 31

32 Working Registers General Purpose Data Registers or Address Pointers DSP Accumulators (40-bit) OA OB SA Programmer s Model ACCA ACCB SRH SB Working Register Array OAB SAB DSP Status DA DC W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W IPL2 IPL1 IPL0 Frame Pointer Stack Pointer MCU Status DSP OPERAND Registers DSP ADDRESS Registers Program Counter 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 32 SRL RA N OV SZ C PUSH.S Shadow Status Register 0

33 Programmers Model ACCA 39 ACCAU 31 ACCAH 15 ACCAL 0 Two DSP ACCB ACCBU ACCBH ACCBL Accumulators 15 CORCON 0 Core/DSP Control Register dspic Only 7 PSVPAG 0 Prg. Space Visibility Page Address 7 TBLPAG 0 Data Table Page Address 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 33

34 Programmers Model dspic Only 15 RCOUNT 0 Repeat Loop Counter 15 DCOUNT 0 Do Loop Counter 22 DOSTART 0 Do Loop Start Address 22 DOEND 0 Do Loop End Address 2006 Microchip Technology Incorporated. All Rights Reserved GS5 Slide 34

35 Microchip 16-bit MCU Software Stack SPLIM 0x27FE Over Flow Error Stack Two Pointer levels used (W15 ) Top to of save the PC Stack Pushed Data 0x00 PCH PCL SRL PCH PCL Stack Grows Towards Higher Address Interrupt push call Under Flow Error 0x Microchip Technology Incorporated. All Rights Reserved GS5 Slide 35

ICD ICD ICD ICD ICD

ICD ICD ICD ICD ICD MPLAB ICD2 MPLAB ICD2 PIC MPLAB-IDE V6.0 ICD2 usb PC RS232 MPLAB IDE PC PC 2.0 5.5V LED EEDATA MPLAB ICD2 Microchip MPLAB-IDE v6.0 Windows 95/98 Windows NT Windows 2000 www.elc-mcu.com 1 ICD2...4 1.1 ICD2...4