dsPIC Architecture Overview
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- 钊刷 毕
- 5 years ago
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1 Digital Signal Control 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 1
2 dspic30f MCU P P MCU 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 2
3 dspic30f dspic dspic30f: 16-bit MCU with the power of P 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 3
4 dspic30f Product dspic(r) C P i n s Flash KB SRAM Bytes EE Bytes Timer 16-bit Input Cap Output Comp/ Std PWM Motor Cntrl PWM A/D 10-bit 500 KSPS Quad Enc U A R T S P I ( T M ) I 2 C ( T M ) C A N dspic30f ch Yes dspic30f ch Yes dspic30f ch Yes dspic30f ch Yes dspic30f ch Yes dspic30f ch Yes dspic30f ch Yes UPS, 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 4
5 dspic30f Product dspic(r) C Pins Flash KB SRAM Bytes EE Bytes Timer 16-bit Input Capture Output Compare Std PWM A/D 12-bit 100 KSPS U A R T S P I ( T M ) I 2 C ( T M ) C A N Codec Interface dspic30f ch dspic30f ch AC97, I2S dspic30f ch AC97, I2S dspic30f ch dspic30f ch AC97, I2S dspic30f ch AC97, I2S dspic30f ch dspic30f ch AC97, I2S 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 5
6 dspic30f Product dspic(r) C Pins Flash KB SRAM Bytes EE Bytes Timer 16-bit Input Capture Output Compare Std PWM A/D U A R T S P I ( T M ) I 2 C ( T M ) C A N dspic30f bit, 8 ch 1 1 dspic30f bit, 8 ch 1 1 dspic30f bit, 10 ch 1 1 dspic30f bit, 10 ch 2 1, 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 6
7 dspic dspic dspic dspic ASM30 & LINK Microchip Technology dspic30f 16-bit Architecture Workshop 7
8 dspic ( ) Harvard 4M x 24-bit (PS) dspic Flash 64 KB () 8 / 16-bit dspic EEPROM 16 x 16-bit W MCU P 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 8
9 dspic ( ) Modulo (Circular buffers) Bit Reversed P 17-bit x 17-bit 40-bit (ACC) 40-stage Barrel Shifter with +/-16-bit shift range Rounding and Saturation Logic 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 9
10 dspic ( ) (Non-Maskable Traps) : SLEEP IDLE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 10
11 Program Memory (PS) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 11
12 Linear Program Space (PS) 4M x 24-bit 24-bit 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 12
13 (dspic30f6014) (04-7E) (84 - FE) 0x bit wide Reset Vector- GOTO instruction Interrupt Vector Table Alternate Vector Table E 84 FE 0x (0x x017FFE) Configuration Memory User Flash Program Memory (~48K Instructions) Data EEPROM (4 K Bytes) Configuration Memory Space 0x017FFE 0x x7FF000 0x xFFFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 13
14 23-bit ( PC, 24-bit wide Access) Table (TBLRD and TBLWT) Byte Word 32 KB RAM (Program Space Visibility, PSV) Byte Word 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 14
15 (PC) 23-bit Program Counter (PC<22:0>) PC<0> 0 ( ) PC 2 PC 32-bit 24-bit bit 24 Program Counter x7FFFFF 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 15
16 Table () 24-bit (EA) TBLPAG + W Table Page 64K bytes 32K words Configuration TBLPAG<7> 1 Config. 8-bit from TBLPAG 16-bit from Wn EA<0> Byte Select User/ Configuration Space select bit <7> TBLPAG <6:0> 8-bits EA<15:0> 0/1 16-bits 24-bit 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 16
17 Table () able : TBLRDL : Table Read Low TBLWTL : Table Write Low TBLRDH : Table Read High TBLWTH : Table Write High TBLRDH TBLWTH Byte ( 24-bit ) (Phantom byte) 0x Microchip Technology dspic30f 16-bit Architecture Workshop 17
18 Table bit ( ) 00 Phantom Byte Table bits 16-bits TBLRDH.W TBLRDL.W TBLRDH.B Wn<0> = 1 TBLRDH.B Wn<0> = 0 TBLRDL.B Wn<0> = 1 TBLRDL.B Wn<0> = Microchip Technology dspic30f 16-bit Architecture Workshop 18
19 PSV RAM 16 K Word 32K Byte RAM PSV bit (CORCON<2>) 1 EA<15> =1 PSV PSVPAG (Program Space Visibility Page register) Byte (8 b23:b16) EA<14:1> [Wn] 0 Select PSVPAG<7:0> 1 EA<14:1> 0/1 User Space only 8- bits 15-bits 24-bit Effective Address Byte Select 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 19
20 PSV Data Space Program Space 00 (EA<15>=0) PSVPAG 0x20 Data Space EA 16 EA<15>=1 and PSV = 1 EA = 0x9000 0x7FFE 0x8000 0x Address Concatenation x0FFFFE 0x x x10FFFE 1 0xFFFE EA = 0x9000 PSVPAG = 0x x Data Read 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 20
21 PSV 24-bits 16-bits RAM 32KB 8 bits NOP NOP 16-bit RAM 8-bits = 0x3F 16-bits 24-bit 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 21
22 PSV PSV PSV data/program (Von Neumann - like) : PSV FIR One MAC per filter tap, executed within a REPEAT loop PSV allows filter coefficients to be stored in PS saving valuable SRAM Minimal performance impact. 1 cycle per REPEAT iteration plus: 1 extra cycle at REPEAT entry due to PSV data pipe fill 1 extra cycle at REPEAT exit due to PSV data pipe flush 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 22
23 (RTSP) (ICSP) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 23
24 Data Memory 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 24
25 Linear Data Memory Data Memory () 64 KB Data Memory Data memory Byte dspic RAM 16-bit (word ) Byte Word little-endian LSB ( ) MSB ( ) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 25
26 Little-Eendian MSB LSB x001 Byte 1 Byte 0 0x000 0x003 Byte 3 Byte 2 0x002 Byte 5 Byte 4 0x004 Word 0 Word 1 0x006 Long Word <15:0> Long Word <31:16> RAM * word ( EA<0>=0 ) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 26
27 Data Memory () X Space MCU P ( MAC ). (X & Y) P MAC X, Y 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 27
28 dspic30f KB SFR Space MS Byte Address 0x0001 0x07FF 0x bits MSB LSB SFR Space X Data Ram (X) LS Byte Address 0x07FE 0x0800 Near Data Memory 8 KB 8 KB SRAM Space 0x17FF 0x1801 0x27FF 0x8001 Y Data Ram (Y) 0x17FE 0x1800 0x1FFE 0x27FE 0x8000 Addressable Indirectly or with File Register MOV Instruction Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE X, Y dspic 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 28
29 Data Memory () Indirect EA from W8,W9 Indirect EA from W10, W11 [Wn] X-space X Space Unused This section of is designated as Y- space for P instructions X Space Unused Y Space X Space Unused MCU P Note: 32 KB Section of PS mapped to using PSV, is actually mapped to X Microchip Technology dspic30f 16-bit Architecture Workshop 29
30 X, Y AGUs X AGU Y AGU XY AGUs MODULO X AGU Bit-Reversed X AGU Y AGU 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 30
31 Data Memory () RAM 8 KB Near RAM - 0x1FFF 13-bit (SFR) - 0x07FE 64KB Wn 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 31
32 word : MOV 0x1001, W2 ; ; ( NOP) : PSV PSV : MOV 0xFEFE, W2 ; PSV ; {Note: MOV 0xFEFE, W2 PSV } ( NOP) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 32
33 dspic 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 33
34 dspic30f CPU () CPU : P 17x17-bit * 40-bit * 40-bit / 40-bit * MCU 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 34
35 dspic30f CPU () MCU 16-bit ALU W DO REPEAT 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 35
36 dspic CPU 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 36
37 W () W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 ( ) ( ) 15 0 MAC Prefetch Offset MAC Write Back Ptr. Frame Pointer Stack Pointer Stack Pointer Limit FP SP SPLIM WREG P P P ACCA (40-bit) ACCB ACCAU ACCBU ACCAH ACCBH ACCAL ACCBL 0 SRH SRL OA OB SA SB OAB SAB DA DC IPL2IPL1 IPL0 P Status MCU Status 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 37 RA N OV SZ C
38 OA, OB, OAB Accumulator Overflow Status bit (overflowed into <32:39>) SA, SB, SAB Accumulator Saturation STICKY Status (bit 31 or 39 overflow) DA Do Loop Active bit (Read Only) DC MCU ALU Half Carry/Borrow bit RA REPEAT Loop Active bit (Read Only) N, OV, Z, C 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 38
39 () Program Counter (23-bit) 7 0 TBLPAG TABLE Data Read Page Address 7 0 PSVPAG PSV Page Address 13 0 RCOUNT REPEAT Loop Counter 13 0 DCOUNT DO Loop Counter 22 DOSTART 0 0 DO Loop Start Address DO SFRs 22 0 DOEND 0 DO Loop End Address 15 0 US EDT DL2 DL1 DL0 SATA SATB SATDWACCSAT IPL3 Core Control Register (CORCON) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 39 PSV RND IF
40 () W15 PUSH (W15) RAM W15 POP W15 CALL PC PC SRL (MCU ) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 40
41 () x1001 0x1000 0x00 PC[15:0] PC[23:16] (Call / Interrupt) PC[15:0] SRL (Call / Interrupt) PC[22:16] IPL<3> SRL register saved (CORCON<3>) with PC value... Note: (W15) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 41
42 : Frame Pointer W14 (FP) LNK #N ; (N / 2) word W14 W15 / W14 W15 W15 W14 ( ) 16-bit (word) [W14 + n] / W14 ULNK ; W14 ( -1) W15 W15 ( ) W14 W Microchip Technology dspic30f 16-bit Architecture Workshop 42
43 PUSH W0 Frame of MyRoutine 0x0800 <-- W14 <-- W15 0xFFFE MyRoutine:... PUSH W0 PUSH W1 PUSH W2 CALL Func POP W2 POP W1 POP W0... MyFunc:LNK #4... ULNK RETURN 0x0800 W14 --> W15 --> 0xFFFE LNK #4 Frame of MyRoutine Parameter 1 = W0 Parameter 2 = W1 Parameter 3 = W2 PC<15:1> Frame Ptr of MyRoutine Temp Variable 1 Temp Variable 2 Top Of Stack PC<22:16> 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 43 0 Frame of MyFunc
44 REPEAT () : REPEAT #lit14 REPEAT Wn N+1 N 14-bit W RCOUNT RA bit RCOUNT > 1 RCOUNT = 1 RA bit 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 44
45 REPEAT () REPEAT RA bit (SRL) REPEAT RCOUNT RCOUNT REPEAT REPEAT : DO REPEAT DISI, LNK, PWRSAV, ULNK, RESET 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 45
46 DO () DO N+1 N 14-bit W Loop DOSTART Loop DOEND Loop DCOUNT Loop 32K 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 46
47 DO () DO 7 6 DO DO DO shadower ( ) DO DO DL<2:0> DL<2:0> 0 DCOUNT > 1DA Microchip Technology dspic30f 16-bit Architecture Workshop 47
48 DO () Setting the EDT bit terminates DO loop execution (drops the DO level by one) DL bits modified by HW to reflect new DO level DO loop is interruptible ISRs can contain DO loops On entry into ISR, the DA or DL<2:0> bits should be checked to determine if the DO SFRs need to be stacked prior to executing any DO loops within the ISR 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 48
49 DO () The following instructions cannot be used as one of the last two instructions of a DO loop: Flow Control (i.e., GOTO, CALL, BRA) RETFIE, RETURN or RETLW instructions DO or REPEAT instructions Compare-and-Skip type instructions (i.e., CPSGT, CPSEQ, CPSLT) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 49
50 P 40-bit Accumulator A 40-bit Accumulator B Saturate Adder 40 Round Logic Saturate 16 Enable Negate Barrel Shifter X Data Bus Sign Extend Zero-backfill bit Multiplier/Scaler Operand Pre-Processing From W Array To W Array 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 50
51 17x17 MCU P 32-bit 1.31 (fractional) 32-bit (integer) 17-bit x 17-bit (-1.0) * (-1.0) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 51
52 : 2 s [ ~ 32767] [0x8000 ~ 0x7FFF] (Q15) 2 s : S.FFFFFFFFFFFFFFF [-1.0 ~ ] 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 52
53 0x4001 (Integer) : x4001 = = = (Fractional) : implied radix point 0 0x4001 = = = Microchip Technology dspic30f 16-bit Architecture Workshop 53
54 0xC002 (Integer) : xC002 = = = (Fractional) : implied radix point xC002 = = = Microchip Technology dspic30f 16-bit Architecture Workshop 54
55 / = = x xA xC xE x x x x7FFF : / = Microchip Technology dspic30f 16-bit Architecture Workshop 55
56 dspic30f 16-bit to ( ) (Q15 Format) x bit -2,147,483,648 2,147,483, to ( ) (Q31 Format) x bit -549,755,813, ,755,813, to ( ) (Q31 Format with 8 Guard bits) x Microchip Technology dspic30f 16-bit Architecture Workshop 56
57 To Sign Extend and P Adder 33 Shift one bit left for fractional multiplies IF bit, CORCON<0> Integer/Fractional Select Fractional Scaler P MCU <31:16> MCU <15:0> MCU Wn+1:Wn x17-bit MCU multiply unaffected by scaler Input 1 Input Multiply Mixed Mode Select (Instruction Decode) 2 Mixed Mode Operand Pre-processor Data paths to W Array and X Data bus (via W array) From W Array To W Array 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 57
58 MCU (MUL.UU, MUL.SS, MUL.US, MUL.SU, MUL.B, MUL.W) 16-bit x 16-bit ( Wn ) W ( / ) 32-bit W W1:W0W3:W2 W13:W12 : MUL W4, W0, W2 W4 * W0 W3:W2 ( MUL.B MUL.W WREG 32-bit W3:W2 8 x 8 W2 ) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 58
59 P (ED, EDAC, MAC, MPY, MPY.N, MSC) ACCA ACCB / / IF CORCON<0> US CORCON<12> Fractional: scaler automatically shifts the multiplier result one bit to the left (LSB) This maintains proper alignment of the radix point (product has a 1.31 numerical format) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 59
60 ( IF, CORCON<0> = 1 ) MPY W4*W5, A If W4 = 0xFFF7 ( ) If W5 = 0x7FF7 ( ) 0xFF FFFB 8051 (40-bits) 0xFF FFF7 00A2 (40-bits) x x results 2.31 results after scaler shift Extra sign-extension bit (required for 0x8000*0x8000) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 60
61 To 40-bit Adder 40 Sign Extend LAC instruction Zero Backfill 16 X Data Bus Fractional Scaler 32 17x17-bit Signed Multiplier Mixed Mode Operand Pre-processor ED, EDAC, MAC, MPY, MPY.N, MSC instructions 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 61
62 Zero Backfill & Sign Extend Control Block Control logic used to interface 16-bit and 32-bit data with the 40-bit accumulator Think of it as a data massager which allows data to be properly placed in the 40-bit accumulator Data loads are placed into (ACCxH:ACCxL) P products are placed into (ACCxH:ACCxL) Sign extend logic sign extends from bit 31 through all of ACCxU ACCxU = 0xFF for negative values ACCxU = 0x00 for positive values ACCxU ACCxH ACCxL LAC [W4++], #-3, A ABCD Before After 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 62 W4 ACCA 0x2000 SR FF (OA,OAB=1)
63 40-bit P Adder and Accumulators Source Select 2 M3 Source Select 1 Status Bits 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate From Barrel Shifter Saturatio n Mode Negate Control M4 M5 To Round/Saturation Logic for Data Space Writes Adder Input Select Accumulator Bypass M2 BS Source Select Zero M1 To Barrel Shifter From Sign Extension Logic 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 63
64 40-bit Accumulators Two Independent 40-bit Accumulators 32 result bits + 8 guard bits (for large dynamic range) Accumulators are memory-mapped Overflow detection, flags and associated branch instructions for each Accumulator Two optional saturation modes 31-Bit Saturation - (Normal Saturation) 39-Bit Saturation - (Super Saturation) Accumulator store mechanism is 16-bits wide Optional biased or unbiased rounding Includes independent data write saturation logic 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 64
65 40-bit Accumulator Alignment Accumulator Alignment and Usage A ACCxU ACCxH ACCxL B C D A. 40-bit Accumulator consists of ACCxU:ACCxH:ACCxL B. Load and Store Operations C. Operations in Normal Saturation mode D. Operations in Super Saturation mode P instructions LAC, SAC and SAC.R are used to load and store the accumulators, since they provide sign-extension, shifting and rounding capabilities Microchip Technology dspic30f 16-bit Architecture Workshop 65
66 Four Methods of Accumulator Storage SAC - Stores truncated ACCxH SAC.R - Stores rounded ACCxH Accumulator Write-Back (via CLR, MAC, MOVSAC, MSC) - Stores rounded ACCxH MOV from memory mapped Accumulator register Contents of specified register are stored No rounding or Write Saturation performed Not recommended for most applications (for storing integer products, this method is OK) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 66
67 Round and Data Write Saturation 8 ACCxU<39:31> Overflow Logic OVFL From ACCA / ACCB 16 ACCxH<16> ACCxL<15:0> 16 Rounding Logic ACCxH<31:16> 0x0 or 0x1 15th bit carry out 16-bit Adder 16 0x7FFF 0x To X-Data Bus RND CORCON<1> SATDW CORCON<5> 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 67
68 Accumulator Rounding Only utilized by SAC.R and Acc. Write-Back Mode is selected by RND bit (CORCON<1>) Conventional (biased): Rounds up if ACCxL<15> = 1 Convergent (unbiased/default): Rounds up if.. ACCxL is 0x8000 and ACCxL<16> = 1 OR ACCxL is greater than 0x8000 Rounding does not affect Accumulator ACCxU ACCxH ACCxL 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 68
69 Accumulator Rounding during Memory Store CONVENTIONAL ROUNDING RND = 1 CONVERGENT ROUNDING RND = 0 31 MS WORD xxx xxxx xxxx xxxx 0 31 MS WORD Round Up (add 1 to MS word) when: LS word >= 0x8000 Round Up (add 1 to MS word) when: LS word = 0x8000 and bit 16 = 1 LS word > 0x MS WORD xxx xxxx xxxx xxxx 0 31 MS WORD Round Down (add nothing) when: LS word < 0x8000 Round Down (add nothing) when: LS word = 0x8000 and bit 16 = 0 LS word < 0x8000 The RND bit, CORCON<1>, selects the Accumulator rounding mode during memory store. [Default is convergent on POR] Example 1 (Rounding): SAC.R A, Slit4, Wdo (Slit4 = [ ]) Example 2 (Truncation): SAC A, Slit4, Wdo (Slit4 = [ ]) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 69
70 Data Space Write Saturation Provides a 16-bit interface to the Data Bus even when 1.31 Saturation is not used For SAC, SAC.R and Accumulator Write-Backs, the 1.15 saturated contents of ACCx are stored Contents of Accumulator are not changed Mode is enabled by SATDW (CORCON<1>) Example (SATDW = 1, ACCSAT = 0): SAC.R A, W0 ; Stores ACCA to W0 If ACCA = 0x00 7FFF FFFF, the value stored to W0 = 0x7FFF 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 70
71 40-bit Barrel Shifter 40-bit wide barrel shifter Used for both MCU and P shift operations Shift ACCA, ACCB, W registers or memory Maximum shift range is 16 bits to the left or right - varies by instruction type Overflow recognition and range limit detection Integral part of P engine so permits shifting concurrent with other P operations 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 71
72 Shift Operation Types MCU shifts (arithmetic and logical) Operate on 16-bit Working registers Literal shift range of 15 bits to the left or right Variable shift by any value P shifts (arithmetic only) Operate on ACCA or ACCB Literal & variable range of 16 bits to the left or right Shifts beyond 16 bits cause an arithmetic error trap If enabled, saturation is applied to the result Saturation correct even for shifts that overflow ACCx 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 72
73 MCU Shifts SL, ASR, LSR Instructions Literal shift range of 15 bits to the left or right SL Wb, #lit4, Wnd (also ASR, LSR) Variable shift by any value in Wns SL Wb, Wns, Wnd (also ASR, LSR) Wns > 15 will result in: SL, LSR: Wnd = ASR when Wb<15>=0 : Wnd = ASR when Wb<15>=1 : Wnd = 0xFFFF 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 73
74 P Shifts SFTAC Instruction: Literal or variable shift value SFTAC B, #slit6 or SFTAC A, Ws Shift range of 16 bits to the left or right If enabled, saturation is applied to the result Saturation correct even for shifts that overflow ACCx Variable shift in excess of maximum range will cause a trap (accumulator is preserved) LAC, SAC and SAC.R Instructions Reduced range of up to 8 bits left or 7 bits right Shifting is optional 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 74
75 dspic 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 75
76 84 word (24 bit) word : Program Flow Changes (2 cycles) Branch Instructions (2 or 3 cycles) Table instructions (2 cycles) MOV.D Instructions (2 cycles) DO instruction (2 cycles) Divide Instructions* (18 cycles) *Note: Division is iterative(used with REPEAT) and interruptible on any cycle 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 76
77 The dspic 30F ISA features : MOVE instructions MATH instructions LOGIC instructions SHIFT / ROTATE instructions BIT instructions STACK instructions PROGRAM FLOW instructions CONTROL instructions P / Accumulator instructions MCU 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 77
78 MCU (3-operand) MCU C A = B C A = W register B = W register or indirect address C = W register or indirect address Indirect address can be pre/post modified ADD W1, W2, W3 ; W3 = W1 + W2 ADD W1, [W2], [W3++] ; *W3++ = W1 + *W2 MUL.UU W1, [W2++], W4 ; W4 = W1 * [*W2++] 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 78
79 P Assembly Syntax ADD Acc ADD Wso,#Slit4, Acc CLR Acc,Wx,Wxd,Wy,Wyd,AWB ED Wm*Wm,Acc,Wx,Wxd,Wy EDAC Wm*Wm,Acc,Wx,Wxd,Wy LAC Wso,#Slit4,Acc MAC Wm*Wn,Acc, Wx,Wxd,Wy,Wyd,AWB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB MPY Wm*Wn,Acc,Wxd,Wx,Wyd,Wy MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd MPYN Wm*Wn,Acc,Wx,Wxd,Wy,Wyd MSC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB NEG Acc SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo SFTAC Acc,#Slit5 SFTAC Acc,Wn SUB Acc Description Add Accumulators [Shift then] Add to Accumulator * Clear Accumulator Partial Euclidean Distance Euclidean Distance [Shift then] Load Accumulator * Multiply and Accumulate Square and Accumulate Store Accumulator and Pre-fetch Multiply Wn by Wm to Accumulator Square to Accumulator -(Multiply Wn by Wm) to Accumulator Multiply and Subtract from Accumulator Negate Accumulator [Shift then] Store Accumulator * [Shift then] Store Rounded Accumulator * Arithmetic Shift by Slit5 Accumulator Arithmetic Shift by (Wn) Accumulator Subtract Accumulators Note: Instructions in yellow, form the MAC class of P instructions. All instructions execute in 1 cycle and occupy 1 instruction word. Optional shift operations indicated by * 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 79
80 MAC ( P ) : 1 operation on ACCA (or ACCB) with data fetched into W register(s) from a previous cycle 2 data fetches - 1 each from X- and Y- 2 updates to the X and Y EAs used for the data fetch operations 1 write back (WB) of the other accumulator, ACCB (or ACCA), to X Microchip Technology dspic30f 16-bit Architecture Workshop 80
81 MAC () : MAC W4*W5, A, [W8]+=2, W4, [W10]-=6, W5, W13 Source operand registers Destination accumulator Y prefetch source Y prefetch destination X prefetch source X prefetch destination Other Acc. Write-back destination 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 81
82 MAC () : MPY MAC MPY W4*W5, A, [W8], W4, [W10], W5, [W13]+=2 MAC W5*W6, B, [W9]-=6, W4, [W11+W12], W7 Data fetches are optional and may be made to only one bus, if so desired Accumulator WB is also optional MPY A, W4*W7 ; no pre-fetch/base syntax 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 82
83 Addressing Modes 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 83
84 dspic30f : / 8 KB Near W ( ) Register indirect with register or literal offset (supported in some instructions) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 84
85 byte 8 Kb (Near DM) ADD {.b} 0x900, {WREG} MCU WREG WREG { } option 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 85
86 : MOV Word 64KB MOV 0x2500, W7 MOV W : byte MOV WREG 8Kb 64KB word ( ) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 86
87 - Near Data (Word) ADD 0x1000 0x4001 0x0002 W0 W1 W2 W3 W 0x4001 WREG 0x x3001 = 0x7002 0x7002 0x3001 0x1000 0x1002 0x1FFE 0x2000 W14 W15 0x2400 W MOV 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 87
88 - Near Data (Word) ADD 0x1000, WREG 0x7002 0x4001 0x0002 W0 W1 W 0x4001 0x4064 0x7002 WREG 0x3001 0x1000 0x1002 W2 W3 0x x3001 = 0x7002 0x1FFE 0x2000 W14 W15 0x2400 W MOV 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 88
89 - Near Data (Byte) ADD.B 0x1001 0x4001 0x0002 W0 W1 W2 W3 W 0x4001 WREG 0x01 + 0x30 = 0x31 0x3101 0x3001 0x1000 0x1002 0x1FFE 0x2000 W14 W15 0x2400 W MOV 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 89
90 - 64KB (Word) MOV W3, 0x2000 0x0002 W 0x1000 W0 0x1002 W1 W2 W3 0xABCD W3 0x2 0x xABCD 0x1234 0x1FFE 0x2000 W14 W15 0x2400 W 64KB KB 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 90
91 RAM.nbss.ndata.section.nbss MYBUF:.space 2 ; Word Format.section.ndata MYFLAG:.byte 0x0A MOV 0x900, WREG ;Copy data at 0x900 to W0 MOV WREG, MYBUF ;Copy W0 to MYBUF 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 91
92 W W0 - W15 ( - 0x001F RAM ) byte word : IOR W2, W4, W6 W2 W4 OR W Microchip Technology dspic30f 16-bit Architecture Workshop 92
93 W0 W1 W2 W3 W13 W14 W15 W 0x1009 0x0003 0x100C 0x Word ADD W1, W2, W13 0x x03 = 0x100C 0x1009 0x0002 0x1000 0x1002 0x2000 0x2002 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 93
94 W0 W1 W2 W3 W13 W14 W15 W 0x x x000c0c 0x Byte ADD.b W1, W2, W13 0x09 + 0x03 = 0x0C 0x1009 0x0002 0x1000 0x1002 0x2000 0x2002 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 94
95 W W (EA) 64KB byte (Source and Destination ) [ ] Wn : [W0] 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 95
96 W0 W1 W2 W3 W14 W15 W 0x1000 0x8000 0x2000 0x Word ADD [W1], W2, [W3] 0x x7FFF = 0xFFFF 0x1000 0x7FFF 0xFFFF 0x0002 0x1000 0x1002 0x2000 0x2002 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 96
97 W0 W1 W2 W3 W14 W15 W 0x1000 0x1005 0x2000 0x Byte ADD.b [W1], W2, [W3] 0x05 + 0x03 = 0x08 0x1000 0xAA03 0x7F08 0x7FFF 0x0002 0x1000 0x1002 0x2000 0x2002 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 97
98 Post-Modification (EA) EA = Wn C : [W1++] [W2--] Post-modifies byte / 1 word / 2 Post-modification 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 98
99 W0 W1 W2 W3 W14 W15 W 0x1000 0x1002 0x8000 0x2000 0x1FFE 0x2400 Post-Modification: Word Access ADD [W1++], W2, [W3--] 0x x7FFF = 0xFFFF Pointer Post-Modification W1 = W1 + 2 = 0x = 0x1002 W3 = W3-2 = 0x = 0x1FFE 0x1000 0x1002 0x7FFF 0xFFFF 0x0002 0x1000 0x1002 0x2000 0x2002 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 99
100 W0 W1 W2 W3 W14 W15 W 0x1000 0x1001 0x8000 0x2000 0x1FFF 0x2400 Post-Modification: Byte Access ADD.b [W1++], W2, [W3--] 0x00 + 0xFF = 0xFF Pointer Post-Modification W1 = W1 + 1 = 0x = 0x1001 W3 = W3-1 = 0x = 0x1FFF 0x1000 0x1001 0x7FFF 0x00FF 0x0002 0x1000 0x1002 0x2000 0x2002 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 100
101 Pre-modification (EA) EA = Wn C : [W1++] [W2--] Pre-modifies byte / 1 word / 2 Pre-modification 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 101
102 W0 W1 W2 W3 W14 W15 W 0x1000 0x1002 0x8000 0x2000 0x1FFE 0x2400 Pre-Modification: Word Access ADD [++W1], W2, [--W3] 0x x4000 = 0xC000 Pointer Pre-Modification W1 = W1 + 2 = 0x = 0x1002 W3 = W3-2 = 0x = 0x1FFE 0x1000 0x1002 0x7FFF 0x4000 0xC000 0x0002 0x1000 0x1002 0x1FFE 0x2000 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 102
103 (ED, EDAC, LAC, MAC, MOV, MOVSAC, MPY, MPY.N MSC, PUSH, POP, SAC,, SAC.R) W W4 = 0x2000 W5 = 0x0004 W6 = 0x1000 [0x2004] = 0x000A [0x1000] = 0xEEEE [0x1002] = 0xFFFF MOV [W4+W5], [W6++] W4 = 0x2000 W5 = 0x0004 W6 = 0x1002 [0x2004] = 0x000A [0x1000] = 0x000A [0x1002] = 0xFFFF 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 103
104 W0 W1 W2 W3 W 0x1000 0x0020 0x2000 0x2002 MOV [W1+W2], [W3++] 0x7FFF 0x1000 0xF354 0x1020 W14 W15 0x2400 = 0x x20 0x1020 0x2000 0xF354 0x2000 0x2002 Pointer Post-Modification W1, W2 Unaffected W3 = W3 + 2 = 0x = 0x2002 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 104
105 W MOV MOV #MyTableBaseAdr, W0 #Offset, W1 NextWordRead: MOV [W0 + W1], W2 ;Process contents of W2 ADD W1, #Offset, W1 BRA NextWordRead 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 105
106 16 bits MOV 16-bit Byte Word 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 106
107 W0 W1 W2 W3 W13 W14 W15 W 0x1000 0x0003 0x101E 0x2400 ADD W1, #30, W13 0x x1E = 0x101E 0x1000 0x0002 0x1000 0x1002 0x2000 0x2002 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 107
108 W MOV : [-1024, 1022] MOV word MOV Byte [-512, 511] 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 108
109 W0 W1 W2 W3 W 0x1000 0x2000 0x Word MOV [W1 + #0x20], [W3++] 0x7FFF 0x1000 0xF354 0x1020 W14 W15 0x2400 = 0x x20 0x1020 0x2000 0xF354 0x2000 0x2002 Pointer Post-Modification W1 W3 = W3 + 2 = 0x = 0x2002 0xFFFC 0xFFFE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 109
110 MCU Move Instructions Math and Logic Instructions Bit Instructions Stack Control Instructions Program Flow Control Instructions CPU Control Instructions P MAC class of Instructions Other Accumulator-based instructions 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 110
111 MOV MOV 64 KB : MOV #0x1234,W4 MOV W4,W6 MOV 0x1F00,W4 MOV [W4++],[--W6] MOV [W4+W5],[W8] MOV [W4+#768],[W8] ;Immediate operand ;Register-direct ;File-register ;Indirect with pre ;and post-modifier ;Indirect with ;Register Offset ;Indirect with ;Literal offset 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 111
112 Math Logic / : MUL.SU W2, #31, W2 ;W3:W2 = W2 * 31 AND W3, [W5++], [W8++] ADD 0x900, WREG ;W0 = W0+ Mem[0x900] IOR #0x3FF, W4 ;W4 = W4 OR 0x03FF REPEAT #17 ;W0 = Quot.(W8/W2) DIV.S W8, W2 ;W1 = Remder.(W8/W2) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 112
113 / (3 or 4-bit ) : BSET.b INTCON1H, #7 ;Sets bit 15 of INTCON1 BTG INTCON1, #15 ;Toggle bit 15 of INTCON1 BCLR [W1++], #9 ;Clears bit 9 of [W1] BSET W0, #4 ;Sets bit 4 of W0 BTSS W0, #4 ;Test bit 4 of W0 and skip ;next instruction if set 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 113
114 / / : CP 0x1200 ;Compare Mem[0x1200] ;with W0 CP W2, #13 ;Compare W2 with 13 CPSGT W3, W5 ;If W3>W5 skip next ;instruction 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 114
115 / W15 PUSH (TOS) W15 POP W Microchip Technology dspic30f 16-bit Architecture Workshop 115
116 : REPEAT W2 DO #15, Label1 BRA W3 GOTO W1 CALL W5 RCALL Subroutine1 GOTO Label2 CALL Subroutine2 ;Repeat next instruction ;W2+1 times ;Execute a block of code ;16 times ;PC<15:0> = W3, PC<23:16> = 0x00 ;PC<15:0> = W1, PC<23:16> = 0x00 ;PC<15:0> = W5, PC<23:16> = 0x00 ;1-word instruction ;2-word instruction ;2-word instruction 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 116
117 Modulo : Modulo MODCON XMODEN X-Modulo YMODEN Y-Modulo Wn X Y- 15 XMODEN YMODEN YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0 MODCON REGISTER 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 117
118 : = 17 words (0x0800-0x0821 = 0x22 bytes = 17 words) W2 X Modulus Y Modulus X Bit Reversed MODCON = 0x8FF2 XMORT = 0x0800 XMODEND = 0x0821 MOV MOV MOV MOV MOV MOV MOV MOV DO Loop: MOV #0x0800,W0 W0,XMORT #0x0821,W0 W0,XMODEND #0x8FF2,W0 W0,MODCON #55AA,W0 #0x0800,W2 #16,Loop Modulo : X Data Space Buffer Start Buffer End W0,[W2++] ; W2 =0x0800 when DO loop completes XMORT must be on a zero power of 2 boundary. XMORT = 0x0800 [W2++] or [++W2] causes rollover XMODEND = 0x Microchip Technology dspic30f 16-bit Architecture Workshop 118
119 Modulo : : Y Data Space = 17 words (occupying memory region 0x181E - 0x183F) W2 Y Modulus Buffer Disable X Modulus Disable X Bit Reversed MODCON = 0x4F2F YMORT = 0x181E YMODEND = 0x183F Buffer Start YMORT = 0x181E [W2--]] or [--W2] causes rollover Note: Byte addresses are used for YMORT and YMODEND values. Buffer End YMODEND = 0x183F YMODEND must be on a ones power of 2 boundary Microchip Technology dspic30f 16-bit Architecture Workshop 119
120 Modulo : Example Specifications: Buffer Length = 16 words (occupying memory region 0x1800-0x181F) W2 is selected register Y Modulus Buffer Disable X Modulus Disable X Bit Reversed MODCON = 0x4F2F YMORT = 0x1800 YMODEND = 0x181F Note: Byte addresses are used for YMORT and YMODEND values. Y Data Space Buffer Start 2 n entries Buffer End YMORT must be on a zero power of 2 boundary. YMORT = 0x1800 [W2--]] or [--W2] causes rollover [W2++] or [++W2] causes rollover YMODEND = 0x181F YMODEND must be on a ones power of 2 boundary Microchip Technology dspic30f 16-bit Architecture Workshop 120
121 (Bit-Reversed) Bit-Reversed (BR) addressing is used to efficiently implement data addressing for radix-2 FFT Pivot Point BR modifier is added to the base W register, with direction of Carry propagation reversed, to generate the next EA 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 121
122 (16 - ) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 122
123 16 () A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0xA6DC x xA6C2 AGU adder A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Supported only in word mode write operations carried out in X data space BR addressing assumes priority over Modulo addressing for write operations, when the two are simultaneously enabled 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 123
124 16 () (0) 0xA6C0 (1) 0xA6C2 (2) 0xA6C4 (3) 0xA6C6 (4) 0xA6C8 (5) 0xA6CA (6) 0xA6CC (7) 0xA6CE (8) 0xA6D0 (9) 0xA6D2 (10) 0xA6D4 (11) 0xA6D6 (12) 0xA6D8 (13) 0xA6DA (14) 0xA6DC (15) 0xA6DE : = 0xA6DC = XB*2 = 0x (0xA6DC) (0x0010) (0xA6C2) >>>>> = 0xA6C20 (0) 0xA6C0 (8) 0xA6D0 (4) 0xA6C8 (12) 0xA6D8 (2) 0xA6C4 (10) 0xA6D4 (6) 0xA6CC (14) 0xA6DC (1) 0xA6C2 (9) 0xA6D2 (5) 0xA6CA (13) 0xA6DA (3) 0xA6C6 (11) 0xA6D6 (7) 0xA6CE (15) 0xA6DE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 124
125 - MODCON XBREV BREN (XBREV<15>) BWM (MODCON<11:9>) W XB (XBREV<14:0>) (Modifier value) 15 BWM3 BWM2 BWM1 BWM0 MODCON REGISTER BREN XB14 XB13 XB12 XB11 XB10 XB9 XB8 XB7 XB6 XB5 XB4 XB3 XB2 XB1 XB0 BREN - Bit Reversed Addressing Enable XB<14:0> - X AGU Bit Reversed Modifier XBREV REGISTER 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 125
126 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 126
127 dspic30f (IVT) 8 (Non-Maskable) 54 7 (IVT) Microchip Technology dspic30f 16-bit Architecture Workshop 127
128 (IVT) Reset - GOTO Instruction Reset - GOTO Address Reserved Oscillator Fail Trap Address Error Trap Stack Error Trap Math Error Trap Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 2 Interrupt Vector 53 Reserved Reserved E Reserved 84 Oscillator Fail Trap Interrupt Vector 53 FE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop
129 () CPU trap IPL CPU IPL<3> bit (CORCON<3>) IPL<2:0> bits (SRL<7:5) 0~7 IPC = Microchip Technology dspic30f 16-bit Architecture Workshop 129
130 () CPU (IPL<3:0>) CPU IPL<2:0> CPU IPL<3> IPL IPL<3:0> 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 130
131 Context / SRL PC PUSH(.D) POP(.D) PUSH.S POP.S W0 W3 MCU (DC, N, OV, Z, C) shadow registers 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 131
132 15 0 0x0800 SRL pushed onto stack to preserve IPL<2:0> and MCU ALU status (except DC) PC<15:0> SR<7:0> PC<22:16> IPL3 W15 ( ) W15 ( ) IPL3 saved in MS bit of stacked PC value 0x27FE 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 132
133 NSTDIS (INTCON1<15>) NSTDIS = 1 CPU Microchip Technology dspic30f 16-bit Architecture Workshop 133
134 Traps () (Traps) 8 ~ 12 NMI (Traps) 13 ~ 15 CPU Execution cannot resume until trap is acknowledged 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 134
135 Traps () (Traps) ( 11) ( ) ACCA, ACCB (optional) ACCA or ACCB (optional) ( 12) (Traps) ( 13) ( 14) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 135
136 DISI DISI DISICNT DISICNT 0 DISICNT DISICNT DISI (INTCON2<14>) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 136
137 dspic ASM30 & LINK Microchip Technology dspic30f 16-bit Architecture Workshop 137
138 C Source Files C30 C Compiler Compiler Driver Program Source Files (*.s) Assembly Source Files (*.s) ASM30 Assembler Archiver (Librarian) COFF Object Files (*.o) Object File Libraries (*.a) LINK30 Linker Executable COFF file (*.cof) MPLAB IDE Debug Tool Command Line Simulator 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 138
139 ASM30.include.include source file *.inc MPASM < >.include c:\pic30_tools\support\inc\p30f6014.inc.include C:\Program Files\MPLAB IDE \dspic_tools\support\inc\p30f6014.inc C # *.h #include p30f6014.h 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 139
140 ASM30.equ.equiv.set MPASM dspic.equ CORCONH, 0x45 MPASM CORCONH equ 0x45.equ.equiv.set.equ 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 140
141 ASM30.section :.section name [, Flags ] :.bss : (Uninitialized Data).data : (Initialized Data).text : (Executable Code) Flags b : bss section ( ) n : Section is not load d : Data section ( ) r : Read-Only data section (PSV window) x : Execttable section 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 141
142 ASM30.section Section Name Default Flag.bss b.data d.text x : Var1 & Var2.bss (uninitialized data).section.bss, "b" Var1:.space 4 ; 4 bytes Var2:.space 1 ; 1 byte 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 142
143 .align :.align n n N 2 modulo addressing :.section.bss, "b".align 8 ; 8 A_Var:.space 6 ; 6 Bytes A_Var 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 143
144 .palign :.palign n n N 2 :.section.my_const_data, x".align 2 ; My_Dtat:.hword 0x2000,0x3000,0x4000 ; 6 Bytes A_Var 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 144
145 dspic Section Name.bss.nbss.xbss.ybss.pbss.data.ndata.xdata.ydata.dconst.ndconst Description General Memory is not uninitialized Near Memory (8kB) is not uninitialized X Memory is not uninitialized Y Memory is not uninitialized Persistent Data Memory General Memory (initial values) Near Memory (initial values) X Memory (initial values) Y Memory (initial values) Constants in the General Memory Constants in the Near Memory Section Flag b b b b b d d d d d d 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 145
146 General FFFF const Program Space Visibility Data Window (PSV) Near xbss,.xdata.nbss,.ndata.ybss,.ydata.bss,.data.bss,.nbss,.xbss,.ybss:,.data,.ndata,.xdata,.ydata: (SFR) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 146
147 .bss :.section.bss, b Uninitialized Data RAM (0x800) *.gld Link30 : ; ; Uninitialized variables in general data memory ; section.bss, "b".align 2 A_Var:.space 4 ; 4 Bytes A_Var B_Var:.space 20 ; 20 Bytes B_Var C_Var:.space 4 ; 4 Bytes C_Var 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 147
148 .nbss FR WREG 8K Bytes MOV 0x1000,WREG ADD.B 0x17FF,WREG BD f f f f f f f f f f f f f B: Byte D: File Reg. WREG f : 13 bit (8K Bytes) FR Wn 32K Words MOV 0xF000,W0 ; : word 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 148
149 Near Data.nbss :.section.nbss, b Uninitialized Data RAM (0x800 0x1FFF) : ; ; Uninitialized variables in near data memory ; section.nbss, "b".align 2 A_Var:.space 4 ; 4 Bytes A_Var B_Var:.space 20 ; 20 Bytes B_Var C_Var:.space 4 ; 4 Bytes C_Var 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 149
150 X X Space.xbss :.section.xbss, b Uninitialized Data X Data RAM P (P X Y Space ) : A/D FIR IIR Modulo Buffer :.equ SAMPLES, 64 ; A/D number of samples ;... ;Uninitialized variables in X-space in data memory ;....section.xbss, "b" x_input:.space 4*SAMPLES ;Allocating space (in bytes) to variable Microchip Technology dspic30f 16-bit Architecture Workshop 150
151 Y Y Space.ybss :.section.ybss, b Uninitialized Data Y Data RAM P dspic X- Space Y-Space :.equ SAMPLES, 64 ; A/D number of samples ;... ;Uninitialized variables in Y-space in data memory ;....section.ybss, "b" y_input:.space 4*SAMPLES ;Allocating space (in bytes) to variable Microchip Technology dspic30f 16-bit Architecture Workshop 151
152 :.space size [,fill].space size Bytes [fill] :.equ SAMPLES, 64 ;Number of samples ;.section.xbss, "b" x_input:.space 2*SAMPLES ;Allocating space (in bytes) to variable. ;... ;Uninitialized variables in Y-space in data memory ;....section.ybss, "b" y_input:.space 2*SAMPLES ;... ;Uninitialized variables in Near data memory (Lower 8Kb of RAM) ;....section.nbss, "b" Var1:.space 4 ; 2 words of space for variable "var1". Var2:.space Microchip Technology dspic30f 16-bit Architecture Workshop 152
153 RAM dspic SFR 2K Bytes ~ 0x07FF RAM 0x0800 RAM Data : RAM dspic X Unimplemented Data & Y Data RAM Size PSV 32K Bytes PSV SFR Space X Data RAM Y Data RAM X Data Area (Unimplemented) 0x07FF 0x0800 0x0nnn 0x0mmm 0x0rrr 0x8000 0xFFFF 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 153
154 RAM 1..xbss -- 0x nbss --.xbss 3..bss --.nbss 4..ybss -- 0x1800 (dspic30f6014) -- 0x0900 (dspic30f2010) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 154
155 .bss.section.bss, "b".align 2 A_Var:.space 4 B_Var:.space 20 C_Var:.space 4.section.bss, "b".align 2 D_Var:.space 4 E_Var:.space 2 F_Var:.space 2 ;... ;.section.xbss, "b" x_input:.space 4*SAMPLES ;Allocating space (in bytes) to variable. ;... ;.section.ybss, "b" y_input:.space 2*SAMPLES ;... ;.section.nbss, "b" var1:.space 2 ;Example of allocating 1 word of space for variable "var1" 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 155
156 dspic30f6014 Data Memory Usage section address alignment gaps total length (dec) xbss 0x x100 (256).nbss 0x x2 (2).bss 0x x24 (36).ybss 0x x80 (128) Total data memory used (bytes): 0x1a6 (422) Dynamic Memory Usage region address maximum length (dec) heap 0x (0) stack 0x1880 0xf18 (3864) Maximum dynamic memory (bytes): 0xf18 (3864) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 156
157 dspic30f2010 Data Memory Usage section address alignment gaps total length (dec) xbss 0x x100 (256).nbss 0x x2 (2).bss 0x x24 (36).ybss 0x x80 (128) Total data memory used (bytes): 0x1a6 (422) Dynamic Memory Usage region address maximum length (dec) heap 0x9a6 0 (0) stack 0x9a6 0x52 (82) Maximum dynamic memory (bytes): 0x52 (82) Stack Request :.ybss (0x926) + Length (0x80) = 0x Microchip Technology dspic30f 16-bit Architecture Workshop 157
158 Program Start-Up dspic C:\Program Files\MPLAB IDE\dsPIC_Tools \support\templates\assembly tmp6010.s & tmp6014.s -- Tmp6010_srt.s & tmp6014_srt.s Microchip Technology dspic30f 16-bit Architecture Workshop 158
159 tmp6010.s & tmp6014.s.bss,.nbss,.xbss,.ybss dspic reset reset: (Label) Reset Vector 00 goto reset reset: 0x text ;Start of Code section reset: MOV # SP_init, W15 ;Initalize the Stack Pointer MOV # SPLIM_init, W0 ;Initialize the Stack Pointer Limit Register MOV W0, SPLIM 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 159
160 (disassembly) ( ) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 160
161 crt0.o crt1.o \dspic_tools\support\templates\assembly\tmp6014_srt.s Project Object File Crt0.o crt0.o Initialized Data Crt1.o 1. Reset Crt0.o _reset 2. (W15 & SPLIM) 3. PSVPAG CORCON (.const ) User s main 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 161
162 tmp6010_srt.s & tmp6014_srt.s.equ 30F6014, 1.include "\pic30_tools\support\inc\p30f6014.inc ;... ;Initialized variables in X,Y-space in data memory ;....section.xdata, "d".align 32 ;Aligns the next word to be stored to a multiple of 32 x_in:.hword 0x1111, 0x2222, 0x3333, 0x4444, 0x5555 ; y_in: ;.text _main:.section.ydata, "d".hword 0x1234, 0x5678, 0x9abc, 0xdef0, 0xabab CALL _wreg_init ;Start of Code section ;Call _wreg_init subroutine 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 162
163 --- crt0.o Reset Vector _reset Main 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 163
164 Data Memory Usage section address total length (dec) xbss 0x800 0x80 (128).xdata 0x880 0x20 (32).nbss 0x8a0 0x2 (2).ndata 0x8a2 0xa (10).ybss 0x1800 0x80 (128).ydata 0x1880 0xa (10) Total data memory used (bytes): 0x136 (310) crt0.o 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 164
165 .section.data, d.data &.ndata RAM.section.data, d D1:.long 0x ; 4 bytes D2:.word 0x55AA ; 2 bytes D3:.byte 0xA5.section.ndata, d near RAM.section.ndata,"d" D4:.float ; 4 bytes D5:.double ; 8 bytes 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 165
166 .section.xdata, d.xdata &.ydata X Data RAM.section.xdata, d D1:.long 0x ; 4 bytes D2:.word 0x55AA ; 2 bytes D3:.byte 0xA5.section.ydata, d Y Data RAM.section.ydata,"d" D4:.float ; 4 bytes D5:.double ; 8 bytes 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 166
167 0b , 0B , x55AA, 0X00FF Floating IEEE-754 format Fixed-Point Number Q15 format 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 167
168 .byte 8-bit data format.word 16-bit data format.hword 16-bit data format.long 32-bit data format.int bit data format.fixed 16-bit Q15 data format.float 32-bit IEEE -754 float format.single 32-bit IEEEE-754 float format.double 64-bit IEEE-754 float format.ascii null byte (0x00).assiz -- null byte (0x00) 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 168
169 (Label) : _. (Local Label) 1: 10 0 ~ 9 b f print_string: mov w0,w1 cp0.b [w1] bra z,9f mov.b [w1++],w0 call print_char bra 1b 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 169 9: return
170 ROM Data.section.const, r Program Memory.section.const, "r" ; The following symbols (C1 and C2) will be placed ; in the named section ".const". C1:.word 0x3132 C2:.word 0x3334 hello:.ascii "Hello world!\n\0" 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 170
171 Program Memory tblpage (name) Get page for Table Read/write operations tbloffset (name) Get pointer for Table Read/write operations psvpage (name) Get page from PSV data window operations psvoffset (name) Get pointer from PSV data window operations paddr (label) Get 24-bit address of label in Program Memory handle (label) Get 16-bit reference of label in Program Memory.sizeof. (name) Get size of section name in address units.startof. (name) Get starting address of section name 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 171
172 Table Read/Write Table Read TBLRDL.B, TBLRDL.W, TBLRDH.B, TBLRDH.W Table [Wn] 16-bit Page 24-bit #tblpage (label name) TBLPAG #tbloffset (label name) [Wn] 64KW 2004 Microchip Technology dspic30f 16-bit Architecture Workshop 172
173 Table Read ; ;Tone table is placed as a loopup table in program memory.section.const,"r".palign 4 ToneTable:.hword 0x1370,0x1398,0x13B0,0x13C6,0x13D9,0x13E9,0x13F5,0x13FC.hword 0x13FF,0x13FC,0x13F5,0x13E9,0x13D9,0x13C6,0x13B0,0x1398.hword 0x137F,0x1366,0x134E,0x1338,0x1325,0x1315,0x1309,0x1302.hword 0x1300,0x1302,0x1309,0x1315,0x1325,0x1338,0x134E,0x1356; ;.section.text, x ; : : : ; mov #tblpage(tonetable),w0 ;Get upper address (page) mov W0,TBLPAG ;Load address into PSVPAG mov #tbloffset(tonetable),w0 ;Get lower address (offset) of text ;in program memory tblrdl [W0++],W1 ; Get ToneTable into the W Microchip Technology dspic30f 16-bit Architecture Workshop 173
Section1_16bit Arc.ppt
16-bit Elite Program 2009 Summer Section-1 Microchip 16-bit 2005 Microchip Technology Incorporated. All Rights Reserved. Slide 1 MCU CPU (NOP),, (Data Memory), I/O CPU w. ALU/Working Reg. Data Mem. Data
2/80 2
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