2.1 Altera Quartus (SOPC) SOPC Quartus (PLD) Quartus FPGA CPLD 2.1 Quartus
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1 2 Quartus Quartus 2.3 Quartus
2 2.1 Altera Quartus (SOPC) SOPC Quartus (PLD) Quartus FPGA CPLD 2.1 Quartus
3 2.1 Quartus
4 2.1.1 Quartus 2.2 Quartus
5 Text Editor Block&Symbol Editor MegaWizard Plug-In Manager Assignment Editor Floorplan Editor SOPC Builder DSP Builder Software Builder Analysis&Synthesis VHDL VerilogHDL AHDL Design Assistant RTL Viewer LogicLock Window Floorplan Editor VQM Writer Fitter Assignment Editor Floorplan Editor Chip Editor Report Window Incremental Fitting Timing Analyzer Report Window Simulator Waveform Editor EDA EDA Netlist Writer Floorplan Editor LogicLock Window SignalTap II SignalProbe Chip Editor RTL Viewer Assembler Programmer Convert Programming Files Chip Editor Resource Property Editor Change Manager 2.2 Quartus
6 2.1.2 EDA Quartus EDA Quartus EDA 2.3 EDA
7 VHDL (.vhd) VerilogHDL (.v) Quartus EDA EDA Quartus Quartus EDIF (.edf) Verilog Quartus (.vqm) EDA EDA Quartus EDA Netlist Writer EDA Quartus Quartus Assembler Quartus EDA EDA Verilog (.vo) VHDL (.vho) VQM (.sdo) Tcl (.tcl) IBIS (.ibs) STAMP (.data.mod.lib) Quartus EDA 2.3 EDA
8 Quartus EDA NativeLink Quartus EDA Quartus ( Tcl ) Quartus Makefile 2.4
9 2.4 Quartus Tcl Makefile
10 Quartus Shell quartus_sh Quartus Shell Quartus Tcl Verilog (.v) VHDL (.vhd) Verilog Quartus (.vqm) (.tdf) (.bdf) EDIF (.edf) quartus_sim quartus_tan quartus_map quartus_fit Design Assistant quartus_drc Compiler Database quartus_cdb EDA Netlist Writer quartus_eda Assembler quartus_asm Software Builder quartus_swb quartus_pgm quartus_cpf EDA Verilog (.vo) VHDL (.vho) VQM (.sdo) 2.4
11 2.1.4 Quartus 1 Altera Quartus LogicLock LogicLock
12 2 IP Quartus SOPC Builder SOPC Builder (SOPC) IP ( ) SOPC Builder Altera MegaWizard Plug-In Manager Quartus (LPM) Altera/AMPP SM IP Megafunctions
13 3 I/O Quartus I/O ( ) (PCB)
14 4 Quartus Altera FPGA Quartus 4.0 FIFO RAM 5 CPLD FPGA HardCopy ASIC CPLD FPGA Quartus FPGA IP HardCopy Stratix FPGA ASIC
15 6 Quartus (GUI) Quartus Synopsys (SDC) Quartus (Tcl)
16 7 Quartus Quartus Quartus 4.0 MAX+PLUS Quartus Quartus
17 2.2 Quartus PC Quartus Altera (1) 400 MHz 512 MB (2) 800 MB Quartus (3) Microsoft Windows NT 4.0(Service Pack 4 ) Windows 2000 Windows XP
18 (4) Microsoft Windows SVGA (5) CD-ROM (6) ByteBlaster ByteBlasterMV (LPT ) MasterBlaster USB-Blaster MasterBlaster APU(Altera Programming Unit) USB ( Windows 2000 Windows XP) (7) Microsoft IE 5.0 (8) TCP/IP
19 2.2.2 Quartus Quartus ( Quartus 4.0 ) (1) Quartus Quartus ( 2.5 ) install.exe
20 2.5 Quartus
21 (2) Install Quartus and Related Software Quartus ( 2.6 ) GNU Tools and Excalibur Component ModelSim- Altera
22 2.6 Quartus
23 (3) 2.7 Quartus ( )
24 2.7 Quartus
25 EDA 2.8
26 2.8
27 2.8 Next> Quartus (4) Quartus
28 2.2.3 Quartus 1 Quartus Altera (license.dat) Altera Quartus node-locked(fixedpc) license network license(floatpc FLOATNET FLOATLNX) Quartus
29 (1) network license( ) node-locked license( ) Quartus license.dat Altera MAX+PLUS (2) network license(floatpc FLOATNET FLOATLNX) FLEXlm (FLEXlm license manager server) (3) node-locked(fixedpc) (Sentinel Software Guard) (4) Quartus (5) (license.dat)
30 2 Quartus 30 Altera Altera Licensing ASCII license.dat (1) Quartus Altera ID (2) network license( ) G 5 (Gxxxxx) node-locked license( ) (Software Guard) T (Txxxxxxxxx)
31 (3) (NIC) NIC < > \quartus4\bin\lmutil lmhostid < > ipconfig /all 2.9
32 2.9 (NIC)
33 (1) IE Altera (2) node-locked license( ) FIXEDPC network license( ) FLOATPC FLOATNET FLOATLNX (3)
34 (4) Altera license.dat 2.10
35 Daemon 2.10 Node-Locked( )
36 2.11 PC
37 HOST ID Daemon 2.11 Network( )
38 3 license.dat Daemon HOST ID NIC ID ( VENDOR) SERVER <hostname> 00E04C6E013E <port number> VENDOR alterad <path to daemon executable> USE_SERVER HOST ID NIC ID
39 (1) license.dat 2.1
40 2.1 <hostname> <port number> EDA_Altera PC alterad<path to daemon executable> Altera Vendor Daemon \<Quartus >\bin\alterad.exe
41 (2).dat (3).dat license.dat.txt FEATURE FEATURE \ 4 Quartus 1) Quartus Quartus
42 (1) Quartus (2) Specify valid license file Tools Options License Setup 2.12
43 LM_LICENSE_FILE AMPP/MegaCore 2.12 Options License Setup
44 (3) License file license.dat <host> PC <port> license.dat 2.11 (4) OK AMPP MegaCore License Setup Licensed AMPP/MegaCore functions
45 2) Windows NT Windows 2000 Windows XP Windows NT Windows 2000 Windows XP Quartus Windows NT (1) (2) (3)
46 (4) LM_LICENSE_FILE (5) < > \flexlm\license.dat ( <host> <port> license.dat ) (6) Windows 2000 Windows XP (1) (2) (3) 2.13 (4) 2.13
47 2.13
48 2.14
49 (5) 2.14 (6) LM_LICENSE_FILE (7) < > \flexlm\license.dat ( <host> <port> license.dat ) (8) Quartus LM_LICENSE_FILE 2.12 Options License Setup Use LM_LICENSE_FILE variable
50 2.3 Quartus Quartus EDA MAX+PLUS Quartus Quartus Quartus (GUI) MAX+PLUS 2.15 Quartus
51 Quartus Analysis & Elaboration Quartus Integrated Analysis & Synthesis Quartus Quartus Quartus Quartus (.vo/.vho,.sdo) / (.sof/.pof) / 2.15 Quartus
52 2.16 Quartus (GUI)
53 Project Navigator Status Node Finder Messages Change Manager Tcl console 2.16 Quartus
54 1 Project Navigator Project Navigator Hierarchy MAX+PLUS (Hierarchy Display) Files Design Units 2 Status Status MAX+PLUS
55 3 Node Finder Node Finder MAX+PLUS Search Node Database 4 Message Message MAX+PLUS Quartus 5 Change Manager Change Manager Chip Editor
56 6 Tcl Console Tcl Console (GUI) Tcl Tcl MAX+PLUS View Utility Windows MAX+PLUS Quartus MAX+PLUS
57 (1) Tools Customize (2) Customize General Look & Feel MAX+PLUS 2.17
58 2.17 Customize
59 (3) Apply Quartus MAX+PLUS 2.18
60 2.18 Quartus MAX+PLUS
61 2.4 Quartus EDA EDIF VQM 2.19
62 Quartus Quartus Quartus Verilog VHDL AHDL MegaWizard Manager.bdf.tdf.vhd.vhdl.v.vlg.edif.edf Exemplar Synopsys Synplicity.bdf.gdf.bsf.sym.tdf.vhd.v.edf.edif.v,.vlg,.vhd,.vhdl,.vqm BlockSymbol Text Text Text Text Text Quartus 2.19
63 2.4.1 Quartus (New Project Wizard) EDA MAX+PLUS Quartus File Convert MAX+PLUS Project MAX+PLUS (.acf) Quartus Quartus Quartus
64 2.20 New Project Wizard EDA
65 MAX+PLUS 2.20 New Project Wizard
66 Assignments Settings EDA Quaruts Quartus Settings Files Settings 2.21
67 / / EDA 2.21 Settings
68 2.4.2 File New 2.22 New Device Design Files Block Diagram/Schmatic File OK 2.23
69 2.22
70 2.23 Quartus
71 Quartus (Block Editor) (Schematics) (Block Diagrams) Quartus (Block Design Files) MAX+PLUS (Graphic Design Files) Quartus MAX+PLUS 2.23 Quartus Block Editor
72 1 Quartus (LPM) (1) 2.23 Edit Insert Symbol 2.24 Symbol
73 2.24 Symbol
74 (megafunctions) MegaWizard Plug-In Manager (others) MAX+PLUS 74 (primitives) Altera /
75 (2) (+) Symbol OK Cancel 2.25
76 2.25
77 (3) 74 (2) (others) maxplus
78 2.26
79 (4) Symbol Symbol Symbol (5) ( inst1 ) Properties 2.27 General Ports Parameters Format
80 2.27
81 2 (Block Diagram) (Top-Down) ( ) ( ) (1) (2) Block Properties 2.28 I/Os 2.27
82 I/Os 2.28 dataa Add Existing Block I/Os reset clk datab ctrl1 addra addrb General Block_A
83 2.28
84 (3) (Node Line) (Bus Line) (Conduit Line) 2.29
85 2.29
86 (4) I/O (Conduit Properties) 2.30
87 2.30
88 (5) I/O Properties I/O 2.31 (Mapper) Properties General ( ) Mappings I/O Add View Show Mapper Tables
89 2.31 I/O
90 (6) (HDL).bdf Create Design File from Selected Block (AHDL VHDL Verilog HDL Schematic) 2.32 OK Quartus
91 2.32
92 Quartus Update Design File from Selected Block (Y) Quartus
93 3 MegaWizard Plug-In Manager MegaWizard Plug-In Manager Altera LPM(Library Parameterized Megafunction) MegaCore( FFT FIR ) AMMP(Altera Megafunction Partners Program PCI DDS ) MegaWizard Plug-In Manager
94 Tools MegaWizard Plug-In Manager Symbol ( 2.24) MegaWizard Plug-In Manager Quartus MegaWizard Plug-In Manager qmegawiz Quartus MegaWizard Plug-In Manager 2.2 MegaWizard Plug-In Manager
95 2.2 MegaWizard Plug-In Manager < >.bsf < >.cmp < >.inc < >.tdf < >.vhd < >.v < >_bb.v < >_inst.tdf < >_inst.vhd < >_inst.v VHDL ( ) AHDL ( ) AHDL VHDL Verilog HDL Verilog HDL ( Hollow body Black box) EDA AHDL ( ) VHDL ( ) Verilog HDL ( )
96 Quartus MegaWizard Plug-In Manager (1) Tools MegaWizard Plug-In Manager Symbol ( 2.24) MegaWizard Plug-In Manager 2.33
97 2.33 MegaWizard Plug-In Manager
98 (2) Next> 2.34
99 2.34 MegaWizard Plug-In Manager
100 (3) Next> Finish (3) Documentation Finish
101 (4) MegaWizard Plug-In Manager Symbol ( 2.24) (Megafunctions) 2.35 OK 2.36 ( View Show Parameter Assignments)
102 2.36 Ports (Unused Used) Unused Parameters I/O Quartus / - RAM
103 MegaWizard Plug-In Manager 2.35
104 2.36
105 4 (Block Symbol Files,.bsf) Quartus
106 (1) File Create/Update Create Symbol Files for Current File (.bsf) 2.37 (Y)
107 2.37
108 (2) Symbol ( 2.24 ) OK (3) Edit Selected Symbol Edit Selected Symbol 2.38
109 2.38
110 5 ( / ) / 1) (Node Line) (Bus Line) Quartus
111 2) (Input) (Output) (Bidir) Symbol (primitive) (pin) OK Symbol Ctrl
112 3) A0 A1 clk n A[n- 1..0] A pin_name
113 FIR
114 2.39 FIR
115 6 Tools Options Quartus Category Block/Symbol Editor 2.40
116 2.40
117 7 File Save As 2.41 Add file to current project
118 2.41 (Save As)
119 File New ( 2.22 ) Device Design Files AHDL File( Verilog HDL File VHDL File) OK AHDL Verilog HDL VHDL AHDL File Ahdl1.tdf Verilog HDL File Verilog1.v VHDL File Vhdl1.vhd 2.42 Edit
120 AHDL Verilog HDL VHDL / 2.42
121 2 (*) Quartus (1) (2) Insert Template
122 Quartus (AHDL VHDL Verilog HDL) (3) Template Section OK (4)
123 2.43
124 Category Text Editor 4 AHDL.tdf VHDL.vhd Verilog HDL.v
125 (1) File New Other Files Memory Initialization File(MIF) OK OK 2.44
126 Hex Mif 2.44
127 (2) 2.45 (3) 2.45
128 ASCII ASCII 2.45
129 View Cells Per Row ( ) Address Radix Binary( ) Hexadecimal( ) Octal( ) Decimal( ) Memory Radix Binary Hexadecimal Octal Signed Decimal( ) Unsigned Decimal( ) (4) Value (5).hex.mif
130 2 Altera MegaWizard Plug-In Manager RAM 8 (1) Tools MegaWizard Plug-In Manager Create a new custom megafunction variation Next
131 (2) storage LPM_RAM_DP LPM_RAM_DP+ RAM Altera Cyclone Cyclone Stratix GX altsyncram RAM LPM_RAM_DP+
132 2.46 RAM
133 (3) Next (4) With one read port and one write port As a number of words Next (5) Next (6) (Single clock) Next (7) 5 6 Next (8) 7.mif.hex 2.47
134 MIF HEX 2.47
135 (9) Finish RAM (10) Symbol Project RAM 2.48
136 2.48 Project RAM
137 3 (1) my_rom.mif (2) MegaWizard Plug-In Manager 2.46 LPM_ROM SinROM (3) MegaWizard Plug-In Manager
138 (4) MegaWizard Plug-In Manager 3 my_rom.mif (5) Finish ROM (6) ROM SinROM (7) MegaWizard Plug-In Manager LPM_ADD_SUB Adder
139 1 16 / Next 4 (pipeline) Finish (8) 10 ROM (9) 2.49
140 2.49 DDS
141 Quartus (Analysis & Synthesis) Analysis & Synthesis Quartus (Integrated Synthesis Support) VHDL(.vhd) Verilog(.v) Integrated Synthesis Quartus VHDL Verilog AHDL EDA VHDL Verilog HDL Quartus EDIF (.edf) VQM (.vqm)
142 Quartus Altera (.bdf) MAX+PLUS (.gdf) 2.50 quartus_map quartus_drc Quartus Tcl ( View Utility Windows Tcl Console) quartus_map (Analysis & Synthesis)
143 Quartus Analysis & Synthesis Verilog 1995 (IEEE ) Verilog 2001 (IEEE ) VHDL 1987(IEEE ) 1993(IEEE ) Analysis & Synthesis Verilog 2001 VHDL 1993 (.lmf) Quartus Quartus Assignments Settings Settings Verilog HDL Input VHDL Input
144 (.lmf) VHDL (.vhd) Verilog HDL (.v) AHDL (.tdf) (.bdf) Quartus Quartus Quartus quartus_map VHDL (.vhd) Fitter Verilog HDL (.v) (.rdb) HDL EDA EDA (.rpt.htm) EDIF (.edf) Quartus Verilog Quartus (.vqm) quartus_drc RTL 2.50 Quartus
145 2.5.2 Quartus 1 Quartus Ananlysis & Synthesis Quartus Tools Compiler Tool Quartus 2.51
146 Analysis & Synthesis Assembler EDA Analysis & Synthesis EDA EDA Assembler EDA Fitter Fitter Fitter 2.51 Quartus
147 (1) 2.51 Analysis & Synthesis (2) Processing Start Start Analysis & Synthesis (3) Quartus 2.52
148 Start Analysis & Synthesis 2.52
149 2 Quartus 2.53
150 (TDF BDF Verilog HDL VHDL VQM EDIF Netlist files) Analysis & Synthesis Fitter Assembler.vo.vho 2.53 Quartus
151 2.3 Quartus
152 2.3 Quartus Analysis & Synthesis quartus_map Fitter quartus_fit Timing Analyzer qartus_tan Assembler quartus_asm EDA Netlist Writer quartus_eda Fitter Quartus Analysis & Synthesis Analysis & Synthesis Fitter Programmer Object Files(.pof) SRAM Object Files(.sof) Hexadecimal (Intel-Format) Output Files(.hexout) Tabular Text Files(.ttf) Raw Binary Files(.rbf).pof.sof Quartus MasterBlaster ByteBlaster.hexout,.ttf.rbf Altera Assembler Fitter EDA EDA Netlist Writer Analysis & Synthesis Fitter Timing Analyzer
153 2.5.3 Quartus Analysis & Synthesis Fitter Quartus Settings Settings 2.54
154 EDA 2.54 Settings Device
155 (1) Assignments Settings (2) Hierarchy Settings (3) Quartus 1
156 (1) Settings Category Device Assignments Device Settings Device 2.54 (2) Family Stratix (3) Available devices Auto device selected by the Fitter from the 'Available devices' list (4) Show in 'Available devices' list
157 2 (1) Settings Category Compilation Process 2.55
158 2.55 Settings Compilation Process
159 (2) Use Smart compilation (3) Preserve fewer node names to save disk space (4) VQM 3 Analysis & Synthesis Analysis & Synthesis (1) Settings Category Analysis & Synthesis Settings 2.56
160 2.56 Settings Analysis & Synthesis Setting
161 (2) Optimization Technique Speed f MAX Area Balanced (3) Analysis & Synthesis Settings Category VHDL Input Verilog HDL Input VHDL Verilog HDL Quartus (.lmf)
162 (4) EDIF (.edf) Verilog Quartus (.vqm) Quartus Category Synthesis Netlist Optimizations Perform WYSIWYG Primitive Resynthesis Perform Gate- Level Register Retiming Perform WYSIWYG Primitive Resynthesis Quartus (Atom Netlist) (Un-map) (Re-map) Altera Quartus 2.57 APEX Cyclone Cyclone MAX Stratix Stratix GX
163 Atom Netlist LE LE LE Un-map Re-map LE LE Place & Route 2.57 Perform WYSIWYG Primitive Resynthesis Quartus
164 Perform Gate-Level Register Retiming Quartus 2.58 APEX Cyclone Cyclone MAX Stratix Stratix Stratix GX Perform WYSIWYG Primitive Resynthesis
165 D Q 10ns D Q 5ns D Q Gate-Level Registe Retiming D Q 7ns D Q 8ns D Q 2.58 Perform Gate-Level Register Retiming
166 4 Fitter( ) (1) Settings Category Fitting Settings 2.59
167 2.59 Settings Fitter Setting
168 (2) (Timing-driven compilation) Optimize timing Optimize hold timing Optimize I/O cell register placement for timing IO Paths and Minimum TPD Paths Timing-driven compilation Quartus Fitter effort Standard Fit Fast Fit Auto Fit Quartus
169 (3) Physical Synthesis Optimizations Physical Synthesis Optimizations MAX Stratix Stratix GX Cyclone Settings Category Fitter Settings Physical Synthesis Optimizations Physical Synthesis Optimizations 2.60
170 2.60 Settings Physical Synthesis Optimizations
171 (Perform physical synthesis for combinational logic) Quartus (LUT) 2.61
172 a c LUT d a e c d LUT e f g LUT f LUT g 2.61
173 2.61 Quartus DSP I/O (Perform register duplication) Quartus 2.62
174 1 LE 1 LE LE LE LE 2 LE LE 2 LE LE 2.62
175 (Perform register retiming fitter) Quartus Perform Gate-Level Register Retiming (4) Physical synthesis effort Normal Extra Fast Normal Extra Fast Normal
176 2.5.4 Quartus 1) (Assignment Editor) (1) Assignments Assignment Editor (Category) Locations pin Assignments Pins 2.63
177 2.63 Assignment Editor
178 (2) Assignment Editor To CLK (3) Location (4) Assignment Editor (5) Processing Start Start I/O Assignment Analysis I/O OK
179 2) (Floorplan Editor) (1) Assignments Timing Closure Floorplan (Timing Closure) Timing Closure View Package Top Package Bottom Interior LABs Interior Cells (2) Node Finder View Utility Windows Node Finder Node Finder
180 (3) Node Finder Named * Filter Pins: all Pins: unassigned List Nodes Found 2.64 (4) Nodes Found Timing Closure Floorplan (GDF) (BDF) (5) Processing Start Start I/O Assignment Analysis I/O OK
181 2.64 Floorplan Editor Node Finder
182 I/O Processing Start Start I/O Assignment Analysis Tcl quartus_fit < > --check_ios I/O Start I/O Assignment Analysis (.pin) Processing Compilation Report Compilation Report Fitter
183 I/O (Analyze I/O Assignment Summary) (Floorplan View) (Pin-Out File) (Resource Section) (Fitter Messages)
184 Start I/O Assignment Analysis Start I/O Assignment Analysis Start I/O Assignment Analysis Assignments Back-Annotate Assignments... Pin & device assignments 2.65 QSF
185 2.65 Start I/O Assignment Analysis
186 2.5.5 Quartus 2.51 Processing Start Compilation (1) Processing Start Compilation 2.66
187 (2) Locate in Design File Help (3) 2.66
188 2.67
189 2.66
190 2.67
191 2.5.6 ( ) (Floorplan Editor) Quartus (1) (Timing Closure Floorplan) LogicLock( ) (2) (Last Compilation Floorplan)
192 (Interior Logic Cells) (Interior LABs) (Field View) (Top View) (Bottom View) 1 1) ( 2.67 ) Fitter Fitter Floorplan View (Interior Logic Cells) View Color Legend Window 2.68
193 (LAB) (LE) 2.68
194 2) View Routing Show Node Fan-Out View Routing Show Node Fan-In 2.69 View Routing Show Node Fan-In Show Node Fan-Out
195 3) View Equations 2.69
196 2.69
197 4) (Field View) Field View Field View 2.70
198 DSP M4K M512 I/O M-RAM 2.70 Field
199 View Interior Cells 2 (Timing Closure Floorplan) Quartus 1) Assignments Timing Closure Floorplan
200 Quartus 2.71
201 Quartus Quartus LogicLock 2.71
202 2) LogicLock LogicLock View MegaLAB LAB (Field View)
203 3) View Routing (1) (Show Paths between Nodes ) I/O (2) (Show Node Fan-In Show Node Fan-Out ) I/O
204 (3) (Show Routing Delays ) I/O (4) (Show Connection Count ) (5) (Show Physical Timing Estimate ) (Potential Destination Resources) ( ) Field
205 (6) (Show Routing Congestion ) ( ) Routing Congestion Setting (7) (Show Critical Paths ) Critical Path Settings (Slack)
206 (8) LogicLock (Show LogicLock Regions Connectivity ) LogicLock LogicLock 4) LogicLock MegaLAB LAB
207 (1) (2) (Assignment Editor) (3) Node Finder (4) LogicLock (5) (Project Navigator) Hierarchy LogicLock
208 (1) File New (2) Other Files Vector Waveform File OK 2.72
209 2.72 Quartus
210 (3) 1 s Edit End Time s ms(10 3 s) s(10 6 s) ns(10 9 s) ps(10 12 s) OK (4) File Save As ( ) *.vwf Add file to current project
211 2 VWF (1) View Utility Windows Node Finder Node Finder 2.73 Name Insert Node or Bus Insert Node or Bus Node Finder
212 (2) Node Finder Filter Pins:all Named * List Nodes Found (3) Nodes Found Name Shift Ctrl (4) Node Finder
213 2.73
214 3 1) ( clk) Value Clock Timing Setting Clock setting 2.74
215 2.74
216 2) ( d) Value Count Value Value Arbitrary Value 3) Value 2.75
217 2.75
218 Edit Value 2.76 File Save
219 2.76
220 Assignments Settings Settings Category Simulator 2.77
221 2.77
222 2 Functional Processing Generate Functional Simulation Netlist Timing 3 Processing Start Simulation
223 Quartus (Simulator Tool) Quartus MAX+PLUS Tools Simulator Tool 2.78
224 2.78 Quartus
225 ) (1) Processing Simulation Report (2) 2.78 Report
226 2) Simulator Simulation Waveforms 2.79
227 2.79
228 2 (1) (2) (3) Insert Time Bar
229 (4) Properties (5) Properties (Radix) (6) Edit Grid Size (7) View Compare to Waveforms in File
230 VWF VWF VWF
231 2.80
232
233 2.4 (t SU ) (t H ) f MAX ( ) t SU ( ) t H ( ) t CO ( ) t PD ( ) t CO t PD
234 2.7.2 Settings ( ) 1 Assignments Wizards Timing Wizard 2.81 f MAX
235 2.81 1
236 Next 2.82 Next 2.82 Finish
237
238 2 Settings Assignments Timing Settings Settings Timing Requirements & Options 2.83
239 2.83 Settings Timing Requirements & Options
240 2.83 Settings for individual clock signals Clocks 2.84 New Clock settings Applies to node Node Finder (Relationship to other clock settings) Independent of other clock settings Required Duty Cycle
241 2.84
242 2.84 Based on Drived Clock Requirements 2.85
243 2.85
244 3 (Assignment Editor)
245 2.86
246 2.86 (1) Assignments Assignment Editor (2) Category Timing (3) To ( clk* f?) To To Node Finder To To Select Time Group
247 Assignments Time Groups (4) (3) From (5) Assignment Name (6) Value (7) File Save
248 2.7.3 (1) Processing Start Start Timing Analyzer (2) Processing Start Start Minimum Timing Analysis
249 (3) Tools Timing Analyzer Tool 2.87 tpd(t PD ) tsu(t SU ) tco(t CO ) th(t H )
250 2.87 Quartus
251 2.7.4 Timing Analyzer Locate in Assignment Editor List Paths Locate in Timing Closure Floorplan 2.88
252 2.88
253 2.8 Quartus Altera Quartus Assembler (.pof) SRAM (.sof) Quartus (Programmer)
254 Altera MasterBlaster ByteBlasterMV(ByteBlaster MultiVolt) ByteBlaster USB-Blaster Ethernet Blaster Altera (APU) ByteBlasterMV MasterBlaster ByterBlasterMV MasterBlaster USB USB-Blaster Ethernet Blaster ByterBlaster ByteBlaster MasterBlaster USB-Blaster USB Ethernet Blaster Ethernet ByteBlaster
255 Quartus (.cdf) CDF Quartus (Passive Serial mode) JTAG (Active Serial Programming mode) (In-Socket Programming mode)
256 JTAG EPCS1 EPCS4 Altera (APU) CPLD Quaruts (1) Tools Programmer < >.cdf 2.89
257 2.89
258 (2) File Save As CDF 2 (1) Mode Passive Serial (2) Hardware Setup 2.90
259 2.90
260 (3) Add Hardware Add Hardware 2.90 (4) Add Hardware type ByteBlasterMV or ByteBlaster MasterBlaster OK Hardware Setup (5) Hardware Setup Available hardware items Select Hardware Close 2.91 (6) File Save CDF Add File
261 2.91
262 3 (1) MasterBlaster MasterBlaster RS-232 RS-232 USB USB ByteBlasterMV ByteBlasterMV DB25-to- DB25 (2) Start OK
263 4 SRAM (.sof) JTAG JTAG Program/Configure Mode JTAG 5 JTAG Examine (.pof)
264 JTAG (1) JTAG CDF (2) Add Device Select Devices 2.92
265 2.92 JTAG
266 (3) Device family (4) Device name OK (5) File Save CDF Altera Windows 2000
267 (1) (2) / (3) / / (4) / (5)
268 (6) (7) Altera <Quartus >\drivers\win2000\win2000.inf 2.93 (8) Altera ByteBlaster (9) Altera ByteBlaster 2.94
269 < Quartus >\drivers\win2000\ 2.93
270 2.94
271 2.90
272 1 Quartus MAX+PLUS 2 Quartus 3 MAX+PLUS Quartus 4 Quartus
273 5 6 7 Quartus
274 EN 1 Hz CLR
275 (1) (2) ( AHDL) (3) (4) (5) (6)
276
277 Gate (a) Gate (b) 2.96
AL-MX200 Series
PostScript Level3 Compatible NPD4760-00 TC Seiko Epson Corporation Seiko Epson Corporation ( ) Seiko Epson Corporation Seiko Epson Corporation Epson Seiko Epson Corporation Apple Bonjour ColorSync Macintosh
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niosii H:\DB2005\project\niosDK\Example\NiosSmall QuartusII4.2 File -> New Project Wizard Diectory,Name,Top-Level Entity Add Files EDA Tools Setting Finish, OK H:\DB2005\project\niosDK\Example\NiosSmall
Cadence SPB 15.2 VOICE Cadence SPB 15.2 PC Cadence 3 (1) CD1 1of 2 (2) CD2 2of 2 (3) CD3 Concept HDL 1of 1
Cadence SPB 15.2 VOICE 2005-05-07 Cadence SPB 15.2 PC Cadence 3 (1) CD1 1of 2 (2) CD2 2of 2 (3) CD3 Concept HDL 1of 1 1 1.1 Cadence SPB 15.2 2 Microsoft 1.1.1 Windows 2000 1.1.2 Windows XP Pro Windows
KT-SOPCx开发套件简明教程
V2.03 2005-9-1 FPGA SOC FPGA/SOPC IT QuartusII NiosII IDE FPGA/SOPC FPGA/SOPC FPGA/SOPC CT-SOPCx FPGA/SOPC CPLD/FPGA www.fpga.com.cn CPLD/FPGA FPGA QuartusII NiosII CPU SOPC SOPC Builder NiosII IDE 1 www.21control.com
(Load Project) (Save Project) (OffLine Mode) (Help) Intel Hex Motor
1 4.1.1.1 (Load) 14 1.1 1 4.1.1.2 (Save) 14 1.1.1 1 4.1.2 (Buffer) 16 1.1.2 1 4.1.3 (Device) 16 1.1.3 1 4.1.3.1 (Select Device) 16 2 4.1.3.2 (Device Info) 16 2.1 2 4.1.3.3 (Adapter) 17 2.1.1 CD-ROM 2 4.1.4
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01 1-1 Altera Installer 1-2 1-3 FBBCar 1-4 FPGA 1. 2. 3. 4. FBBCar Altera FPGA FBBCar Quartus II ModelSim-Altera 1-1 1-1 FBBCar 1 220 2 10k 2 1k 2 2k 2 470k 2 1 950nm 2 2 38kHz 2 2 3PIN 2 2 1 1 2 01 Altera
图 片 展 示 : 资 源 简 介 : FPGA Altera CycloneII EP2C5T144C8 (4608 个 LE) 2 路 有 源 晶 振 (50M,25M) AS & JTAG 标 准 接 口 VGA 接 口 UART 接 口 蜂 鸣 器 8bit 并 行 DAC 8 路 按 键
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