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1 阻变存储器可靠性与表征高滨清华大学微纳电子系

2 存储器被广泛应用于电子产品互联网国防航天等各领域存储器年产值超过 700 亿美元, 占比超过集成电路总市场的 1/4 存储器的需求逐年增长大数据时代信息技术, 存储器重要性更加突出 2

3 处理器存储器总线总线上的速度延迟额外功耗问题需要探索高速可融合计算与存储的新型器件 3

4 阻变存储器 (RRAM) 4

5 阻变存储器特点单器件特性速度快 : 转变时间 <1 ns 可靠性高 : 循环次数 >10 12, 保持时间 >10 年 /@200 o C 非挥发多值存储高密度 : 器件尺寸 <10 nm, 可三维集成电路特性同时兼备高速度高密度和非挥发性融合计算与存储常关 (normal off), 功耗低非常适合神经形态计算 5

6 21 st Century: Intelligent Era Automatically driving a car Alphago Smart robot Voice Assistant 6

7 Scale up requires energy efficiency Challenge Power hungry High efficiency synapses Power consumed: W Less than a light bulb Stanford, S. B. Eryilmaz et al., IEDM 2015

8 神经形态器件阻变存储器 RRAM 通过改变氧离子浓度调制器件电阻 O 2- 大规模并行生物突触 Na +, Ca 2+ 8

9 忆阻器阵列与神经网络 9

10 规模和速度的提升 8-bit N x M 的向量乘法忆阻器阵列 [ASP-DAC, 2015] CMOS 电路 [Field-Programmable Technology, 2002] 1 个忆阻器 (64 levels) ~ 8-bit 乘法器 + 8-bit 加法强 + 8-bit SRAM 存储器 10

11 RRAM 面临的主要问题机理不清涨落大可靠性不足工艺集成问题模拟阻变特性优化 11

12 RRAM cell optimization Material selection -- Developed several categories of RRAM devices WO x based RRAM shows low RESET current and multi-level storage behavior HfO x based RRAM fabricated with CMOS compatible process. Bit yield >99.9%. TaO x based RRAM shows excellent endurance performance. APL 2013; APL 2014; Nanotechnology

RC ISPP RRAM cell optimization Retention improvement suppressing relaxation effect

Yes YES V BL =V BL, V SL =V SL, V WL =V WL Verify read RESET?

Optimized operation scheme to suppress the relaxation effect is provided Various

13 RC ISPP RRAM cell optimization Retention improvement suppressing relaxation effect Quick and stochastic retention loss after program is observed in some of the bits START Yes YES V BL =V BL, V SL =V SL, V WL =V WL Verify read RESET? No V BL >=V BL _end Yes NO END WL No V BL =V BL +V BL _step BL RRAM Transistor SL SET Optimized operation scheme to suppress the relaxation effect is provided Various characterization methods are utilized to explore the mechanism of relaxation effect EDL 2016; EDL 2017; IMW 2016; APE

1% 0 10 20 Read_ref current(ua) = 1 1T1R array with HfOx/TaOx stack as RRAM cells = 0 >99.

14 Testing results on 16M RRAM chip 100% Probability 10% 1% set1 set100 set500 set1000 reset1 reset100 reset500 reset % Read_ref current(ua) = 1 1T1R array with HfOx/TaOx stack as RRAM cells = 0 >99.9% bit yield; >99% bit yield after 10 4 cycles Develop a foundary+lab platform for future production and application NVMTS 2015; IEDM 2016; IMW 2017; Submit to IEDM

15 Security Application Utilize the variability of HRS resistance, the random key can be generated Good reliability is demonstrated on our RRAM based PUF EDL 2017; VLSI-TSA

16 Requirement of synaptic device Ideal synaptic device: Ideal Filamentary Non-filamentary Enough level number Low current Fast speed Low voltage Good reliability Conductance linearity Linearity Voltage Level number Reliability Current Speed There are some defects for both filamentary device and nonfilamentary device. Device engineering is needed.

17 Challenge of filamentary RRAM Filament connect I-V curve of HfOx based filamentary RRAM Filament rupture Simulated oxygen vacancy distribution Abrupt SET transition is always observed in filamentary RRAM

Electric field increases continuously as filament growing during SET process,

18 Origin of abrupt SET Simulated 2D map of electric distribution of different switching phases Simulated electric potential distribution along filament region Electric field increases continuously as filament growing during SET process, resulting positive feedback which accelerate SET process B. Gao, et al., IEDM 2016, 176

single strong conductive filament Disperse oxygen

19 Improve analog switching Reduce the positive feedback of electric field during SET process Avoid forming single strong conductive filament Disperse oxygen vacancies to a broad region Forming multiple weak conductive filament

shows analog switching at high temperature High temperature

20 Local temperature is a key factor P = exp[ γqe ε f /kt] Ti/HfOx RRAM device exhibits abrupt switching at room temperature, but shows analog switching at high temperature High temperature reduce the influence of electric field during CF formation EDL 2017

21 Insert thermal enhanced layer (TEL) P = exp[ γqe ε f /kt] TEL HfOx RRAM shows excellent analog switching in both SET and RESET by inserting the TEL EDL 2017

22 Insert thermal enhanced layer (TEL) Conductance modulation under identical pulse train after inserting TEL The conductance increases/decreases gradually by applying identical SET/RESET pulses for Ti/TEL/HfOx device. EDL 2017

23 Doping Method P = exp[ γqe ε f /kt] We fabricated HfAlyOx RRAM with ALD multilayer deposition --3 cycles HfOx layer and 1 (or 2) cycles AlOx layer Doping Al could localize the formation oxygen vacancies (Vo) and avoid crystallization

24 Doping Method Doping Process LRS distribution HRS distribution Retention Uniformity and retention are improved by Al doping

25 Connect to a transistor P = exp[ γqe ε f /kt] RESET SET 1T1R cell structure is used Typical I-V curve under DC sweep Transistor is used to limit electric field and avoid overshoot Reliable bi-directional analog switching behavior of 1T1R cell is observed

26 Summary With material engineering, we demonstrate reliable bidirectional analog RRAM with fast speed, low voltage, and good retention

Grey-scale real face recognition Training set from Yale Face Database for experimental face classification The schematic of the perceptron implemented by the 1K bit array A perceptron is

27 Grey-scale real face recognition Training set from Yale Face Database for experimental face classification The schematic of the perceptron implemented by the 1K bit array A perceptron is demonstrated experimentally for grey face pattern classification based on the 1K bit array to verify the capability of the device and the two operation schemes P. Yao, et al. Nat. Commun. 8, 15199, 2017

pattern set consists of 9,000 images by introducing noise to the training images.

28 Experimental test process Set 1: The 24 unseen test images Set 2: Augmented noisy test patterns Set 1: The test database from the Yale Face Database Set 2: Augmented noisy pattern set consists of 9,000 images by introducing noise to the training images. Noise patterns are generated by randomly choosing some pixels and assigning them a random value.

29 Experimental training process The activation function output value of the first class versus the iteration number Initial and final conductance distribution comparison of the first initial state LRS. Inset shows the final conductance map

Energy consumption saving 1000x energy saving

on-chip digital RRAM memory system The two

iteration during training process (around 30 nj

30 Energy consumption saving 1000x energy saving than a Intel Xeon Phi processor with off-chip memory system 20x energy saving than a hypothetical Intel Xeon Phi processor with on-chip digital RRAM memory system The two methods have similar energy consumption per iteration during training process (around 30 nj / iteration). This shows a remarkable energy saving than the traditional way.

31 面临的挑战? 我们未来关于 RRAM 可靠性与表征的研究还存在诸多问题及挑战 RRAM 器件瞬态测量循环次数测试微观原位表征 RRAM 阵列自动测试方法读取速度 31

32 阻变速度的极限 TE BE V TaOX HfO X Voltage(V) ps 0-2.0n -1.0n n 2.0n Time(s) Current(A) 100μ 10μ 1μ Model w/o_rth 800ps data Model w/_rth 50 Ω Probe tip 通过高速脉冲可以屏蔽热效应对阻变过程的影响 Resistance( ) 1M 100k 10k 1k -4.2V -3.4V -3.0V -2.4V -2.8V -7.5V -2.2V -2.0V -1.8V -1.5V 10p 100p 1n 10n 100n 1µ Pulse width(s) 100n Reset Voltage(V) Adv. Ele. Mater. 2017

33 阻变动力学过程通过瞬态电流的测量可以了解阻变动力学过程, 获得神经形态特性的调控方法 Z. Wang, et al, Nature Materials, 2017 C. Du et al, Nano Letters, 2015, 15, 2203

循环次数的极限每次读写切换消耗大量的时间要准确评估器件的循环次数 (endurance), 需要对每次擦写后的电阻进行读取, 单器件需要 10 12

34 循环次数的极限每次读写切换消耗大量的时间要准确评估器件的循环次数 (endurance), 需要对每次擦写后的电阻进行读取, 单器件需要以上的切换阵列上则需要以上的读写次数 M.-J. Lee, et al, Nature Materials, 2011, 10, 625

35 氧空位分布的原位观测要理解阻变微观机理, 了解氧空位的分布及演化情况, 需要原子级的原位表征手段, 对氧空位导电通道的形貌进行三维成像, 并可以随时调控器件的状态 Adv. Mater. 2017

36 CF rupture during RESET

37 CF formation during forming EELS mapping

38 氧空位分布的非破坏性观测要理解氧空位分布与实际器件可靠性之间的关系, 需要非破坏性的物性表征手段, 在实际器件上实时观测氧空位的分布变化 Nanoscale 2017

40 交叉阵列中的串扰阻变存储器阵列在操作中存在多种串扰效应, 为抑制这些效应, 需要对每条 BL WL 同时加电压 ; 受器件特性的影响, 所加电压可能不同因此, 需要开发灵活的阵列测试模块, 可以多通道同时加电压

41 神经网络并行处理基于交叉阵列的神经网络单元研究将是未来相当长时间内的重要方向近期关于阵列操作的文章均发表在 Nature 及其子刊上神经网络最基本的操作是在所有 WL 上同时加不同幅值的电压, 同时在所有 BL 上读取电流, 需要输入多通道的模拟电压值, 同时能够多通道同时读取模拟电流值目前类似的过程都是靠电路或者 FPGA 完成的, 灵活性差周期长, 不适合研发通用阵列测试设备将大大提升研发效率

42 自动校验与弛豫阻变存储器阵列在擦写过程中需要对每个单元反复校验, 以抑制涨落和弛豫效应对 tail bits 的影响单器件的测试程序很容易开发, 但是阵列级的 verify 自动测试方法则是未来急需的工具

43 总结新型存储器将是未来集成电路领域重要的发展方向兼备高速度高密度和非挥发性, 简化存储器系统颠覆传统冯诺依曼架构, 融合计算与存储, 神经形态计算阵列测试将成为未来 RRAM 研究中的主要课题阵列操作模式可靠性一致性神经计算等 RRAM 表征技术需要向极端化发展原子级的原位表征 ps 级脉冲擦写及信号捕捉快速读写阵列单元大规模阵列的自动测试

44 谢谢! 高滨助理教授 / 博士生导师 , gaob1@tsinghua.edu.cn

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2/80 2 2/80 2 3/80 3 DSP2400 is a high performance Digital Signal Processor (DSP) designed and developed by author s laboratory. It is designed for multimedia and wireless application. To develop application