Ultra-Small Low Voltage Drive Input Output Full Range CMOS Dual Operational Amplifier VIO ±6mV, SR=.35V/μs, GBW=55kHz Data Sheet R3DS98EJ2 Rev.2. Apr. 17, 217 Description The READ2351J is input and output full range dual CMOS Operational Amplifier realizing low voltage and low current consumption operation. This IC can be used in minimum operating supply voltage from 1.8V, and in wide ambient temperature range from -4 O C to +125 O C. Available in ultra-small 8 pins TSSOP package. Features Low voltage single supply operation V DD = 1.8V to 5.5V Low input offset voltage V IO ±6.mV Low input bias current I B (1pA). Wide output voltage range V OUT : V SS +.1V to V DD -.1V(@Io=1mA) Supply current (per channel) I DD = 4μA Typ. High slew rate SR =.35V/μs Typ. ( ) reference value of design Product Line-up Type name Product type quality level Package READ2351JSP Low consumption current with high quality level 8 pins plastic TSSOP R3DS98EJ2 Rev.2. Page 1 of 7 Apr. 17, 217
Pin Arrangement Equivalent Circuit (per one channel) Absolute Maximum Ratings <T A =25 o C > Items Symbol Ratings Unit Supply voltage Note.1 VDD -.3 to +6.5 V Differential input voltage VID -VDD to +VDD V Input voltage Note.2 VI -.3 to VDD +.3 V Maximum output current IO 1 ma Power dissipation Note.3 PT 44 mw Junction temperature Tj +15 o C Operating temp. range TA -4 to +125 o C Storage temp. range Tstg -55 to +15 o C Note 1. Please take note that reverse connection of a power supply may cause destruction. 2. Stresses above these ratings may cause permanent damage such as characteristics degradation or destruction. Please do not exceed voltage below of GND-.3V as it is bottom limit. In addition, operation amplifier is operated as normal when input voltage for electrical characteristics is in common mode input voltage range. 3. The value is measured under mounted on a glass epoxy base board (size 1mm 1mm, 1mm thickness, copper foiled surface base board area with 15% solid pattern). Please take note that every package has derating rate s restriction reception. R3DS98EJ2 Rev.2. Page 2 of 7 Apr. 17, 217
Electrical Characteristics <, T A =25 o C > Items Symbol MIN. TYP. MAX. Unit Test Condition Supply voltage VDD - VSS 1.8 5.5 V Input offset voltage VIO ±6. mv Input offset current IIO (1) pa Input bias current IB (1) pa Output high voltage VOH VDD-.1 V IL = 1mA Output low voltage VOL VSS+.1 V IL = 1mA Voltage gain AV 8 12 db RL 1kΩ Channel supply current Common mode rejection ratio Supply voltage rejection ratio Common mode input voltage range Gain bandwidth product IDD/ch 4 8 μa RL=, IO= CMRR 6 8 db SVRR 6 8 db VICM VSS VDD V GBW 55 khz CL=2pF Slew rate SR.35 V/μs CL=2pF ( ) reference value of design Notes Output terminal : The over-current protection feature is not built in the output terminal of this product. Therefore, please insert resistance to output port. Input offset voltage : the amplifier circuit of the first block of operational amplifier. A circuit suitable for operation near GND, and a circuit suitable for operation near +power supply. in case of input voltage of overlap point output port has a minute voltage shift or distortion. R3DS98EJ2 Rev.2. Page 3 of 7 Apr. 17, 217
Electrical Characteristics I DD /ch - Channel supply current - μa 1 8 6 4 2 V IN =1/2V DD I DD /ch vs. V DD 1 2 3 4 5 6 V DD - Supply voltage - V I DD /ch - Channel supply current - μa I DD /ch vs. T A 1 8 V DD =5.5V 6 4 2 V DD =1.8V -5 5 1 15 6 V IO vs. V DD 6 V IO vs. T A V IO - Input offset voltage - mv 4 2-2 -4 V IN =1/2V DD each 3 samples data V IO - Input offset voltage - mv 4 2-2 -4 V DD =5.5V V DD =1.8V -6 1 2 3 4 5 6 V DD - Supply voltage - V -6-5 5 1 15 I B vs. V IN I B vs. T A I B - Input bias current - pa 2 15 1 5-5 -1-15 I B - Input bias current - pa 4 35 3 25 2 15 1 5-2.5 1 1.5 2 2.5 3 3.5 V IN - Input voltage - V -5-5 5 1 15 R3DS98EJ2 Rev.2. Page 4 of 7 Apr. 17, 217
SR - Slew rate - V/μs SR vs. T A (Output rise time).6 V DD =5.5V.5.4.3.2 V DD =1.8V.1 C L =2pF -5 5 1 15 SR - Slew rate - V/μs SR vs. T A (Output fall time).6.5 V DD =5.5V.4.3.2 V DD =1.8V.1 C L =2pF -5 5 1 15 Pulse response Pulse response V IN + Input voltage - V VO - Output voltage - V (Voltage 1V/div) (time 1μs/div) t - Time - μs V O =3.1V C L =2pF V IN + Input voltage - mv V O - Output voltage - mv (Voltage 5mV/div) (time 1μs/div) t - Time - μs V O =1mV C L =2pF V O vs. I O SOURCE V O vs. I O SINK V O - Output voltage - V 3 2.5 2 1.5 1.5 V DD, V SS =±2.75V T A =85 C T A =-4 C T A =125 C V DD, V SS =±1.65V T A =85 C T A =-4 C V DD, V SS =±.9V V O - Output voltage - V -.5-1 -1.5-2 -2.5 V DD, V SS =±.9V T A =85 C T A =-4 C T A =125 C V DD, V SS =±1.65V T A =85 C T A =125 C T A =125 C 2 4 6 8 1 I O SOURCE - Output source current - ma -3 V DD, V SS =±2.75V T A =-4 C 2 4 6 8 1 I O SINK - Output sink current - ma R3DS98EJ2 Rev.2. Page 5 of 7 Apr. 17, 217
A V, φ vs. f A V - Voltage gain - db 1 8 6 4 2 C L =2pF 2 16 12 8 4 φ - Phase margin - deg. -2-4 1 1 1K 1K 1K 1M CMRR - Common mode rejection ratio - db 1 8 6 4 2 CMRR vs. f 1 1 1K 1K 1K 1M C L =2pF SVRR - Supply voltage rejection ratio - db SVRR vs. f 1 SVRR - () C L =2pF 8 6 4 SVRR + (V SS =-3.3V) 2 1 1 1K 1K 1K 1M Channel separation - db 14 12 1 8 6 4 2 Channel separation vs. f CH1 CH2 CH2 CH1 1 1 1K 1K 1K 1M C L =2pF V om - Output voltage swing - V P-P V om vs. f 3.5 3 2.5 2 Gain=4dB V IN =33mV P-P 1.5 Gain=2dB V IN =.33V P-P 1.5 Gain=dB V IN =3.3V P-P 1 1 1K 1K 1K 1M R3DS98EJ2 Rev.2. Page 6 of 7 Apr. 17, 217
Package Dimensions 8-PIN PLASTIC TSSOP JEITA Package code RENESAS code Previous code MASS(TYP.)[g] P-TSSOP8-225-.65 PTSP8JD-A P8GR-65-9LG - Unit:mm detail of lead end NOTE Each lead centerline is located within.1 mm of its true position at maximum material condition. ITEM D D1 E HE A A1 A2 MILLIMETERS 3.15 ±.15 3. ±.1 4.4 ±.1 6.4 ±.2 1.2 MAX..1 ±.5 1. ±.5 A3.25 +.6 b.24 -.5 c.145 ±.55 L.5 Lp.6 ±.15 L1 1. ±.2 +5 θ 3-3 e.65 x.1 y.1 ZD.6 R3DS98EJ2 Rev.2. Page 7 of 7 Apr. 17, 217
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