積體電路設計方法

積體電路設計方法 賴源泰 電機系 成功大學 1

積體電路時代 Transistors integrated on a single chip 10-100 in 1960 1K-20K in 1970 20K-500K in 1980 10M-20M in 1990 2

積體電路時代 Minimum line width in mass production 5μm in 1977 2μm in 1984 1μm in 1995 0.11μm in 2005 25nm in 2010 3

電路設計技術 Circuit Design Techniques PCB Circuits Circuit system = ICs + Transistors + (RLC)+ PCB Progress in Fabrication Technology SSI LSI VLSI SOC 4

設計自動化 Design Description High level computer languages Hardware Description Language Verilog HDL Design Tools Silicon Compiler (synthesizer) Analyzer 5

階層式設計法 Hierarchy (Divide and Conquer) Dividing a circuit into sub-circuits until they are tractable 6

有系統的設計策略 Structural Design Strategy Behavioral Design 功能設計 Structural Design 結構設計 Physical Design 實體設計 7

功能設計範例 Triangle Generator1/2 Schematic Diagram RST Vdd WAVE[3:0] D/A CLK Vss Pulse generator 8

功能設計範例 Triangle Generator2/2 Description Language main(){ triangle() } triangle () { int j=1 ; int I = wave = 0 ; while (1) { if (wave==15) j = -1 ; else if (wave == 0) j =1 ; wave = wave +j ; } 9

結構設計 How components are interconnected to perform a certain function Components: Registers Gates Functional Blocks And etc. 10

結構設計範例 Triangle Generator1/2 Schematic diagram 11

實体電路設計 How a part is constructed to yield a specific structure and hence behavior 12

實体電路設計 Gate Array 閘矩陣電路 Standard Cells 標準單元組成電路 Field Programmable Gate Array 現場規劃閘矩陣電路 System on a Chip 單晶片系統電路 13

閘矩陣電路 Gate array MPGA, musk programmable gate array Prefabricated primitive gates on a silicon substrate Gates are connected to implement desired functions Need no knowledge of detailed technology. Shorter development time and lower development costs 14

Silicon Substrate of Musk Programmable Gate Array 接線區域 Prefabricated gates 15

標準單元電路 Standard-cells 16

標準單元組成電路架構 Standard-cell Architecture 接線區域 標準組成單元 等高不同寬 17

標準單元組成電路架構 Standard-cell Architecture Multiple Metal Layers Pins 接線區域 : Channel, Over cell routing 標準組成單元 可不等高不同寬 Sea of gates 18

現場規劃閘矩陣電路 Field Programmable Gate Array Extension of Musk Programmable Gate Array Programmable Logic Device Implementation of Data Path Architecture Configurable Logic Block Switch Box 19

現場規劃閘矩陣電路架構 FPGA Architecture IOB IOB IOB IOB IOB CLB C CLB C CLB C CLB IOB IOB Switch matrix Switch matrix C C C Switch matrix C IOB CLB CLB CLB C C C CLB IOB Switch Switch C matrix C matrix C Switch matrix C IOB IOB CLB C CLB C CLB C CLB IOB IOB IOB IOB IOB 20

現場規劃閘矩陣電路映對 Technology Mapping for FPGA HDL Compiler Configuration Codes 21

單晶片系統設計 SOC Design Software/Hardware Codesign Structure Programmable Processor + Data path 22

Control Flow Computation v.s. Data flow Computation Compute a = (b+1)*(b-c) Program Memory + b 1 t1 - b c t2 * t1 t2 a Data Memory b t1 c t2 a b 1 Add Sub Multiplier a c 23

單晶片系統組織架構 Organization of SOC CPU Main Memory Data Path Hardware I/O 24

Coupling The Computing Unit to The Host CPU Main Memory Local bus PCI bus Data Path Computing Unit (Accelerator Board) I/O 25

Data Path Hardware Composed of IPs (Intellectual Properties) Bus Connector Data Compactor Signal Processor Barrel Shifter Decoder XXX Multiplier 26

設計流程 I - 軟體硬體分工 Hardware/Software Partitioning Description Language Hardware/Software Partitioning SoftwareTask HardwareTask 27

設計流程 II - 軟體編譯 Software Compilation Software Task (Program) Compiler Machine Codes 28

設計流程 III - 硬體設計製作 Hardware Implementation Data Path Diagram Mapping New Data Path Diagram Scheduling IP Placement Interface Synthesis Routing (Interconnection) Physical Circuit 29

Reconfigurable Computing CPU Main Memory Local bus PCI bus Reconfigurable Computing Unit I/O 30

Dynamic FPGA for Configurable Computing 31

Performance of configurable computer One or two orders faster than processor-based computer Faster than Supercomputer Much Cheaper than Supercomputer 32

Product Development Cost Development Manufacturing Maketing sales General administrative Maintance Finacial 33

Development Cost Chip/circuit/physical design Chip integration Verification, test Software development EDA integration & support Infrastructure cost 34

設計技術的挑戰 Design Technology Challenges Design Productivity Minimum Power Manufacturability Reliability Interference 35

設計的產能 Design Productivity Issues: Cost-driven design flow Reuse of modules, cores, RF, etc. Embedded software design Formal Verification Automated methods Heterogeneous component integration 36

低耗電 Low Power Design Portable System Low Voltage Low Power Power management 37

可製造的設計 Design for Manufacturability Performance/power variability Device parameter variability Lithography limitations impact on design Mixed signal Design for testability Mask cost System level reliability Thermal Built-in-self-test 38

Reliability Logic/Circuit/Layout: mean-time-tofailure aware design Built-in self repair Software reliability Robust design 39

介面設計 Design of interference Logic/circuit/layout: signal integrity analysis Eletromagnetic interference analysis Thermal analysis Interference of heterogeneous components (optical, mechanical, bio, etc.) 40

高速系統 High Performance System Video Image Processing Accelerators for Combinatorial Problems DNA Sequence Matching Cryptographic attacks Scientific Computation Simulation Engines 41

Conclusions Miniature High Circuit Density Complex System High design complexity Challenge design work 42