樹德科技大學資訊工程系 Chapter 8: Counters Shi-Huang Chen Fall 2010 1 Outline Asynchronous Counter Operation Synchronous Counter Operation Up/Down Synchronous Counters Design of Synchronous Counters Cascaded Counters Counter Decoding Counter Applications 2 1
Counting in Binary As you know, the binary count sequence follows a familiar pattern of 0 s and 1 s as described in Section 2-2 of the text. The next bit changes on every fourth number. 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 LSB changes on every number. The next bit changes on every other number. 3 Counting in Binary A counter can form the same pattern of 0 s and 1 s with logic levels. The first stage in the counter represents the least significant bit notice that these waveforms follow the same pattern as counting in binary. LSB 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 MSB 0 0 0 0 1 1 1 1 4 2
2-Bit Asynchronous Counter 5 3-Bit Asynchronous Counter 6 3
3-Bit Asynchronous Counter 7 Propagation Delay Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage. For certain applications requiring high clock rates, this is a major disadvantage. CLK 1 2 3 4 Q 0 Q 1 Q 2 Q 0 is delayed by 1 propagation delay, Q 2 by 2 delays and Q 3 by 3 delays. 8 4
4-Bit Asynchronous Counter 9 Asynchronous Decade Counter This counter uses partial decoding to recycle the count sequence to zero after the 1001 state. The flip-flops are trailingedge triggered, so clocks are derived from the Q outputs. Other truncated sequences can be obtained using a similar technique. 10 5
Asynchronous Modulus-12 Counter 11 4-Bit Asynchronous Binary Counter The 74LS93A 4-bit asynchronous binary counter logic diagram. All J and K inputs are connected internally HIGH 12 6
4-Bit Asynchronous Binary Counter Three configurations of the 74LS93A asynchronous counter. (c) 74LS93A connected as a modulus-12 counter. 13 2-Bit Synchronous Counter In a synchronous counter all flip-flops are clocked together with a common clock pulse. Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes. 14 7
3-Bit Synchronous Counter 15 3-Bit Synchronous Counter 16 8
4-Bit Synchronous Counter Q 1 Q 0 Q 2 Q 1 Q 0 FF0 FF1 G1 G 2 FF2 FF3 HIGH J 0 Q 0 J 1 Q 1 J 2 Q 2 J 3 Q 3 CLK C C C C K 0 Q 0 K 1 Q 1 K 2 Q 2 K 3 Q 3 The 4-bit binary counter has one more AND gate than the 3-bit counter just described. The shaded areas show where the AND gate outputs are HIGH causing the next FF to toggle. Q 0 Q 1 Q 2 Q 3 17 Synchronous BCD Decade Counter This gate detects 1001 LSB 18 9
Synchronous BCD Decade Counter 19 4-bit Synchronous Binary Counter 74HC163 20 10
Synchronous BCD Decade Counter 74LS160 21 Up/Down Synchronous Counters UP UP 0, 1, 2, 3, 4, 5, 4, 3, 2, 3,4, 5, 6, 7, 6, 5, etc. DOWN DOWN 22 11
Up/Down Synchronous Counters A basic 3-bit up/down synchronous counter 23 Up/Down Synchronous Counters The 74HC190 up/down synchronous decade counter 24 12
Design of Synchronous Counter General clocked sequential circuit or state machine Flip-flop 25 Step 1: State Diagram State diagram for a 3-bit Gray code counter 26 13
Step 2: Next State Table 27 Step 3 Flip-Flop Transition Table 28 14
Step 4: Karnaugh Maps 29 Step 5: Logic Expressions for Flip-Flop Inputs 30 15
Step 6: Counter Implementation Three-bit Gray code counter 31 Example (1) 32 16
Example (2) 33 Example (3) 34 17
Example (4) 35 Cascaded Counters 36 18
Cascaded Counters A modulus-100 counter using two cascaded decade counters. 37 Cascaded Counters Three cascaded decade counters forming a divide-by- 1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs. 38 19
Cascaded Counters A divide-by-100 counter using two 74LS160 decade counters. 39 Cascaded Counters with Truncated Sequences A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D 0 is the LSB in each counter). 40 20
Counter Decoding Decoding of state 6 (110) 41 Counter Applications Digital Clock 42 21
Counter Applications Digital Clock Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the rightmost bit is the LSB). 43 Counter Applications Digital Clock Logic diagram for hours counter and decoders. 44 22
Counter Applications Functional block diagram for parking garage control. 45 Counter Applications Logic diagram for modulus-100 up/down counter for automobile parking control. 46 23