www.maxim-ic.com.cn 应用笔记 3259 DS31256 Envoy - 寄存器转储列程 概述本应用笔记提供了将 DS31256 的寄存器 排队程序 描述符和 FIFO RAM 的内容转储到一个文件的程序代码 这些数据在 DS31256 无法正常工作时非常关键, 为进一步的研究和调试提供了重要信息 例如, 寄存器数据经过转储后可以显示每个 DS31256 寄存器的设置 为了保证正确地设置器件, 首先需要检查配置 出现任何问题时, 支持组都将提出这项请求 有时, 只需简单地检查一下配置寄存器即可解决问题 该应用笔记仅仅罗列了可能发生问题的公共区域, 寄存器内容的转储文件提供了有关寄存器配置 排队程序 描述符和 FIFO RAM 的信息 执行寄存器转储之前, 需要做出一些假设 软件中需要以下功能函数 1. write_reg (addr, data) -- 将特定数据写入指定的 DS31256 寄存器 addr = DS31256 寄存器与芯片基础地址的偏差 data = 需要写入寄存器的数据 2. read_reg (addr) -- 在指定地址读取 DS31256 寄存器并返回数据 addr = DS31256 寄存器与芯片基础地址的偏差 3. read_ind_reg (addr, i) -- 在指定地址读取 DS31256 间接寄存器并返回数据 addr = DS31256 寄存器与芯片基础地址的偏差 i = 索引 4. 标准 C 函数 :printf fopen fprintf 和 fclose 5. 一些数据结构被用来在排队程序和描述符中保持数据 1. 将 DS31256 寄存器的数据转储到一个指定文件的程序代码 void dumpregs (char *filename) int addr, i, port; FILE *fptr; /* Open specified file for register dump */ fptr = fopen (filename, "w"); 1 of 9
if (fptr == NULL) printf ("Can't open the file\n"); /* Dump the contents of registers by category to the specified file */ fprintf (fptr, " Dump of DS31256 Registers\n"); fprintf (fptr, " General Config Registers\n"); fprintf (fptr, "MRID:\t %.4x\n", read_reg(0x0)); fprintf (fptr, "MC: \t %.4x\n", read_reg(0x10); fprintf (fptr, "SM: \t %.4x\n", read_reg(0x20); fprintf (fptr, "ISM: \t %.4x\n", read_reg(0x24); fprintf (fptr, "SDMA: \t %.4x\n", read_reg(0x28); fprintf (fptr, "ISDMA: \t %.4x\n ", read_reg(0x2c); fprintf (fptr,"\tsv54:\t %.4x\n", read_reg(0, 0x30); fprintf (fptr,"isv54: \t %.4x\n", read_reg(0x34) ; fprintf (fptr,"lbbmc: \t %.4x\n ", read_reg(0x40); fprintf (fptr,"test: \t %.4x\n", read_reg(0x50); fprintf (fptr,"receive Port Registers \n"); for (i = 0, addr = 0x100; addr <= 0x13c; addr += 4, i++) fprintf (fptr,"rp %d CR: \t %.4x\n", i, read_reg(addr)); if ((i & 3) == 3) fprintf (fptr, "Transmit Port Registers \n"); for (i = 0, addr = 0x200; addr <= 0x23c; addr += 4, i++) fprintf (fptr,"tp%d CR:\t %.4x", i, read_reg( addr)); if ((i & 3) == 3) for (port = 0, addr = 0x300; port < 16; port++, addr += 8) fprintf (fptr, "Channelized Port Registers, Port %d \n", port); for (i = 0; i < 128; i++) fprintf (fptr,"c%d DAT%d : \t %.4x", port, i, read_ind_reg(addr, i)); fprintf (fptr, "R%dCFG%d : \t %.4x", port, i,read_ind_reg(addr, i 0x100)); fprintf (fptr, "T%dCFG%d: \t %.4x", port, i, read_ind_reg(addr, i 0x200)); printf (fptr, "\n"); 2 of 9
fprintf (fptr, "HDLC Registers \n"); fprintf (fptr, "RHPL: \t %.4x\n", read_reg(0x410)); for (i = 0; i < 256; i++) fprintf (fptr,"rhcd%d : \t %.4x", i, read_ind_reg (0x400, i)); fprintf (fptr,"thcd%d : \t %.4x", i, read_ind_reg (0x480, i)); fprintf (fptr, "BERT Registers\n"); fprintf (fptr, "BERTC0 : \t %.4x", read_reg(0x500)); fprintf (fptr, "BERTC1 : \t %.4x", read_reg(0x504)); fprintf (fptr, "BERTRP0 : \t %.4x", read_reg(0x508)); fprintf (fptr, "BERTRP1 : \t %.4x \n", read_reg(0x50c)); fprintf (fptr,"bertbc0 : \t %.4x \n", read_reg(0x510)); fprintf (fptr,"bertbc1 : \t %.4x \n", read_reg(0x514)); fprintf (fptr,"bertec0 : \t %.4x \n", read_reg(0x518)); fprintf (fptr,"bertec1 : \t %.4x \n", read_reg(0x51c)); fprintf (fptr,"receive DMA Registers \n"); fprintf (fptr,"rfqba0 : \t %.4x", read_reg(0x700)); fprintf (fptr,"rfqba1 : \t %.4x", read_reg(0x704)); fprintf (fptr,"rfqea : \t %.4x", read_reg(0x708)); fprintf (fptr,"rfqsbsa : \t %.4x \n", read_reg(0x70c)); fprintf (fptr,"rfqlbwp : \t %.4x", read_reg(0x710)); fprintf (fptr,"rfqsbwp : \t %.4x", read_reg(0x714)); fprintf (fptr,"rfqlbrp : \t %.4x", read_reg(0x718)); fprintf (fptr,"rfqsbrp : \t %.4x", read_reg(0x71c)); fprintf (fptr,"rdqba0 : \t %.4x", read_reg(0x730)); fprintf (fptr,"rdqba1 : \t %.4x", read_reg(0x734)); fprintf (fptr,"rdqea : \t %.4x", read_reg(0x738)); fprintf (fptr,"rdqrp : \t %.4x \n", read_reg(0x73c)); fprintf (fptr,"rdqwp : \t %.4x", read_reg(0x740)); fprintf (fptr,"rdqfft : \t %.4x", read_reg(0x744)); fprintf (fptr,"rdba0 : \t %.4x", read_reg(0x750)); fprintf (fptr,"rdba1 : \t %.4x \n", read_reg(0x754)); fprintf (fptr,"rdmaq : \t %.4x", read_reg(0x780)); fprintf (fptr,"rlbs : \t" %.4x", read_reg(0x790); fprintf (fptr,"rsbs : \t" %.4x \n", read_reg(0x794)); fprintf (fptr,"receive DMA Channel Configuration \n"); for (i = 0; i < 256; i++) fprintf (fptr,"channel %d : \t ", i); fprintf (fptr, "%.4x", read_ind_reg (0x770, 0x100 + i)); 3 of 9
fprintf (fptr, "%.4x \t", read_ind_reg (0x770, 0x000 + i)); fprintf (fptr, "%.4x", read_ind_reg (0x770, 0x300 + i)); fprintf (fptr, "%.4x \t", read_ind_reg (0x770, 0x200 + i)); fprintf (fptr, "%.4x", read_ind_reg (0x770, 0x500 + i)); fprintf (fptr, "%.4x \n", read_ind_reg ( 0x770, 0x400 + i)); fprintf (fptr, "Transmit DMA Registers \n"); fprintf (fptr, "TPQBA0 : \t %.4x", read_reg(0x800)); fprintf (fptr, "TPQBA1 : \t %.4x", read_reg(0x804)); fprintf (fptr, "TPQEA : \t %.4x", read_reg(0x808)); fprintf (fptr, "TPQWP : \t %.4x", read_reg(0x80c)); fprintf (fptr, "TPQRP : \t %.4x \n", read_reg(0x810)); fprintf (fptr, "TDQBA0 : \t %.4x", read_reg(0x830)); fprintf (fptr, "TDQBA1 : \t %.4x", read_reg(0x834)); fprintf (fptr, "TDQEA : \t %.4x", read_reg(0x838)); fprintf (fptr, "TDQWP : \t %.4x", read_reg(0x83c)); fprintf (fptr, "TDQRP : \t %.4x \n", read_reg(0x840)); fprintf (fptr,"tdqfft : \t %.4x", read_reg(0x844)); fprintf (fptr,"tdba0 : \t %.4x", read_reg(0x850)); fprintf (fptr, "TDBA1 : \t %.4x", read_reg(0x854)); fprintf (fptr, "TDMAQ : \t %.4x \n", read_reg(0x880)); fprintf (fptr, "Transmit DMA Channel Configuration \n"); for (i = 0; i < 256; i++) fprintf (fptr, "Channel %d : \t", i); fprintf (fptr, "%.4x", read_ind_reg(0x870, 0x100 + i)); fprintf (fptr, "%.4x \t", read_ind_reg(0x870, 0x000 + i)); fprintf (fptr, "%.4x", read_ind_reg(0x870, 0x300 + i)); fprintf (fptr, "%.4x \t", read_ind_reg(0x870, 0x200 + i)); fprintf (fptr, "%.4x", read_ind_reg(0x870, 0x500 + i)); fprintf (fptr, "%.4x \n", read_ind_reg(0x870, 0x400 + i)); fprintf (fptr, "%.4x", read_ind_reg(0x870, 0x700 + i)); fprintf (fptr, "%.4x \t", read_ind_reg(0x870, 0x600 + i)); fprintf (fptr, "%.4x", read_ind_reg(0x870, 0x900 + i)); fprintf (fptr, "%.4x \t", read_ind_reg(0x870, 0x800 + i)); fprintf (fptr, "%.4x", read_ind_reg(0x870, 0xb00 + i)); fprintf (fptr, "%.4x \n", read_ind_reg(0x870, 0xa00 + i)); 4 of 9
5 of 9 应用笔记 3259: 寄存器转储例程 (DS31256) 2. 将发送排队程序和描述符转储到一个指定文件的程序代码 有些结构用来存储尚未确定或已经执行的排队数据和描述符, 这些数据有助于检查已经生成和正确发送的数据 void dumptx(drvdev * dp, int32 filename, int32 channel, int32 desc2) FILE fptr; dmatxdoneqdesc doneq; /* structure of Transmit Done Queue */ dmatxdev tdma; /* structure of DMA TX subsystem of the device */ dmatxbufdesc tbd; /* structure of Transmit Buffer Descriptor */ dmapendqdesc * pendq; /* structure of Transmit Pending Queue*/ int i, a = 0; int32 dev = 0; int32 tdqrp, tdqwp; int32 tpqrp, tpqwp; tdma = &dp->txdma; /* Get the pointer from the device structure */ doneq = tdma->doneqstart; /* Transmit Done Queue Start Pointer */ pendq = tdma->pendqstart; /* Transmit Pending Queue Start Pointer */ /* Open the specified file for data dump */ fptr = fopen(filename, "w"); if (fptr == NULL) printf ("Can't open the file\n"); fprintf (fptr, "\ntx Buffer Descriptors : \n"); for(i=0; i<tdma->bufdesccnt; i++) tbd = &tdma->bufdesc[i]; fprintf (fptr,"%4x : %.8x %.8x %.8x %.8x\n", i, tbd->dataaddr, tbd->desc1, tbd->desc2, tbd->desc3); /* Check the transmit pending queue write and read pointer before print out the data */ tpqwp = read_reg (0x80c); tpqrp = read_reg (0x810); fprintf (fptr, "\ntransmit Pending Queues : \n"); fprintf (fptr, "Read Pointer: %.8x Write Pointer : %.8x\n",tpqrp,tpqwp); pendq = tdma->pendqstart; for(i = pendq; i <= tdma->pendqend; pendq++) fprintf (fptr, "%4x : %.8x\n", a, pendq->desc);
a++; if (pendq == tdma->pendqend) break; /* Check the transmit done queue write and read pointer before print out the data */ tdqwp = read_reg(0x840); tdqrp = read_reg(0x83c); fprintf (fptr, "\ntransmit Done Queue Descriptors : \n"); fprintf (fptr, "Read Pointer: %.8x Write Pointer : %.8x\n",tdqrp,tdqwp); a=0; doneq = tdma->doneqstart; for (i = doneq; i <= tdma->doneqend; doneq++) fprintf (fptr,"%4x : %.8x\n", a, doneq->desc); a++; if (doneq == tdma->doneqend) break; /* Close the file */ 3. 将接收 FIFO RAM 的内容转储到一个指定文件的程序代码 void dump_rx_fifo_rams(char *filename) unsigned long reg_val; unsigned long rftst1, rftst2, rftst3, rftst4, rftst5, rftst6; unsigned long ram_addr; unsigned long max_busy_cnt, busy_cnt; FILE *fptr; /* DS31256 RX FIFO test register addresses */ rftst1 = 0x09D0; rftst2 = 0x09D4; rftst3 = 0x09D8; rftst4 = 0x09DC; rftst5 = 0x09E0; rftst6 = 0x09E4; 6 of 9
max_busy_cnt = 10; printf ("Dumping RX FIFO RAM's to file %s\n\n", filename); /* Open specified file for RAM data dumping */ fptr = fopen(filename, "w"); /* Put chip in test mode */ write_reg(0x0050, 0x0001); /* Dump RX FIFO SBP RAM */ /* Will be covered by write configuration and read configuration RAM dumps below */ /* Dump RX FIFO BP RAM to file */ fprintf (fptr, "RX FIFO BP RAM\n"); for (ram_addr=0; ram_addr<1024; ram_addr++) write_reg(rftst1, (0x0400 + ram_addr) 0x4000); printf ("\n\nerror: Max busy cnt of %d on rftst1 - RX FIFO BP RAM\n", max_busy_cnt); fprintf (fptr, "%.3x\n", read_reg(rftst2) & 0x03ff); /* Dump RX FIFO HWM RAM to file */ fprintf (fptr, "RX FIFO HWM RAM\n"); for (ram_addr=0; ram_addr<256; ram_addr++) write_reg(rftst1, (0x0800 + ram_addr) 0x4000); printf ("\n\nerror: Max busy cnt of %d on rftst1 - RX FIFO HWM RAM\n", max_busy_cnt); fprintf (fptr, "%.3x\n", read_reg(rftst2) & 0x03ff); 7 of 9
/* Dump RX FIFO write configuration RAM to file */ fprintf (fptr, "RX FIFO Write Configuration RAM\n"); for (ram_addr=0; ram_addr<256; ram_addr++) write_reg(rftst1, (0x0c00 + ram_addr) 0x4000); printf ("\n\nerror: Max busy cnt of %d on rftst1 - RX FIFO WCFG RAM\n", max_busy_cnt); fprintf (fptr, "%.4x%.4x%.4x\n", read_reg(rftst4) & 0x3fff, read_reg(rftst3) & 0xffff, read_reg(rftst2) & 0xffff); /* Dump RX FIFO read configuration RAM to file */ fprintf (fptr, "RX FIFO Read Configuration RAM\n"); for (ram_addr=0; ram_addr<256; ram_addr++) write_reg(rftst1, (0x1000 + ram_addr) 0x4000); printf ("\n\nerror: Max busy cnt of %d on rftst1 - RX FIFO RCFG RAM\n", max_busy_cnt); fprintf (fptr, "%.1x%.4x%.4x\n", read_reg(rftst4) & 0x000f, read_reg(rftst3) & 0xffff, read_reg(rftst2) & 0xffff); /* Dump RX FIFO data RAM to file */ fprintf (fptr, "RX FIFO Data RAM\n"); for (ram_addr=0; ram_addr<2048; ram_addr++) 8 of 9
write_reg(rftst1, (0x2000 + ram_addr) 0x4000); printf ("\n\nerror: Max busy cnt of %d on rftst1 - RX FIFO DATA RAM\n", max_busy_cnt); fprintf (fptr, "%.3x%.4x%.4x%.4x%.4x\n", read_reg(rftst6) & 0x0fff, read_reg(rftst5) & 0xffff, read_reg(rftst4) & 0xffff, read_reg(rftst3) & 0xffff, read_reg(rftst2) & 0xffff ); /* Close output file */ /* take chip out of test mode */ write_reg(0x0050, 0x0000); 结论本应用笔记提供了将 DS31256 的寄存器 排队程序 描述符和 FIFO RAM 的内容转储到一个文件的软件 如需进一步了解有关 HDLC 控制器产品的信息, 请联络电信应用支持组 :Email 地址 : telecom.support@dalsemi.com (English only), 电话 :972-371-6555 (Dallas, TX, USA) 9 of 9