SSSC /4168P 2005 8
4 4, (ADC), LCD Driver, (Buzzer), 1
3 CPU17 CPU 26 33 42 45 48 73 79 85 89 A/D 92 111 125 128 131 SSU4168P 133 143 A: / 153 B: 156 C: 158 D: 160 E: 161 F: 163 G: PAD 167 2
,, 11 4 CMOS 512 4 RAM, 20 I/O,,, RC A/D 34 LCD 4 CPU,,, 12 (1), 148 /, (2) : HL XY (3) : 32768KHz ( 91 s) : 700KHz RC (4) : 8160 (5) : 512 4 (512 nibble, 512 N) (6) I/O 3 4 ( NMOS CMOS, / ) 1 4 ( ) 1 4 ( NMOS CMOS ) (7) ( ) (8) 8 (MSB) (LSB) 3
(9) (34 ) 1/4 duty, 1/3 bias: 120 30 4 1/3 duty, 1/3 bias: 93 31 3 1/2 duty, 1/2 bias: 64 32 2 34 8 (Mask Option) (10) RC A/D A : 1/(10 4 8) 1 B : 1/2 14 1 (11) (Capture Circuit): 256Hz, 128 Hz, 64 Hz 32 Hz (12) (13) : 2, 5,, 1 A/D (14) 15V/3V (15) (16) 80 4
13 1-1 1-1 5
14 1-2, 1-3, 1-4, 1-5 1-2 (GP) 6
1-3 (GA) 7
1-4 (TB) 8
-xxx 1-5 9
15 151 1-1, 1-2 1-1(A) GP GA, TB PADI/O V SS 32 30 30 0V V DD 67 65 65 V DD1 42 40 40 LCD Bias (12V/15V) V DD2 44 42 42 LCD Bias (24 V/30V) V DD3 45 43 43 LCD Bias (36 V/45V) V DDI 42 41 41 C1 46 44 44 C2 47 45 45 LCD Bias V DDL 31 29 29 ( ) XT 69 67 67 Input, XT 68 66 66 Output OSC1 66 64 64 Input OSC2 65 63 63 Output TST1 71 69 69 Input TST2 72 70 70 Input 32768KHz, 32768KHz, R OS, V DD RESET 70 68 68 Input :,, 000H V DD 10
1-1(B) GP GA, TB PADI/O P00 77 75 75 P01 78 76 76 P02 79 77 77 P03 80 78 78 P10 73 71 71 P11 74 72 72 P12 75 73 73 P13 76 74 74 P20 18 16 16 P21 19 17 17 P22 20 18 18 P23 21 19 19 P30 22 20 20 P31 23 21 21 P32 24 22 22 P33 25 23 23 P40 26 24 24 P41 27 25 25 P42 28 26 26 P43 29 27 27 Input Output Input/ Output Input/ Output Input/ Output 4 P0 : :, 4 (P1): NMOS CMOS ( P01CON) ; P10 4 P2 : : 4 P3 : : 4 P4 : : 11
1-1(C) GP GA, TB PADI/O BD 30 28 28 Output RT0 33 31 31 Output 0 CRT0 34 32 32 Output 0 / RS0 35 33 33 Output 0 A/D CS0 36 34 34 Output 0 IN0 37 35 35 Input 0 RC (ADC) RT1 41 39 39 Output 1 RS1 40 38 38 Output 1 CS1 39 37 37 Output 1 IN1 38 36 36 1 RC 12
1-1(C) GP GA, TB PADI/O L0 1 79 79 L1 2 80 80 L2 3 1 1 L3 4 2 2 L4 5 3 3 L5 6 4 4 L6 7 5 5 L7 8 6 6 L8 9 7 7 L9 10 8 8 L10 11 9 9 L11 12 10 10 L12 13 11 11 L13 14 12 12 L14 15 13 13 L15 16 14 14 LCD L16 17 15 15 L17 48 46 46 L18 49 47 47 L19 50 48 48 L20 51 49 49 L21 52 50 50 L22 53 51 51 L23 54 52 52 L24 55 53 53 L25 56 54 54 L26/P50 57 55 55 L27/P51 58 56 56 L28/P52 59 57 57 L29/P53 60 58 58 L30/P60 61 59 59 L31/P61 62 60 60 L32/P62 63 61 61 L33/P63 64 62 62 Output LCD / Output LCD / ; 13
1-2 GP GA, TB PADI/O P00 77 75 75 P01 78 76 76 P02 79 77 77 P03 80 78 78 P20 18 16 16 P21 19 17 17 P22 20 18 18 P23 21 19 19 P30 22 20 20 P31 23 21 21 P32 24 22 22 P33 25 23 23 P40 26 24 24 P41 27 25 25 P42 28 26 26 P43 29 27 27 P00 77 75 75 P01 78 76 76 Input Input :, : P33 25 23 23 Input SIN P40 26 24 24 Output SOUT P41 27 25 25 Output P42 28 26 26 Input SCLK Output RC P43 29 27 27 Input ADC RC 14
152 1-3 Pin OSC1 OSC2 TST1, TST2 P00 P03 P10 P13 P20 P23 P30 P33 P40 P43 BD RT0 CRT0 RS0 CS0 IN0 RT1 RS1 CS1 IN1 L0 L33 / : / : : / : : / : 15
16 (CLK) : 32768KHz 700KHz RC CLK XT OSC1 1 (Machine Cycle), 5 S1 M1 S1 1-6 16
CPU 21 148, 8 4 32 512 4 RAM (SFR), RAM BANK 7 BANK 6, SFR BANK 0 780H 7FFH, 128 4 2-1 : (1), (BANKS) (BSR0 BSR1) (BCF BEF) (2) 1FE0H 1FFFH 32, 17
22 2-2 2-2 18
221 A, B, H, L, X Y A ( ) B, H, L, X Y 5 B A H L X Y, 2-3 2-3, M, d, (HL) (XY), b, BA HL 19
222 (PC) 13, (8K ) 223 (SP) (SP), BANK 0 7EH 7FH,, 1, SP SP, SP SP 0FFH, SP BANK 7 0FFH 0FEH SP 6 2-4 224 (C),, C 1, C 20
23 231,, CZP, 8 8192 8 2-5, 0H 10H 1FH CZP (CZP area), CZP, 8 020H 03DH 1FE0H 1FFFH 32, 21
232 2321 (SFR) BANK 0 000H 07FH 128 N SFR, BANK 6 BANK 7( 512 N), 4 2-6 2-6, 7FFH, 128 N, 11 3 (BANK), 8 HL, XY : SFR : (BCF) 1, BANK 0, (Bank Selection) 22
2322 (Bank Selection) BSR0 BSR1, BCF BEF PUSH BSR POP BSR, HL, XY, 2-1 BCF BEF BSR0 BSR1 2-2 BSR0 BSR1 2-1 BCF, BEF, BCF BEF HL XY 0 0 BSR0 BSR0 BSR0 0 1 BSR0 BSR1 BSR1 0H 7FH, 1 0 BSR0 BSR0 1 1 BSR0 BSR1 BANK 0 ; 80H 0FFH, BSR0 0H 7FH, BANK 0 ; 80H 0FFH, BSR1 BANK 7 2-2 BSR0 BSR1 BRSR0, BSR1 BRSR0, BSR1 0 BANK 0 4 BANK4 1 BANK1 5 BANK5 2 BANK2 6 BANK6 3 BANK3 7 BANK7 : BANK1 BANK5 23
2323 (1) HL 2 7 HL (2) XY 2-8 XY 24
(3) 2-9 (4) (PUSH, POP,, ) 2-10 25
CPU 31 : (Normal operation mode) (System reset mode) (Halt mode) 3-1 3-1 CPU, CPU : CPU PC HLT 1 26
32 321, RESET : (1) CPU (2) (3) V DDL V DD ; 05, V DDL (VR) (4) LCD ( V SS ), 63ms, LCD (5), 000H 3-2 3-3 3-2 27
3-3 28
322 3-2 3-2(a) / (PC) 000H A (A) B (B) 0H 0H (C) 0 HL (HL) XY (XY) (SP) 0(BSR0) 1(BSR1) 00H 00H 0FFH 0H 0H (BCF) 0 (BEF) 0 1 (P1) 2 (P2) 3 (P3) 4 (P4) P20 (P20CON) P21 (P21CON) P22 (P22CON) P23 (P23CON) P30 (P30CON) P31 (P31CON) P32 (P32CON) P33 (P33CON) P40 (P40CON) P41 (P41CON) P42 (P42CON) P43 (P43CON) 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H, /, 64Hz,, /, P01 (P01CON) 8H P1 CMOS, P0, P2, P3, P4 29
3-2(b) / (SCON) 0H,, (SBUFL) 0H (SUBFH) 0H (FCON) 0EH (BDCON) 0H,, 1 (BFCON) 0H (CAPCON) 0H 0,1 0(CAPR0) (CAPR1) (DSPCON) 0CH 1/4 (duty) 0H 0H 0 30(DSPR0~30) 0H ADC 0(ADCON0) 0CH A, RC ADC 1(ACCON1) 0H IN0 A/D A 0(CNTA0) A/D A 1(CNTA1) A/D A 2(CNTA2) A/D A 3(CNTA3) A/D A 4(CNTA4) A/D B 0(CNTB0) A/D B 1(CNTB1) A/D B 2(CNTB2) 0H 0H 0H 0H 8H 0H 0H 0H A/D B 3(CNTB3) 0CH (WDTCON) (BUPCON) 8H 13V 0(IRQ0) 1(IRQ1) 2(IRQ2) 0H 0H 0CH 0(IE0) 0H 1(IE1) 0H 2(IE2) 0EH (HALT) 0EH (MIEF) 0EH :, RAM 30
33 331 (HALT) (HALT) HALT (7DH) (R/W) b3 b2 b1 b0 * * * HLT 0: ( ) 1: *, 1, 0 : HLT 1 CPU 332 HLT 1, CPU,,,,, CPU,, CPU S1 CPU (HLT ), 10 ( ), CPU 3-4 (MI) MI 1, CPU, 3-4 ; MI 0, CPU, 3-5 :, 1 MI 0, 1 31
3-4 ( MI = 1) 3-4 ( MI = 0) 32
41 10 (10 ), 2, 8 10,, 9 (IE0, IE1, IE2), CPU 4-1, 4-1 4-1 1 WDTINT 03BH 2 0 (P2, P3, P4) XI0INT 038H 3 SIOINT 035H 4 1 (P0) XI1INT 032H 5 A/D ADINT 02FH 6 256Hz 256HzINT 02CH 7 32Hz 32HzINT 029H 8 16Hz 16HzINT 026H 9 1Hz 1HzINT 023H 10 01Hz 01HzINT 020H, (WDTINT) :, ( ): 1), 2) (vertical stack instruction) LAI LLI 3) ADCS SUBCS,, 33
4-1 34
42, MI 1,, 5, : (1) MI 0 (2) PC, A, B, H L C (3) 4 (SP SP-4) (4) PC, 4-2 4-2 RTI, 5 : (1) PC, A, B, H L C (2) 4 (SP SP+4) (3) MI 1 35
43 431 4, S1 1 1, IRQ0, IRQ1, IRQ2, IRQ0, IRQ1, IRQ2 0 3: QAD A/D QAD 1 2: QXI1 P00 P03 QXI1 1 1: QSIO 8 QSIO 1 0: QXI0 P20 P23, P30 P33, P40 P43 QXI0 1 36
3: Q1Hz 1Hz Q1Hz 1 2: Q16Hz 16Hz Q16Hz 1 1: Q32Hz 32Hz Q32Hz 1 0: Q256Hz 256Hz Q256Hz 1 37
1: QWDT QWDT 1 0: Q01Hz 01 Hz Q01Hz 1 38
432 (IE0, IE1, IE2) 4, CPU,, IE0, IE1, IE2 MI 0, IE0, IE1 IE2 39
40
433 (MIEF) (MIEF) MI 1, 0, MI 0 ; RTI MI 1 MI 1, 4-2 4-2 / 0 IE0 30H 1 IE1 31H 0H 2 IE2 32H 0H 0EH 0 IRQ0 33H 0CH 1 IRQ1 34H 2 IRQ2 35H 0H MIEF 7CH 0EH 0H 41
(2CLK) 51 (2CLK) (32768KHz, ), RC (700KHz, ), 32768KHz CPU, 32768KHz (32768KHz) RC (700KHz) (FCON) : RC (ROS), (VDD) 700KHz 52 5-1 42
53 32768Khz, (32768KHz) RC (700KHz) RC, RC (700KHz) CPU (FCON) FCON 0(CPUCLK) 0, (32768 KHz) ; CPUCLK 1, RC ((700KHz),, (32768KHz), RC 0, CPUCLK 1 RC, RC, OSC1/OSC2, RC, OSC1 V DD 54 (FCON) 0: CPUCLK, 0, 43
55 CPUCLK 0 1, 32768KHz 700KHz, VDDL VDD 5-2 5-2 5-1 5-2 RC 5-1 PAD / GP GA,TB XT 69 67 67, 32768KHz XT 68 66 66, 32768KHz OSC1 66 64 64 RC OSC2 65 63 63 5-2 RC (Ta = 25 ) V DD (V) R OS (K ) F OSC (KHz) 30 60 700 15 160 280 44
(TBC) 61 (TBC) 15 1/10 TBC 32768KHz TBC,,,, 62 6-1 6-1 45
63, (32768KHz), TBC 0000H TBC 256Hz/32 Hz/16 Hz/1 Hz/01 Hz, 16Hz 1 Hz /8 Hz /16 Hz 1 Hz /8 Hz 64 Hz 256 Hz /128 Hz /64 Hz /32 Hz TBCR TBC 1 Hz /2 Hz /4 Hz /8 Hz, TBCR, 01 Hz /1 Hz /2 Hz /4 Hz /8 Hz 0 6-2 TBCR : TBCR, LMAD TBCR, A TBCR 1 Hz /2 Hz /4 Hz /8 Hz, 1,,, 1Hz 1, 1Hz, MI (E1Hz) TBCR (Q1Hz) 64 (TBCR) 4 TBCR 1 Hz /2 Hz /4 Hz /8 Hz, TBCR 1 Hz /2 Hz /4 Hz /8 Hz 46
6-2 TBCR 47
(P0, P1, P2, P3 P4) 71 4, 4 / 4 72 P0 P1 (P00 P03 P10 P13) 721 P0 P1 P0 P01 (P01CON), ( ) P00 P01, P1 P01CON P1 CMOS NMOS 7-1 P0 P1 48
P0 P1 V DDI V SS P0 P1, V DDI V SS 7-2 P0 P4, V DDI V DD 7-2 P0 P1 49
722 P0 P1 (1) P0 (P0) 4, P0 (2) P1 (P1) P1 P1, P1 0 P1, : S3, P1 7-3 LMAD m8 7-3 50
, S2 (A) BA 7-4 LAMD m8 7-4 (3) P01 (P01CON) P01CON P0, P1 P2, P3 P4 P01CON, / 2: PUD P0MOD 0, P0, PUD 0 P0, 51
PUD 1 P0 PUD P2, P3 P4 PUD 0 : P2, P3 P4 (P20CON P23CON, P30CON P33CON P40CON P44CON) P0 P2, P3 P4 1: P1MOD P1MOD P1, P1MOD = 0, P1 CMOS, P1MOD = 1, P1 NMOS P1MOD 0 P10 P13 0: P0MOD P0MOD P0, P0MOD = 0, P0 / ( PUD ), P0MOD = 1, P0 P0MOD 0 P00 P03 723 P0 P0 64Hz P0n (n = 0,1,2,3) XI1INT 1 QXI1 15625ms (64Hz) P0 ( 7-5),, P0 P00 P03 1 PUD = 1, P00 P03 P00 P03, 1; PUD = 0, P00 P03 P00 P03, 1 7-5 1 52
7-6 1 (PUD = 1) 7-7 1 (PUD = 0) 53
73 P2, P3 P4 (P20 P23, P30 P33, P40 P44) 731 P2, P3 P4 P2, P3 P4 4 / /,, CMOS NMOS P01CON PUD P2, P3 P4 P33, P40 P42 P43 RC, 7-8 P2,P3 P4 54
P2, P3 P4 V DDI V SS P2, P3 P4, V DDI V SS 7-9 P0 P4, V DDI V DD 7-9 P2,P3 P4 55
732 P2, P3 P4 (1) P2 (P2) P2 P2, P2 P2 P2, P2 P2, P2 (2) P3 (P3) P3 P3, P3 P3 P3, P3 P3, P3 (3) P4 (P4) P4 P4, P4 P4 P4, P4 P4, P4 P2, P3 P4, P2, P3 P4 P2, P3 P4, P2, P3 P4 0 P2, P3 P4, S3, 7-10 LMAD m8 56
7-10, S2, A BA 7-11 7-11 (4) P2 (P20CON P23CON) P20CON P23CON 4, / P3 (P30CON P33CON) P4 (P40CON P43CON ) 4, / 57
58
59
60
61
(5) P3 (P30CON P33CON) 62
63
64
65
(6) P4 (P40CON P43CON) 66
67
68
3: P2nIE, P3nIE P4nIE (n = 0 ~ 3) /, IE 0,, 1,, 0 0 2: a) P20F P23F P30F P32F, 0 64Hz, 1 (32768KHz 700KHz) 0 P33 P40 P43 64Hz b) SIN (P33CON) SIN 1, P33, SIN 0, P33 SIN 0 c) SOUT (P40CON) SOUT 1, P40, SOUT 0, P40 SOUT 0 69
d) SPR (P41CON) SPR 1, P41 ; SPR 0, P41 SPR 0 e) SCLK (P42CON) SCLK 1 (SCON) EXSC 0, P42,, EXSC 1, P42 ; SCLK 0, P42 SCLK 0 f) MON (P43CON) MON 1, P43 A/D RC ; MON 0, P43 MON 0 1: P2nDIR, P3nDIR P4nDIR (n = 0~3) DIR, DIR 1,,, 0, 0: P2nMOD, P3nMOD P4nMOD (n = 0~3), MOD ( P01CON PUD ) ;, MOD CMOS NMOS 7-2 7-2 DIR, MOD PUD DIR MOD PUD 0 0 0 0 0 1 0 1 1 0 CMOS 1 1 NMOS 70
733 P2, P3 P4 P2, P3 P4, 0 (XI0INT) P2, P3 P4 XI0INT 0 QXI0 ( 7-12),, 0 038H 7-12 0 ( ) 71
7-13 0 7-3 / P2 P2 00H R/W 0H P3 P3 01H R/W 0H P4 P4 02H R/W 0H P0 P0 03H R P1 P1 04H R/W 0H P20 P20CON 10H W 0H P21 P21CON 11H W 0H P22 P22CON 12H W 0H P23 P23CON 13H W 0H P30 P30CON 14H W 0H P31 P31CON 15H W 0H P32 P32CON 16H W 0H P33 P33CON 17H W 0H P40 P40CON 18H W 0H P41 P41CON 19H W 0H P42 P42CON 1AH W 0H P43 P43CON 1BH W 0H P01 P01CON 1CH W 8H IE0 30H R/W 0H IRQ0 34H R/W 0H 72
81 8, P33 P40 P42 82 8-1, P33, P40, P41, P42 8-1 73
83 (SBUFH SBUFL), (SCON) ENTR 1,, SCON SEND 1, (SIOINT), SBUFH SBUFL SBUFH SBUFL SCON SDIR 1, (LSB), SDIR 0, (MSB) SCON EXSC EXSC 0, P42/SCLK ; EXSC 1, P42/SCLK 8-2 8-2 74
8-2, ENTR 1,, P41/SPR, P41/SPR, P42/SCLK ;,, P41/SPR P42/SCLK 8-2, ENTR 1 : SBUFH SBUFL 8 SR; P41/SPR ; P42/SCLK, SR P40/SOUT, P42/SCLK, P33/SIN SR; 8, P41/SPR ; SR SBUFH SBUFL; ENTR, SEND 1, SIOINT, P40/SOUT P33/SIN, P40/SOUT NMOS ( P40CON P40MOD 1 ), P33/SIN ( P01CON PUD 0 ) PUD, P33/SIN V DDI 75
84 (1) (SCON) 3: SDIR (MSB) (LSB), SDIR 0, MSB ; SDIR 1, LSB SDIR 0 2: EXSC EXSC 0, ; EXSC 1, P42/SCLK EXSC 0 1: SEND SEND,, SEND 1, SEND, SCON SEND SEND 0 0: ENTR ENTR 0, ENTR 1,, 0 ENTR, SIOINT ENTR 0 76
(2) (SBUFH, SBUFL) SBUFL SD0 LSB, SBUFH SD7 MSB, SBUFL SBUFH 8-3 8-3 77
8-1 / SBUFL 06H R/W 0H SBUFH 07H R/W 0H SCON 08H R/W 0H IE0 30H R/W 0H IRQ0 34H R/W 0H 78
91 15 4, (BDCON) (BFCON) 92 9-1 9-1 93 BDCON EBD 1, BD BFCON 15 BDCON SELF BD SELF 0, ( ); SELF 1, ( ) 50% BDCON BM1/BM0 :, 79
9-2: (a) 1, 8Hz (b) 2, 1Hz 8Hz (c), EBD, 16Hz (d), EBD 1 9-2 80
94 (1) (BDCON) BDCON, BD 3: SELF SELF 0, BD ( ); SELF 1, BD ( ) SELF 0 2: EBD EBD 0, 1 0: BM1 BM0 00, 1 81
(2) (BFCON) 3~0: BF3~0, 0, 50% 9-2 / BDCON 0AH R/W 0H BFCON 0BH R/W 0H 82
95 BD 9-3 BD 83
9-4 9-4, 84
(Capture Circuit) 101 P00 P01 ( P00 P01 ), P00 P01 ( P00 P01 ), P00 P01 32Hz 256Hz (CAPCON) (CAPR0, CAPR1), 102 10-1 85
103 10-2 CAPR0 10-1, ECAP0 1, P00, CRF0 2KHz 1 ( 10-2 ) CRF0 1, CAPR0, 32Hz, 64Hz, 128Hz 256Hz CAPR0( 10-2 ), CPAR0, CRF0 ( 10-2 ) 1 CRF0, P00 ( ), ( 10-2 ) ECAP0, CAPR0, CAPR0, 32Hz 256Hz CAPR1 CAPR0 10-2 CAPR0 86
104 (1) (CAPCON) CAPCON 4 3: CRF1 CAPR1 P01 P01 P01 P01, CRF1 1 CRF1 ECAP1 1, 32Hz 256Hz CAPR1 1 CRF1, P01 CAPR1, CRF1 CRF1 0 2: CRF0 CRF1, CAPR0 1: ECAP1 CAPR1 ECAP1 0,, CAPR1, ECAP1 1 CRF1 1, 32Hz 256Hz CAPR1, CAPR1 ECAP1 0 0: ECAP0 ECAP1, CPAR0 87
(2) (CAPR0, CAPR1) 4, 10-1 / CAPCON 0EH R/W 0H 0 CAPR0 0CH R 0H 1 CAPR1 0DH R 0H 88
(WDT) 111 6, CPU 112 11-1 89
113, (WDT), (WDTC) (WDTCON) 5H 0AH WDTC, WDTC 19~20, (WDTINT) WDTINT,, WDTC CPU, WDTC, WDTC CPU 11-2, 0, 5H WDTCN WDTC, 1, 0AH WDTCON WDTC WDTC 0, WDTC 11-2 90
11-3 11-3 : WDTC ; 5H WDTCON( 0 1); 0AH WDTCON WDTC ( 1 0); 5H WDTCON( 0 1); 0AH WDTCON WDTC ( 1 0); 5H WDTCON( 0 1); 1 0AH WDTCON, WDTC, 0 114 (WDTCON) WDTCON 91
A/D (ADC) 121 2 RC A/D 2, A (CNTA0~4), B (CNTB0~3) ADC (ADCON0 ADCON1) RC, ADC, 122 A/D 12-1 123 A/D 12-1, RC A 48 (1/10 4 8), (CLK), 79,999 B RC (OSCCLK) 14, 16,383 A B (OVFA OVFB) ADINT ADCON0 SADI A B ADINT SADI 0, A, SADI 1, B ADINT 02FH ADCON0 EADC A/D / EADC 1, RC, RC, EADC 0, RC, A/D RC ADCON1, RC P43, 92
12-1 A/D 93
1231 RC RC A/D : ( ) ( ) A/D RC, ( ), A/D, A/D, ( ) 12-1 ( ADCON1 ) ADCON1 CROSC0 CROSC1 OM3 OM2 OM1 OM0 RS0 RT0 CRT0 CS0 RS1 RT1 0 1 2 3 4 5 6 7 0 0 0 0 Z Z Z Z Z 0 0 0 1 1/0 Z Z 0/1 Z 0 0 1 0 Z 1/0 Z 0/1 Z 0 0 1 1 Z Z 1/0 0/1 Z 0 1 0 0 1/0 Z 0/1 Z Z 0 1 0 1 Z Z Z Z 1/0 0 1 1 0 Z Z Z Z Z 0 1 1 1 Z Z Z Z Z Z Z Z Z Z Z IN0 RS0-CS0 RT0-CS0 RT 0-1 -CS0 RS0-CT0 RS1-CS1 1/0 RT1-CS1 8 1 Z Z Z Z Z Z Z IN1 : Z ; 1/0 0/1 ; 1 4 CROSC0, 5 6 CROSC1 0 7 IN0 IN1, RC,, : t OSCCLK, K OSCCLK, C C S C T, R R S R T k OSCCLK V DD, RI, C R, 12-2 94
12-2 RC k OSCCLK V DD (V) RIn(kW) CSn, CTn(pF) RSn, RTn(kW) k OSCCLK 820 100 22 3 10 820 10 25 15 10 : n = 0, 1, 0-1 820 100 22 820 10 24 OM3 OM2 OM1 OM0 0 0 0 1 RS0 0 0 1 0 RT0 12-2 CROSC0 OM3 OM2 OM1 OM0 0 0 0 1 RS0 0 0 1 0 RT0 0 0 1 1 RS 0-1 CROSC0 (, ) 95
OM3 OM2 OM1 OM0 0 0 0 1 CS0 0 1 0 0 CT0 OM3 OM2 OM1 OM0 0 1 0 1 RS1 0 1 1 0 RT1 96
A, B RC (OSCCLK), B, RC B ( B RC (OSCCLK), A, A, RC A 12-6, : [1] A 80,000-nA0 1(80,000) na0 A(CNTA4 CNTA0) na0 [2] B 0000H B [3] ADCON1 OM3 OM0 ( 12-1) [4] 1H ADCON0(SADI = 0, EADC = 1), [1] [3] [4] A/D EADC 1 CRON 1, A ( CRON 1 ) A, [5] EADC,, [6] ADC ADCINT 1 A/D CRON 1, RC, B RC (OSCCLK) A, EADC, B B na0 t SYSCLK nb0 nb0 na0 t SYSCLK t OSCCLK f OSCCLK, t SYSCLK, t OSCCLK OSCCLK nb0 RC f OSCCLK 97
12-6 A 98
B 12-7, : [1] B 4000-nB1 1(4000) nb1 A(CNTB4 CNTB0) NB1 [2] A 0000H A [3] ADCON1 OM3 OM0 ( 12-1) [4] 3H ADCON0(SADI = 1, EADC = 1), [1] [3] [4] A/D EADC 1 CRON 1, B RC ( CRON 1 ) B, [5] EADC,,, [6] ADC ADCINT 1 A/D CRON 1, RC, A RC (OSCCLK) B, EADC, A A nb1 t SYSCLK na1 na1 nb1 t SYSCLK t OSCCLK 1 f OSCCLK, t SYSCLK, t OSCCLK OSCCLK na1 RC f OSCCLK 99
12-7 B 100
1233 A/D ( ) A B A/D 12-8 RC 12-8 RC ( CROSC0) 12-9 12-10 A/D 12-9, RT0 RT0 = f (T) 12-10 A/D, RT0, A/D nt0 RT0 101
K nt0 = K RT0 = K f (T) - - - - - (a) 12-9 nt0, RT0, RT0 RS0 RS0,, 12-11 12-12 12-13, f OSC (RT0) f OSC (RS0),,,, f OSC (RT0) f OSC (RS0) ( A/D nt0) RT0 12-11 12-12 12-13 102
12-14 RT0,,, :, A RS0, B RT0 RT0, :, B RS0, A RT0 12-14 A/D 12-14 103
12-14, na0 = 12,000, t SYSCLK = 1/32768, [1] [10], [a] [f] < > [1] (, ) 32768KHz, 0H FCON [2] A 80,000 - na0 : na0 = 12,000 RS0 0366 na0 A/D, na0, [3] B [4] 1H ADCON1 RS0 : [5] 1H ADCON0 A/D ( A ) [6] HALT HLT 1 : RC RC, RC (CROSC0) RS0 0366, A, [a] ADINT 1 ADC, [b] CPU [c] A/D (EADC = 0) A 00000 B : nb0 = na0 t SYSCLK t OSCCLK(RS0) - - - - - (b) < > [7] 4000 - nb0 B : A, A 00000, [8] 2H ADCON1 RT0 [9] 3H ADCON0 A/D ( B ) [10] HALT HLT 1 RC (CROSC0) RT0 B nb0 t OSCCLK(RT0) B, [d] ADINT 1 ADC, [e] CPU [f] A/D (EADC = 0) A na1 A/D : na1 = nb0 t OSCCLK(RT0) t SYSCLK - - - - - (c) (b) (c) : na1 = na0 t OSCCLK(RT0) t OSCCLK(RS0) - - - - - (d ) t OSCCLK(RS0) RS0, t OSCCLK(RT0) RT0, 104
t OSCCLK(RS0) = k OSCCLK CS0 RS0 t OSCCLK(RT0) = k OSCCLK CS0 RT0 - - - - - (e) (e) (d ) = na0 RT0 RS0 na0( 12,000) RS0, na1 RT0 na1 (a) nt0 na1 1234 RC P43CON MON 1, RC P43,,, A/D 105
124 ADC (1) ADC 0 (ADCON0) 1: SADI SADI 0, ADC A, SADI 0 ADC B SADI 0 0: EADC ADC EADC 1, A/D, A/D EADC 1, A B EADC, EADC A/D EADC 0 106
(2) ADC 1(ADCON1) RC 107
(3) A/D A(CNTA0 CNTA4) : CNTA0 CNTA3, 0~9 108
(4) A/D B(CNTB0 CNTB3) 109
12-3 12-4 A/D 12-3 A/D / ADC 0 ADCON0 2AH R/W 0CH ADC 1 ADCON1 2BH R/W 0H CNTA0 20H R/W 0H CNTA1 21H R/W 0H A CNTA2 22H R/W 0H CNTA3 23H R/W 0H CNTA4 24H R/W 0H CNTB0 26H R/W 0H CNTB 27H R/W 0H B CNTB 28H R/W 0H CNTB 29H R/W 0CH 12-4 A/D GP GA, TB PADI/O RT0 33 31 31 Output 0 CRT0 34 32 32 Output 0 / RS0 35 33 33 Output 0 CS0 36 34 34 Output 0 IN0 37 35 35 Input 0 RC RT1 41 39 39 Output 1 RS1 40 38 38 Output 1 CS1 39 37 37 Output 1 IN1 38 36 36 1 RC 110
(LCD Driver) 131, 1/4 (duty), 1/3, 1/2, 120, 93 64 34 (, COM, SEG ),,,, C L26 L33 132 13-1 111
13-2 (L0 L25) 112
13-3 (L26 L33) 113
133 13-2, L0 DSPR0 0 1 1 2, DSPR1 2 3 3 4 13-3, L26 1, 134 (DSPCON) DSPCON 1 0: DUTY1, DUTY0 DUTY1 DUTY0, 00 1 114
135 0 30(DSPR0 DSPR30) BANK0, 40H 5EH, 0, 1, 0 115
136 L26 L33 8, 13-4 DSPR0 L26 L29, V DD, V SS 13-4 DSPR0 L26 L29, DSPR0 DSPR1, 116
137 (BIAS), 13-1 13-1 V DD 15V 30V V DD V DD 12V 15V 12V 30V V DD3 36V 45V 36V 45V V DD2 24V 30V 24V V DD1 12V 15V ( ) ( ) 12V ( ) 30V ( ) 15V 117
(a) (V DD 15V 30V) (b) V DD V DD 15V (c) V DD V DD 15V 13-5 (C a, C b, C c, C 12 = 01 F),, C a, C b, C c, C 12, V DD3, V DD2, V DD1, C1, C2 1/2, C b, V DD3 118
138 13-6(a) (c) 1/4, 13-7(a) (b) 1/3, 13-8(a) (b) 1/2 13-6(a) 1/4 (1/3 ) 119
13-6(b) 1/4 (1/3 ) 120
13-6(c) 1/4 (1/3 ) 121
13-7(a) 1/3 (1/3 ) 122
13-7(b) 1/3 (1/3 ) 123
13-8(a) 1/2 (1/2 ) 13-8(b) 1/2 (1/2 ) 124
141 142 14-1 * BUPF 0 CPUCLK 14-1 14-1, C L V DDL, 005 125
13V V DDL 700KHz RC, V DDL V DD, BUPF 1, V DDL VDD BUPF V DDL 13V( ) VDDL VDD 14-2, VDDL VDD 05 14-2 V DDL 14-1 V DDL CPUCLK BUPF V DDL 05 V DD 0 0 13V 0 1 V DD 1 V DD 126
144 (BUPCON) 4 BUPCON 127
151 TST1 TST2, A/D RC 700KHz RC P43, RC, A/D 152 TST1 TST2, RESET ( RESET ),, TST1 TST2, TST1 TST2, 15-1 TST1, TST2 RESET 15-1 TST1, TST2 RESET, P43 RC P00 P03, 15-1 15-2 : TST1 TST2, 128
15-1 TST1 TST2 P03 P02 P01 P00 P43 0 0 1 0 0 0 CROSC0 (P43 = IN0 ) 0 0 1 0 0 1 RS0-CS0 0 0 1 0 1 0 RT0-CS0 0 0 1 0 1 1 RT0-1-CS0 0 0 1 1 0 0 CT0-1-RS0 0 0 1 1 0 1 RS1-CS1 0 0 1 1 1 0 RT1-CS1 0 0 1 1 1 1 CROSC1 (P43 = IN1 ) 0 0 0 700KHz RC CROSC0 CROSC1 : 0: 1: : 129
15-2 130
(BC) 161 IC (R BLD ) 162 BC P03 16-1 131
P03,, NMOS (R BLD ), Vrb 06V 163 ECMP CMPF ( BUPCON) ECMP ECMP 1,, ; ECMP 0, CMPF CMPF 1,, 0 ECMP 0, CMPF 16-2 16-2 132
SSU4168P(OTP ) 171 SSU4168P OTP, PROM,, SSU4168P : PROM,, PROM OTP SSU4168P 172 SSU4168P : 1) (PROM)8160 2) LCD : 34 1/4, 1/3 : 120 (30 1/3, 1/3 : 93 (31 1/2, 1/2 : 64 (32 3) : 80 (QFP) 133
173 17-1 SSU4168P 134
174 17-2 SSU4168P(GA) 135
17-3 SSU4168P(GP) 136
175 1751 SSU4168P 17-1 OTP GP GA I/O V PP 31 29 PROM (+125V) V DDI 43 41 I/O V DD 15V, 27V ( PROM ) V DD 30V, SSU4168P, V DDL 137
1752 PROM 17-2 PROM GP GA I/O V SS 32 30, 0V V DD 67 65, +5V V DDI 43 41, +5V V PP 31 29 PROM, +125V RESET TST1 70 68 Input 71 69 Input PROM, PROM TST2 72 70 Input D0(L0) 1 79 I/O D1(L1) 2 80 I/O D2(L2) 3 1 I/O D3(L3) 4 2 I/O D4(L4) 5 3 I/O D5(L5) 6 4 I/O D6(L6) 7 5 I/O LCD D7(L7) 8 6 I/O 9 7 I/O PROM CE (L8) OE (L9) 10 8 I/O PROM A0(L10) 11 9 Input A1(L11) 12 10 Input A2(L12) 13 11 Input A3(L13) 14 12 Input A4(L14) 15 13 Input A5(L15) 16 14 Input A6(L16) 17 15 Input A7(L17) 48 46 Input A8(L18) 49 47 Input A9(L19) 50 48 Input A10(L20) 51 49 Input A11(L21) 52 50 Input A12(L22) 53 51 Input L23 54 52 Input 138
176 SSU4168P, SSU4168P (BUPCON) BUPF 177 17-4 17-5 OTP SSU4168P 17-4 139
17-5 SSU4168P 140
178 PROM SSU4168P, 8160 PROM SSU4168P ( ) PROM, PROM, SSU4168P PROM,, RESET, TST1, TST2, SSU4168P PROM,,, 17-5 PROM CE (L8) OE (L9) V PP V DD V DDI D7 D0 (L7 L0) 0 0 5V 5V 0 1 125V 5V 0 0 125V 5V 17-6 SSU4168P EPROM SW1 D 141
17-6 SSU4168P 142
181 148, HL XY, 121 RAM (SFR) SRF, SFR RAM, SFR, 148 : 81 63 ( 26 XY ) 3 ( XY ) : (1) ; (2) HL XY ; (3),,, ; (4) ; (5) (Skip) (Jump) ; (6) (LMTB a4), (ROM) (7) (LAI n4, LLI n4), 1 5 ( 3 CPU ), 55 ; 2 75 ( 18 XY ); 3 13 ( 9 XY ); 4 2 ; 5 3, : (1) 4 (2) 8 (3), 4 8 (4) 4 (5) 8 (6) (7) / (8) 143
(9) (10) (11) (12) NOP 182 : A C B,H,L,X,Y BA B A 8, B HL H L 8, H XY X Y 8, X BSR BEF, BSR1, BCF, BSR0 M(y) y 4 Mb(y) y+1 8, T(y) ROM y 8 PC SP ST SP SP-1 8 (SP ) MI @XY XY, HL nx x In n ax PC ROM x, PC 0, PC 8 m8 8 r[n2] r n2, r,, n2 0 3 XH H X 16 Skip if,, CPU Carry Borrow 144
145
146
147
148
149
183 (1) 150
(2) ( @XY, XY ) 151
(3) (@XY ) 152
[] A: / A / (P20~P23, P30~P33, P40~P43) B (P00~P33) C (P10~P13) D (L26/P50~L29/P53, L30/P60~L33/P63) 153
E BD CS1 F RS0, RS1, RT0, RT1, CS0 CRT0 G IN0 IN1 H I RC 154
J RESET, TST1 TST2 155
B: B-1 3V 156
B-2 15V 157
C: C G C G LCD-VR 15V 30V LCD : SEG SIGNAL C/S/P DATA DSPR LCD LCD L0 L33 (COM ), (SEG ) C, S P, (a, b, c, d) (0~30) : (1) MASK164 MASK164 (2), (3) P L26 L33, DSPR 0 1 (4),, (5) (DSPR0~31) 158
LCD (1) L0 COM2, L1, L2 (1/4 ) (2) L27 COM1, L28, L29 159
[SSU4168P] D: SSU4168P-xxxGA SSU4168P-xxxGP 160
E: E-1 3V 161
E-2 15V 162
F: C, SSU4168P, 001 004 CG LCD-VR LCD 001 15 LCD 1 002 3 LCD 1 003 15 LCD 2 004 3 LCD 2 163
LCD 1 164
LCD 2 165
G: PAD 166
12,, O(0,0) Table 12 Pad Center Coordinates PAD NO PIN NAME X(um) Y(um) PAD NO PIN NAME X(um) Y(um) 1 L2-1300950 1138185 41 VDDI 1300950-1270710 2 L3-1300950 1019115 42 VDD2 1300950-1155195 3 L4-1300950 900045 43 VDD3 1300950-1039680 4 L5-1300950 780975 44 C1 1300950-924165 5 L6-1300950 661905 45 C2 1300950-808650 6 L7-1300950 542835 46 L17 1300950-693135 7 L8-1300950 423765 47 L18 1300950 8 L9-1300950 304695 48 L19 1300950-462105 9 L10-1300950 185625 49 L20 1300950-346590 10 L11-1300950 66555 50 L21 1300950-231075 11 L12-1300950 -52515 51 L22 1300950-115560 12 L13-1300950 -171585 52 L23 1300950-0045 13 L14-1300950 -290655 53 L24 1300950 115470 14 L15-1300950 -409725 54 L25 1272150 346590 15 L16-1300950 -528795 55 L26/P50 1272150 693135 16 P20-1300950 -647865 56 L27/P51 1272150 808650 17 P21-1300950 -766935 57 L28/P52 1272150 924165 18 P22-1300950 -886005 58 L29/P53 1272150 1039680 19 P23-1300950 -1005075 59 L30/P60 1272150 1155195 20 P30-1300950 -1124145 60 L31/P61 1272150 1270710 21 P31-1300950 -1270710 61 L32/P62 1112715 1270710 22 P32-1172475 -1270710 62 L33/P63 985680 1270710 23 P33-1044000 -1270710 63 OSC2 858645 1270710 24 P40-915525 -1270710 64 OSC1 731610 1270710 25 P41-787050 -1270710 65 VDD 604575 1270710 26 P42-658575 -1270710 66 XT 477540 1270710 27 P43-530100 -1270710 67 XT 350505 1270710 28 BD -401625-1270710 68 RESET 223470 1270710 29 VDDL -273150-1270710 69 TST1 96435 1270710 30 VSS -144675-1270710 70 TST2-30600 1270710 31 RT0-16200 -1270710 71 P10-157635 1270710 32 CRT0 112275-1270710 72 P11-284670 1270710 33 RS0 240750-1270710 73 P12-411705 1270710 167
34 CS0 369225-1270710 74 P13-538740 1270710 35 IN0 497700-1270710 75 P00-665775 1270710 36 IN1 626175-1270710 76 P01-792810 1270710 37 CS1 754650-1270710 77 P02-919845 1270710 38 RS1 883125-1270710 78 P03-1046880 1270710 39 RT1 1011600-1270710 79 L0-1173915 1270710 40 VDD1 1140075-1270710 80 L1-1300950 1270710 : VSS 90% The value of the table is the value of the 90 percent measured from layout 168
X: ML64168/168P /4168P 169