V2.03 2005-9-1 FPGA SOC FPGA/SOPC IT QuartusII NiosII IDE FPGA/SOPC FPGA/SOPC FPGA/SOPC CT-SOPCx FPGA/SOPC CPLD/FPGA www.fpga.com.cn CPLD/FPGA FPGA QuartusII NiosII CPU SOPC SOPC Builder NiosII IDE 1 www.21control.com www.21control.com 1
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QuartusIIFPGA ALTERA LPM Symbol FPGA 11
FPGA quartusii KEY1 1 0 LEDKEY1 LED KEY1 LED 1 QuatrusII Q2FileNew Project Wizad 12
Next 13
Next FPGA Family Cyclone FPGAAvailable devices FPGA FPGA Filters Show Advanced Devices 14
EDA Q2 Next Finish 2 FileNew 15
Block Diagram Schematic File OK Block1.bdfFileSave as Add file to current project 3 Symbol 16
Libraries Name OK notinputoutput symbol symbol symbol symbol input output symbol pin_namepin_name1 Key1LED1 4 QuartusII AssignmentsPins 17
tcl Tcl tcl QuartusII name Setup.tcl filefilenew other files tcl QuartusII FPGA.tcl CT-SOPCx 1 EP1C3 #Setup.tcl # Setup pin setting set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF set_location_assignment PIN_6 -to LED1 set_location_assignment PIN_52 -to key1 2 EP1C6 #Setup.tcl # Setup pin setting set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF set_location_assignment PIN_1 -to led1 set_location_assignment PIN_156 -to key1 18
5 AssignmentsDevice 19
FPGA EP1C3T144C8 Device & Pin Options Device & Pin Options Configuration Configuration 20
OK 6 QuartusII Message 7 1 FPGA Q2 ByteBlasterII PC ToolsProgrammer No Hardware Hardware SetupHardware Setup 21
Add HardwareAdd Hardware Hardware type ByteBlasterMV or ByteBlasterII OK Hardware SetupCurrently selected hardware ByteBlasterII[LPT1]Close 2 ByteBlasterIIPCJTAGEPCS1 JTAGEPCS1 Pin1 ByteBlasterII 10 Pin1 3 FPGA 5V 4 JTAG 22
FPGA Mode JTAG.sof Program/ConfigureVerifyBlank Check 5 Flash ByteBlasterII EPCS1 Mode Active Serial Programming.pof LEDD1 Setup.tcl&set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" EP1C6 V2.0As inputs, tri-stated FlashFPGA LEDD2 FPGA&D1 1KEY1 Assignments->Settings Setting Device & Pin OptionsDevice & Pin Options 23
Unused PinsReserve all unsued pinsdevice & Pin Options QuartusII 8 KEY1 1 0 LED KEY1 LED FPGA QuartusII FPGA LED QuartusII FPGA 24
8 8 VHDL 1. seg7led_test 2. Altera LPM LPM symbol Libraries lpm_counter OK 25
Next 8 Next Next Next Finish LPM_Counter updown1 0 clock aclr q[7..0] 3. FileNew 26
OKVHDLbin27seg.vhdQuartusII entityvhdl library IEEE; use IEEE.std_logic_1164.all; entity bin27seg is port ( data_in : in std_logic_vector (3 downto 0); data_out : out std_logic_vector (6 downto 0) ); end entity; architecture bin27seg_arch of bin27seg is begin process(data_in) begin case data_in is when "0000" => data_out <= "0111111"; -- 0 when "0001" => data_out <= "0000110"; -- 1 when "0010" => data_out <= "1011011"; -- 2 when "0011" => data_out <= "1001111"; -- 3 when "0100" => data_out <= "1100110"; -- 4 when "0101" => data_out <= "1101101"; -- 5 when "0110" => data_out <= "1111100"; -- 6 when "0111" => data_out <= "0000111"; -- 7 when "1000" => data_out <= "1111111"; -- 8 when "1001" => data_out <= "1100111"; -- 9 when "1010" => data_out <= "1110111"; -- A when "1011" => data_out <= "1111100"; -- b when "1100" => data_out <= "1011000"; -- c 27
when "1101" => data_out <= "1011110"; -- d when "1110" => data_out <= "1111001"; -- E when "1111" => data_out <= "1110001"; -- F when others => NULL; end case; end process; end architecture; Q2 ProjectSet as top-level Entity vhd Start Analysis &Synthesis Symbol FileCreate/UpdateCreate Symbol files for current file 4. ProjectSet as top-level Entity symbol Libraries Project OK 28
protel q[3..0] q3 q0 4 q[7..4] inst6 data_in[3..0] inst 4 q[7..4] 5. 6 tcl script tcl 1 EP1C3 tcl CT-SOPCx #Setup.tcl # Setup pin setting for EP1C3 main board set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF set_location_assignment PIN_52 -to key1 set_location_assignment PIN_53 -to key2 set_location_assignment PIN_54 -to reset set_location_assignment PIN_68 -to seg7led1\[0\] set_location_assignment PIN_61 -to seg7led1\[1\] set_location_assignment PIN_56 -to seg7led1\[2\] 29
set_location_assignment PIN_55 -to seg7led1\[3\] set_location_assignment PIN_59 -to seg7led1\[4\] set_location_assignment PIN_67 -to seg7led1\[5\] set_location_assignment PIN_62 -to seg7led1\[6\] set_location_assignment PIN_72 -to seg7led2\[0\] set_location_assignment PIN_69 -to seg7led2\[1\] set_location_assignment PIN_58 -to seg7led2\[2\] set_location_assignment PIN_60 -to seg7led2\[3\] set_location_assignment PIN_57 -to seg7led2\[4\] set_location_assignment PIN_71 -to seg7led2\[5\] set_location_assignment PIN_70 -to seg7led2\[6\] 2 EP1C6 tcl #Setup.tcl # Setup pin setting for EP1C6 main board set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF set_location_assignment PIN_156 -to key1 set_location_assignment PIN_158 -to key2 set_location_assignment PIN_159 -to reset set_location_assignment PIN_169 -to seg7led1\[0\] set_location_assignment PIN_166 -to seg7led1\[1\] set_location_assignment PIN_161 -to seg7led1\[2\] set_location_assignment PIN_160 -to seg7led1\[3\] set_location_assignment PIN_164 -to seg7led1\[4\] set_location_assignment PIN_168 -to seg7led1\[5\] set_location_assignment PIN_167 -to seg7led1\[6\] set_location_assignment PIN_175 -to seg7led2\[0\] set_location_assignment PIN_170 -to seg7led2\[1\] set_location_assignment PIN_163 -to seg7led2\[2\] set_location_assignment PIN_165 -to seg7led2\[3\] set_location_assignment PIN_162 -to seg7led2\[4\] set_location_assignment PIN_174 -to seg7led2\[5\] set_location_assignment PIN_173 -to seg7led2\[6\] 6. ProjectSet as top-level Entity 7. 00 KEY1 KEY2 RESET 30
MCUDSP FPGA 51 ARM MCU DSP FPGA MCUDSPFPGA SOPC MCU + DSP + FPGASOPC MCUDSP FPGA 1 SOPC MCU FPGA 16 32 MCU Altera FPGA CPUNios NiosII ARM 2 SOPC DSPDSP FPGA DSP IP FFT IIRFIRCodec FPGA MPEG4 / DSP 10 DSP Builder IP 3 SOPC FPGASOPC FPGA FPGA MCU DSP MCU+DSP+FPGA ALTERA CycloneStratixStratixII FPGA Altera FPGA SOPC NiosII Altera SOPC Builder DSP DSP Builder 2 31
SOPC FIR DSP FFT Codec NiosII (MCU) 1 n Altera Nios II Nios II Altera FPGA StratixII StratixCyclone 200 DMIPS 60 IP Nios II Nios II Nios II 200 DMIPS FPGA Nios II I/O FPGA NiosII Cyclone FPGA 35 NiosII 1020 FPGA NiosII Nios II 32
Nios II IDE Altera SOPC Builder Quartus II QuartusII NIOS SOPC ALTERA LPM Simbol SOPC Buider NIOS NIOS IDE FPGA FPGA FPGA JTAG RAM 33
QuartusII FPGA FPGA QuartusII NiosII SOPC 1 NiosII 2 NiosII 3 NiosII IDE 4 5 Cyclone PLL LED 2 sopc_led sopc_led QuartusII 3 SOPC Builder NiosII ToolsSOPC Builder niosii_c OK SOPC 34
Target Unspecified Board ClockMHz 50.0 Target Device Family Cyclone SOPC CPU NiosII Processor Altera Corporation Altera NiosII CPU NiosII/e JTAG Debug Module Level1 Finish NiosII CPU niosii cpu_0,:rename 35
On-Chip Memory(RAM or ROM),( Avalon Modules -> Memory -> ) RAM. Memory Type RAMData Width 32bits,Total Memory Size 4K bytes Finish SOPC Builder 36
PIO( Parallel I/O)( Avalon Modules -> Other ) LED Width 2 bits, Finish SOPC Builder 37
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HDL.Generate system module logic in Verilog, Simulation.Create ModelSim(tm) project files Generate, 39
4 QuartusII niosii QuartusII NiosII CPU Symbol Project niosii_c OK niosii_c 40
5 PLL QuatusII PLL CPU Symbol altpll OK altpll 41
Next Which Device family will you be using?cyclone Which device speed grade will you be usingany What is the frequency of the inclk0 input?25.00mhz 16MHz 16MHz 42
Next Next c0 Use this clock Enter output clock parameters; Clock multiplication factorclock division c0 CPU 50MHz 25MHz 2 1 10MHz 5 1 altpll 43
c1 e0 Finish pll c0 Finish QuartusII PLL 6 clk reset led[1..0] 44
7 tcl 1 EP1C3 tcl CT-SOPCx #Setup.tcl # Setup pin setting for EP1C3 main board set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF set_location_assignment PIN_16 -to clk set_location_assignment PIN_54 -to reset set_location_assignment PIN_6 -to led\[0\] set_location_assignment PIN_7 -to led\[1\] 2 EP1C6 tcl #Setup.tcl # Setup pin setting for EP1C6 main board set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF set_location_assignment PIN_28 -to clk set_location_assignment PIN_159 -to reset set_location_assignment PIN_1 -to led\[0\] set_location_assignment PIN_2 -to led\[1\] 8 FlashEPCS1 EPCS1 FPGA 9 Nios IDE Nios II IDE File -> New -> Project New Project C/C++ Application 45
Next Hello LED SOPC Builder SystemBrowse niosii_c.ptf NiosII IDE 46
Finish Hello_LED_0 hello_led.c 47
int alt_main (void) { alt_u8 le d = 0x2; volatile int i; while (1) { for(i=0;i<300000;i++) ; led = 0x1; *(unsigned int *)PIO_0_BASE = led; for(i=0;i<300000;i++) ; led = 0x2; *(unsigned int *)PIO_0_BASE = led; } return 0; } 10 hello_led_0 Properties Properties for hello_led_0configuration SettingsGeneralOptimization LevelOptimize size (-Os 48
OK hello_led_0 hello_led_0_syslib[niosii_c] hello_led_0_syslib[niosii_c]properties Properties for hello_led_0_syslib Configuration SettingsGeneralOptimization Level Optimize size-os 49
System Library System library Max file descriptors: 4Clean exit (flush buffers)link with profiling libraryreduced device driverssmall C library OK 11 hello_led_0build Project 50
Build completed. 760 Bytes 3336 Bytes niosii_c 4K 12 ByteBlasterII FPGA JTAG 5V RunDebug AsNiosII Hardware NiosII IDE Debug Perspective 51
Resume led C/C++ 13 QuartusII EPCS1 52
QuartusII Processing -> Star Compilation, 14 EPCS1 15 LED RESET QuartusII NiosII IDE SOPC CT-SOPCx FPGA/SOPC FPGA LED LCD LED KEY1 1KEY2 1 LCD PC NiosII EP1C6 EP1C3 EP1C6_ExamplesEP1C3_Examplesall_test 1. 32 NiosII CPU0NiosII/e Level1 2. onchip_memory_032 4Kbyte 3. uart_0 96008 1 4. LED IOpio_led2 Output ports only 5. Timer0 6. IOpio_key2bitsInput ports only 7. LCD pio_led_data8bits Bidirection tri-state ports 8. LCD pio_led_ctl3bitsoutput ports only 9. 7 IOpio_seg7led8bitsOutput ports only LCD SOPC Builder Character LCD 16X2 Optrex 15207 LCD 1602A LCD 8 53
IO LCD 3 IO LCD lcd_e, lcd_rs, lcd_rw Altera Character LCD16X2 Optrex 15207 1602A LCD Nios V1.0EPCS1 COM 9600 8 1 V2.0 V1.0 USBUART CP2102E 2 PROM AT24C32EP1C3 4 Pins IOSPIIO EP1C3 E 2 PROM 4 Pins IOSPIIO USB UART SOPC Cyclone RS232 RS485USB RS232 USB USB V2.0 USB V2.0 USB UART USB 54
USB -40+85 \EP1C6_Examples\all_test_USB 2. 115200 8 1 3. NiosII IDE SSCOM32.EXEsscom.ini SSCOM32.EXE USB 55
CP2102 USB UART COM USB COM COM 115200 8 1 EP1C6 EP1C3 EP1C6_ExamplesEP1C3_Examplesall_test_USB 4. USB EP1C6 V2.0 8Mbyte SDRAM 2Mbyte Flash EPCS1 Flash EP1C6 RAM SDRAM Flash NiosII IDE Flash Programmer 56
/altera/kits/nios2/documents ug_nios2_flash_programmer.pdf Nios IDE Flash \EP1C6_Examples\burn_flash_ep1c6ucosII_test SDRAM uc/os-ii Nios II uc/os-ii uc/os-ii FAA 3 uc/os-ii NiosII uc/os-ii\ep1c6_examples\ucosii_test Task1 Task2uc/OS-II NiosIINiosIIuc/OS-II Jean J. LabrosseMicroC/OS-II The Real-Time Kernel(Second Edition)uc/OS-II 3 uc/os-ii 57
CT-SOPCx Altera Cyclone FPGA FPGA/SOPC 58
CT-SOPCx 59
CT-SOPCx FPGA/SOPC 2 3 4 5 6 7 8 60
1. FPGA CT-SOPCx FPGA/SOPC 1FPGA_led_test FPGA LED FPGA 2seg7led_test QuartusII SOPCNios II 1sopc_led NiosII FPGA LED SOPC 61