PHT6N6T THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-sp From junction to solder point Mounted on any PCB 1 15 K/W R th j-amb

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1 PHT6N6T GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT logic level field-effect power transistor in a plastic envelope V DS Drain-source voltage 55 V suitable for surface mounting. I D Drain current (DC) T sp = 5 C 5.5 A Using trench technology the Drain current (DC) T amb = 5 C.5 A device features very low P tot Total power dissipation 8.3 W on-state resistance and has T j Junction temperature 15 C integral zener diodes giving R DS(ON) Drain-source on-state 15 mω ESD protection. It is intended for resistance V GS = 1 V use in DC-DC converters and general purpose switching applications. PINNING - SOT3 PIN CONFIGURATION SYMBOL PIN 1 gate DESCRIPTION d drain 3 source g drain (tab) 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 13) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drain-source voltage V V DGR Drain-gate voltage R GS = kω - 55 V ±V GS Gate-source voltage - - V I D Drain current (DC) T sp = 5 C A T amb = 5 C -.5 A I D Drain current (DC) T sp = 1 C A T amb = 1 C A I DM Drain current (pulse peak value) T sp = 5 C - A T amb = 5 C - 1 A P tot Total power dissipation T sp = 5 C W T amb = 5 C W T stg, T j Storage & operating temperature C ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V C Electrostatic discharge capacitor Human body model - kv voltage (1 pf, 1.5 kω) September Rev 1.

2 PHT6N6T THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-sp From junction to solder point Mounted on any PCB 1 15 K/W R th j-amb From junction to ambient Mounted on PCB of Fig.19-7 K/W STATIC CHARACTERISTICS T j = 5 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = V; I D =.5 ma V voltage T j = -55 C V V GS(TO) Gate threshold voltage V DS = V GS ; I D = 1 ma. 3.. V T j = 15 C V T j = -55 C - -. V I DSS Zero gate voltage drain current V DS = 55 V; V GS = V; µa T j = 15 C µa I GSS Gate source leakage current V GS = ±1 V -. 1 µa T j = 15 C µa ±V (BR)GSS Gate source breakdown voltage I G = ±1 ma V R DS(ON) Drain-source on-state V GS = 1 V; I D = 5 A mω resistance T j = 15 C mω DYNAMIC CHARACTERISTICS T mb = 5 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT g fs Forward transconductance V DS = 5 V; I D = 5 A; T j = 5 C S Q g(tot) Total gate charge I D = 5 A; V DD = V; V GS = 1 V nc Q gs Gate-source charge nc Q gd Gate-drain (Miller) charge - - nc C iss Input capacitance V GS = V; V DS = 5 V; f = 1 MHz - 19 pf C oss Output capacitance pf C rss Feedback capacitance pf t d on Turn-on delay time V DD = 3 V; I D = 5 A; ns t r Turn-on rise time V GS = 1 V; R G = 1 Ω; - 8 ns t d off Turn-off delay time ns t f Turn-off fall time T j = 5 C ns REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS T j = -55 to 175 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I DR Continuous reverse drain T sp = 5 C A current I DRM Pulsed reverse drain current T sp = 5 C A V SD Diode forward voltage I F = A; V GS = V V t rr Reverse recovery time I F = A; -di F /dt = 1 A/µs; ns Q rr Reverse recovery charge V GS = -1 V; V R = 3 V µc September 1997 Rev 1.

3 PHT6N6T AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT W DSS Drain-source non-repetitive I D = 1.9 A; V DD 5 V; mj unclamped inductive turn-off V GS = 1 V; R GS = 5 Ω; T sp = 5 C energy September Rev 1.

4 PHT6N6T PD% Normalised Power Derating Tmb / C Fig.1. Normalised power dissipation. PD% = 1 P D /P D 5 C = f(t sp ) 1E+ 3E+1 1E+1 3E+ 1E+ 3E-1 1E-1 3E- Zth / (K/W) D = T 1E- 1E-7 1E-5 1E-3 1E-1 1E+1 t / s Fig.. Transient thermal impedance. Z th j-sp = f(t); parameter D = t p /T P D tp T BUKX tp t ID% Normalised Current Derating Tmb / C Fig.. Normalised continuous drain current. ID% = 1 I D /I D 5 C = f(t sp ); conditions: V GS 1 V 1 16 ID/A VGS/V = Fig.5. Typical output characteristics, T j = 5 C. I D = f(v DS ); parameter V GS ID/A RDS(ON) = VDS/ID 1 1 DC VDS/V tp = 1 us 1 us 1 us 1 ms 1 ms 1 ms BUKX Fig.3. Safe operating area. T sp = 5 C I D & I DM = f(v DS ); I DM single pulse; parameter t p RDS(ON)mOhm ID/A Fig.6. Typical on-state resistance, T j = 5 C. R DS(ON) = f(i D ); parameter V GS September 1997 Rev 1.

5 PHT6N6T 1 ID/A 8 VGS(TO) / V 5 max. BUK78xx typ. min. Tj/C = VGS/V Fig.7. Typical transfer characteristics. I D = f(v GS ) ; conditions: V DS = 5 V; parameter T j Tj / C Fig.1. Gate threshold voltage. V GS(TO) = f(t j ); conditions: I D = 1 ma; V DS = V GS gfs/s E-1 1E- 1E-3 Sub-Threshold Conduction % typ 98% 1E E E-6 ID/A Fig.8. Typical transconductance, T j = 5 C. g fs = f(i D ); conditions: V DS = 5 V Fig.11. Sub-threshold drain current. I D = f(v GS) ; conditions: T j = 5 C; V DS = V GS a.5 BUK98XX-55 Rds(on) normalised to 5degC pf Ciss Tmb / degc Fig.9. Normalised drain-source on-state resistance. a = R DS(ON) /R DS(ON)5 C = f(t j ); I D = 5 A; V GS = 1 V VDS/V 1 1 Fig.1. Typical capacitances, C iss, C oss, C rss. C = f(v DS ); conditions: V GS = V; f = 1 MHz Coss Crss September Rev 1.

6 PHT6N6T 1 VGS/V VDS = 1V VDS = V QG/nC Fig.13. Typical turn-on gate-charge characteristics. V GS = f(q G ); conditions: I D = 5 A; parameter V DS WDSS% Tmb / C Fig.15. Normalised avalanche energy rating. W DSS % = f(t sp ); conditions: I D = 1.9 A 1 IF/A 8 L + VDD 6 Tj/C = 15 5 VGS VDS T.U.T. - -ID/1 RGS R 1 shunt VSDS/V Fig.1. Typical reverse diode current. I F = f(v SDS ); conditions: V GS = V; parameter T j Fig.16. Avalanche energy test circuit. W DSS =.5 LI D BV DSS /(BV DSS V DD ) RD + VDD VGS VDS - RG T.U.T. Fig.17. Switching test circuit. September Rev 1.

7 PHT6N6T MOUNTING INSTRUCTIONS Dimensions in mm. 3.8 min 1.5 min 1.5 min (3x) min.6 Fig.18. soldering pattern for surface mounting SOT3. PRINTED CIRCUIT BOARD September Rev 1.

8 PHT6N6T Dimensions in mm Fig.19. PCB for thermal resistance and power rating for SOT3. PCB: FR epoxy glass (1.6 mm thick), copper laminate (35 µm thick) September Rev 1.

9 PHT6N6T MECHANICAL DATA Dimensions in mm Net Mass:.11 g B. M A A max max 1 max (x) M B Fig.. SOT3 surface mounting package. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide.. Refer to surface mounting instructions for SOT3 envelope. 3. Epoxy meets UL9 V at 1/8". September Rev 1.

10 PHT6N6T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 13). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September Rev 1.

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