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1 INTEGRATED CIRCUITS MHz 1:9 clock driver 1999 Oct 19

2 MHz 1:9 clock driver FEATURES Phase-Locked Loop Clock distribution for PC100/PC133 applications Spread Spectrum clock compatible Operating frequency 50 to 150 MHz (t phase error jitter) at 100 to133 MHz = ±50 ps Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps Pin-to-pin skew < 200 ps Available in plastic 24-Pin TSSOP Distributes one clock input to one bank of ten outputs External Feedback (FBIN) terminal Is used to synchronize the outputs to the clock input adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic low state. Unlike many products containing PLLs, the does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV CC to ground. The is characterized for operation from 0 C to +70 C. PIN CONFIGURATION On-Chip series damping resistors AGND 1 24 CLK No external RC network required V CC 2 23 AV CC Operates at 3.3 V Inputs compatible with 2.5 V and 3.3 V ranges 1Y0 1Y1 1Y V CC 2Y0 2Y1 GND 6 19 GND DESCRIPTION The is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The operates at 3.3 V V CC and is input compatible with both 2.5 V and 3.3 V input voltage ranges. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are GND 1Y3 1Y4 V CC 1G FBOUT GND 2Y2 2Y3 V CC 2G FBIN SW00389 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 24-Pin Plastic TSSOP 0 C to +70 C PW SOT Oct

3 MHz 1:9 clock driver PIN DESCRIPTIONS PIN NUMBER SYMBOL TYPE NAME, FUNCTION, and DIRECTION 1 AGND GND Analog ground. AGND provides the ground reference for the analog circuitry. 2, 10, 15, 22 V CC PWR Power supply 3, 4, 5, 8, 9 1Y (0 4) OUT 6, 7, 18, 19 GND GND Ground 11 1G IN 12 FBOUT OUT 13 FBIN IN 14 2G IN 16, 17, 20, 21 2Y (0 3) OUT 23 AV CC PWR 24 CLK IN FUNCTION TABLE INPUTS OUTPUTS 1G 2G CLK 1Y (0 4) 2Y (0 3) FBOUT X X L L L L L L H L L H L H H L H H H L H H L H H H H H H H Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0 4) is enabled via the1g input. These outputs can be disabled to a logic LOW state by de-asserting the 1G control input. Each output has an integrated 25 Ω series-damping resistor. Output bank enable. 1G is the output enable for outputs 1Y(0 4). When 1G is LOW, outputs 1Y(0 4) are disabled to a logic LOW state. When 1G is HIGH, all outputs 1Y(0 4) are enabled and switch at the same frequency as CLK. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25 Ω series-damping resistor. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Output bank enable. 2G is the output enable for outputs 2Y(0 3). When 2G is LOW, outputs 2Y(0 3) are disabled to a logic LOW state. When 2G is HIGH, all outputs 2Y(0 3) are enabled and switch at the same frequency as CLK. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0 3) is enabled via the 2G input. These outputs can be disabled to a logic LOW state by de-asserting the 2G control input. Each output has an integrated 25 Ω series-damping resistor. Analog power supply. AV CC provides the power reference for the analog circuitry. In addition, AV CC can be used to bypass the PLL for test purposes. When AV CC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Clock input. CLK provides the clock signal to be distributed by the clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal Oct 19 3

4 MHz 1:9 clock driver FUNCTIONAL BLOCK DIAGRAM 1G Y0 1Y Y2 1Y3 1Y4 2G Y0 CLK FBIN PLL Y1 2Y2 2Y3 AV CC FBOUT SW pin SDR DIMM BACK SIDE FRONT SIDE A[L]VC A[L]VC A[L]VC The PLL clock distribution device and A[L]VC registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW Oct 19 4

5 MHz 1:9 clock driver ABSOLUTE MAXIMUM RATINGS 1 In accordance with the Absolute Maximum Rating System (IEC 134) LIMITS SYMBOL PARAMETER CONDITION MIN MAX UNIT AV CC Supply voltage range Note 2 < V CC V V CC Supply voltage range V I IK Input clamp current V I < 0 50 ma V I Input voltage range Note V I OK Output clamp current V O > V CC or V O < 0 ±50 ma V O Output voltage range Notes 3, V CC V I O DC output source or sink current V O = 0 to V CC ±50 ma T STG Storage temperature range C P TOT Power dissipation per package 700 mw NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. AV CC must not exceed V CC 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. This value is limited to 4.6 V maximum. RECOMMENDED OPERATING CONDITIONS 1 LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT V CC, AV CC Supply voltage V V IH HIGH level input voltage 2 V V IL LOW level input voltage 0.8 V V I Input voltage 0 V CC V T amb Operating ambient temperature range in free air C NOTE: 1. Unused inputs must be held high or low to prevent them from floating. ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise specified) TEST CONDITIONS LIMITS SYMBOL PARAMETER UNIT AV CC, V CC (V) OTHER MIN TYP MAX V IK Input clamp voltage 3 I I = 18mA 1.2 V MIN to MAX I OH = 100µA V CC 0.2 V OH HIGH level output voltage 3 I OH = 12mA 2.1 V 3 I OH = 6mA 2.4 MIN to MAX I OL = 100µA 0.2 V OL LOW level output voltage 3 I OL = 12mA 0.8 V 3 I OL = 6mA 0.55 I I Input current 3.6 V I = V CC or GND ±5 µa I CC Quiescent supply current 3.6 V I = V CC or GND; I O = 0, outputs: LOW or HIGH 10 µa I CCA AV CC power supply current AV CC = µa I CC Additional supply current per input pin 3.3 to 3.6 One input at V CC 0.6V; other inputs at V CC or GND 500 µa C I Input capacitance 3.3 V I = V CC or GND 2.8 pf C O Output capacitance 3.3 V O = V CC or GND 5.4 pf 1999 Oct 19 5

6 MHz 1:9 clock driver TIMING REQUIREMENTS Over recommended ranges of supply voltage and operating free-air temperature. SYMBOL PARAMETER MIN MAX UNIT f CLK Clock frequency MHz Input clock duty cycle % Stabilization time 1 1 ms NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. SWITCHING CHARACTERISTICS Over recommended ranges of supply voltage and operating free-air temperature, C L = 30 pf 1 PARAMETER FROM TO V CC, AV CC = 3.3 V ±0.3 V (INPUT)/CONDITION (OUTPUT) MIN TYP MAX UNIT t 2 phase error CLKIN = 100 MHz to 133 MHz CLKIN = 66 MHz FBIN ps ps t phase error, jitter 3 CLKIN = 100 MHz to 133 MHz FBIN ps t SK(0) 4 Any Y or FBOUT Any Y or FBOUT 200 ps jitter (peak-peak) CLKIN = 66 MHz to 133 MHz Any Y or FBOUT jitter (cycle-cycle) Duty cycle reference F(CLKIN > 60 MHz) Any Y or FBOUT % t r V O = 0.4 to 2 V Any Y or FBOUT V/ns t f V O = 0.4 to 2 V Any Y or FBOUT V/ns NOTES: 1. These parameters are not production tested. 2. This is considered as static phase error. 3. Phase error does not include jitter. (t phase error = static t phase error jitter (cycle-cycle) ). 4. The t SK(0) specification is only valid for equal loading of all outputs. 65 ps PARAMETER MEASUREMENT INFORMATION 3V INPUT t pe 50% V CC 0V FROM OUTPUT UNDER TEST 30pF 500Ω OUTPUT 2V 0.4V 50% V CC 2V 0.4V V OH V OL t r t f LOAD CIRCUIT FOR OUTPUTS VOLTAGE WAVEFORMS & PHASE ERROR TIMES NOTES: 1. C L includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 100MHz, Z O = 50Ω, t r 1.2ns, t f 1.2ns. 3. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms SW Oct 19 6

7 MHz 1:9 clock driver CLKIN FBIN t phase error FBOUT ANY Y t SK(0) ANY Y ANY Y t SK(0) Figure 2. Phase Error and Skew Calculations SW Oct 19 7

8 MHz 1:9 clock driver TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT Oct 19 8

9 MHz 1:9 clock driver NOTES 1999 Oct 19 9

10 MHz 1:9 clock driver Data sheet status Data sheet status Product status Definition [1] Objective specification Preliminary specification Product specification Development Qualification Production This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California Telephone Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: Document order number: Oct 19 10

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