利用VHDL設計乘法器

Size: px

Start display at page:

Download "利用VHDL設計乘法器"

帅尤
5 years ago
Views:

1 利用 VHDL 設計乘法器 Implement of Multiplier by Using VHDL 許地申 Dih-Shen Hsu 中華技術學院電機系副教授 Associate Professor Department of Electrical Engineering China Institute of Technology 摘要在計算機結構裡加, 減, 乘, 除是常被用到的運算, 本文提出以非常高速積體電路硬體描述語言 (VHDL) 來描述硬體, 說明如何將兩個運算元作相乘的運算我們首先以無號數整數做乘法運算來說明其原理, 設計其電路結構其實在 VHDL 程式中, 我們更可以載入 STD_LOGIC_ARITH 與 STD_LOGIC_UNSIGNED 元件盒之後, 直接進行乘法運算, 既簡單又容易擴充最後, 我們將以 4-bit X 4-bit 的例子來做電路描述電路合成電路模擬並以七段顯示器將其結果顯示出來關鍵字 : 非常高速積體電路硬體描述語言電路描述電路合成電路模擬 Abstract We have known operation that perform addition, subtraction, multiplication, and division. In this paper we are presented primarily to describe hardware using by VHDL. We can explain how multiplication may be performed for two operand. Multiplication of unsigned numbers illustrates the main issues involved in the design of multiplier circuit. In fact, after the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED packages were added to the VHDL program, it became not only simple but also easy to extended. Next, consider a 4 x 4 example to circuit description, circuit synthesis, and circuit simulation by using VHDL. Finally, this approach can also be displayed by 7-segment. Keyword : VHDL, circuit description, circuit synthesis, circuit simulation - 1 -

2 利用 VHDL 設計乘法器壹. 簡介 VHDL 是 Very High Speed Integrated Circuit Hardware Description Language 的英文縮寫是一種快速的電路設計工具, 功能涵蓋了電路描述電路合成電路模擬等三大電路設計工作 [4-8] VHDL 原來是由美國國防部於 70 年代開始研究發展的電路設計工具, 並於 1987 年成為 IEEE 的一種標準語言原先發展的目的是為了將電子電路的設計和其內部的含意, 用文件的方式儲存起來, 以便其他人能夠輕易地了解電路的設計意義這至少意味著兩種重大的改變 : 設計電路可以透過文字描述的方式, 完成設計工作電子電路也可以當作文件一樣來儲存從 VHDL 每年能夠以超過 30% 的速度快速成長便可以知道 VHDL 電路設計語言不但功能強大, 而且能夠滿足各個設計階層的設計工作, 從 ASIC 設計到 PCB 系統設計, 都能夠輕易地達成設計工作者的需求在產品更換快速的今天,VHDL 可以說是符合市場需求,VHDL 有以下之優點 : 功能強大設計靈活有各種不同的描述風格可流通性與可攜性本文將先就無號數整數乘法運算, 以四位元乘四位元作解說接著也可作有號數兩運算元之相乘 ; 其次, 載入 STD_LOGIC_ARITH 與 TD_LOGIC_UNSIGNED 元件盒之後, 直接進行乘法運算 ; 並以七段顯示器將其結果顯示出來貳. 乘法器基本原理兩個二進位數之相乘如十進位數相乘一樣於圖 1 為四位元做徒手乘法運算圖首先由右至左逐次檢查乘數位元是否為 1, 如為 1, 將被乘數做適當地移位至適當的位置 ; 如為 0, 將 0 放置適當位置其次將所有移位之被乘數求其和即為所得之積, 此積應為八位元圖 2 為乘法中硬體的運算情形 [1-3], 利用多重加法器來完成即每一步中一個四位元加法器可用來計算其新的部分乘積於計算進行時最不重要位元在連續加法中, 並不受到影響 ; 因此他們可直接放到最後之乘積中 - 2 -

3 multiplicand 1000 multiplier X product multiplicand 1000 multiplier X 1001 partial product partial product partial product product 圖 1. 徒手乘法圖 2. 乘法運算架構参. 乘法器製作概念現在我們可以運用最簡單且直觀的方式來完成所需要的硬體電路描述, 所以在往後的程式中我們使用 AND GATE 來做部分乘積的運算, 使用全加器來計算部分乘積的最後結果下面為全加器的布林代數式 : S = Cin A B Cout = Cin A + CinB + AB 其中,A B 分別代表兩個輸入運算元 ; 為前一個位元所作的加法進位,S 為相加後的結果 ; C 為相加後的進位, 也就是連接至下一個全加器的 C 這兩個 out 代數式是全加器中的內部運作, 透過全加器的運算能將所有的部分乘積相加, 以得到我們所要的乘積 C in in 經過上述乘法器原理之解説, 我們可以將電路架構用較直觀的方式表現出來, 如圖 3. 所示我們將部分乘積分別放到 PPXY 中, 例如 PP00, 即代表乘數中第 0 個位元, 和被乘數第 0 個位元作運算, 其結果放置 PP00, 其他都依此類推一個全加器有兩個輸出, 一個為 Sum, 另一個為 Cout 所以我們用 PSXY 來表示第 X 列的全加器運算出來的 Sum; 用 PCXY 來表示第 X 列的全加器運算出來的 Cout 必須注意的是上面三列的全加器是用來做部分乘積相加的, 而最底下的一組全加器是用來讓上一列之 PS 和 PC 的輸出, 做完最後運算之後, 再將結果傳送給 P0 至 P7 的 Product, 這就是最後的結果於是我們就可以直接用這架構圖和一些運算的方式, 利用 VHDL 來寫出乘法器的程式 - 3 -

4 利用 VHDL 設計乘法器 PP13 PP03 PP12 PP02 PP11 PP01 PP10 PP00 PP23 PP22 PP21 PP20 PP33 PP32 PP31 PP30 P7 P6 P5 P4 P3 P2 P1 P0 圖 3. 乘法器電路架構圖肆. 程式架構根據圖 3. 乘法器電路架構圖, 首先設計 4 X 4 乘法器程式架構如圖 4 其次, 如須擴充至 16 X 16 乘法器, 只須更改常數 N 的設定值如圖 5 我們更可以載入 STD_LOGIC_ARITH 與 STD_LOGIC_UNSIGNED 元件盒之後, 直接進行乘法運算, 既簡單又容易擴充圖 6. 為簡便 4 X 4 乘法器程式架構 ; 圖 7. 為七段顯示器程式架構 ; 圖 8. 為 4 X 4 乘法器且以七段顯示器顯示之程式架構 ; 圖 9. 簡便 16 X 16 乘法器程式架構 ; 圖 10. 帶符號之簡便 4 X 4 乘法器程式架構 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mult1_1 IS PORT ( a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - 4 -

5 prod : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END mult1_1; ARCHITECTURE mult1_arch OF mult1_1 IS CONSTANT n:integer :=4; SUBTYPE PART IS STD_LOGIC_VECTOR(n-1 DOWNTO 0); TYPE PARTS IS ARRAY(0 TO 4) OF PART; SIGNAL pp,pc,ps:parts; BEGIN pgen:for j IN 0 TO n-1 GENERATE pgen1:for k IN 0 TO n-1 GENERATE pp(j)(k)<=a(k) AND b(j); pc(0)(j)<='0'; pp(4)(3)<='0'; pp(4)(2)<='0'; pp(4)(1)<='0'; pp(4)(0)<='0'; ps(0)<=pp(0); prod(0)<=pp(0)(0); addr:for j IN 1 TO n-1 GENERATE addc:for k IN 0 TO n-2 GENERATE ps(j)(k)<=pp(j)(k) XOR pc(j-1)(k) XOR ps(j-1)(k+1); pc(j)(k)<=(pp(j)(k) AND pc(j-1)(k)) OR (pp(j)(k) AND ps(j-1)(k+1)) OR (pc(j-1)(k) AND ps(j-1)(k+1)); prod(j)<=ps(j)(0); ps(j)(n-1)<=pp(j)(n-1); pc(1)(3)<='0'; pc(2)(3)<='0'; pc(3)(3)<='0'; ps(4)(0)<='0'; - 5 -

6 利用 VHDL 設計乘法器 pc(n)(0)<='0'; addlast:for k IN 1 TO n-1 GENERATE ps(n)(k)<=pc(n)(k-1) XOR pc(n-1)(k-1) XOR ps(n-1)(k); pc(n)(k)<=(pc(n)(k-1) AND pc(n-1)(k-1)) OR (pc(n)(k-1) AND ps(n-1)(k)) OR (pc(n-1)(k-1) AND ps(n-1)(k)); prod(2*n-1)<=pc(n)(n-1); prod(2*n-2 DOWNTO n)<=ps(n)(n-1 DOWNTO 1); END mult1_arch; 圖 4. 4 X 4 乘法器程式架構 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mult1 IS PORT ( a,b : IN STD_LOGIC_VECTOR(15 DOWNTO 0); prod : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END mult1; ARCHITECTURE mult1_arch OF mult1 IS CONSTANT n:integer :=16; SUBTYPE PART IS STD_LOGIC_VECTOR(n-1 DOWNTO 0); TYPE PARTS IS ARRAY(0 TO 16) OF PART; SIGNAL pp,pc,ps:parts; BEGIN pgen:for j IN 0 TO n-1 GENERATE pgen1:for k IN 0 TO n-1 GENERATE pp(j)(k)<=a(k) AND b(j); pc(0)(j)<='0'; - 6 -

7 pp(16)(15)<='0'; pp(16)(14)<='0'; pp(16)(13)<='0'; pp(16)(12)<='0'; pp(16)(11)<='0'; pp(16)(10)<='0'; pp(16)(9)<='0'; pp(16)(8)<='0'; pp(16)(7)<='0'; pp(16)(6)<='0'; pp(16)(5)<='0'; pp(16)(4)<='0'; pp(16)(3)<='0'; pp(16)(2)<='0'; pp(16)(1)<='0'; pp(16)(0)<='0'; ps(0)<=pp(0); prod(0)<=pp(0)(0); addr:for j IN 1 TO n-1 GENERATE addc:for k IN 0 TO n-2 GENERATE ps(j)(k)<=pp(j)(k) XOR pc(j-1)(k) XOR ps(j-1)(k+1); pc(j)(k)<=(pp(j)(k) AND pc(j-1)(k)) OR (pp(j)(k) AND ps(j-1)(k+1)) OR (pc(j-1)(k) AND ps(j-1)(k+1)); prod(j)<=ps(j)(0); ps(j)(n-1)<=pp(j)(n-1); pc(1)(15)<='0'; pc(2)(15)<='0'; pc(3)(15)<='0'; pc(4)(15)<='0'; pc(5)(15)<='0'; pc(6)(15)<='0'; pc(7)(15)<='0'; - 7 -

8 利用 VHDL 設計乘法器 pc(8)(15)<='0'; pc(9)(15)<='0'; pc(10)(15)<='0'; pc(11)(15)<='0'; pc(12)(15)<='0'; pc(13)(15)<='0'; pc(14)(15)<='0'; pc(15)(15)<='0'; ps(16)(0)<='0'; pc(n)(0)<='0'; addlast:for k IN 1 TO n-1 GENERATE ps(n)(k)<=pc(n)(k-1) XOR pc(n-1)(k-1) XOR ps(n-1)(k); pc(n)(k)<=(pc(n)(k-1) AND pc(n-1)(k-1)) OR (pc(n)(k-1) AND ps(n-1)(k)) OR (pc(n-1)(k-1) AND ps(n-1)(k)); prod(2*n-1)<=pc(n)(n-1); prod(2*n-2 DOWNTO n)<=ps(n)(n-1 DOWNTO 1); END mult1_arch; 圖 X 16 乘法器程式架構 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY T3 IS PORT ( a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END T3; ARCHITECTURE arch OF T3 IS BEGIN y(7 DOWNTO 0) <= a(3 DOWNTO 0)*b(3 DOWNTO 0); END arch; - 8 -

9 圖 6. 簡便 4 X 4 乘法器程式架構 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SVN_DISP IS PORT (Y:IN STD_LOGIC_VECTOR(7 DOWNTO 0); a,b,c,d,e,f,g,a1,b1,c1,d1,e1,f1,g1,a2,b2,c2,d2,e2,f2,g2: OUT STD_LOGIC ); END SVN_DISP; ARCHITECTURE A OF SVN_DISP IS SIGNAL OUTPUT : STD_LOGIC_VECTOR(20 DOWNTO 0); SIGNAL I : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN I(7 DOWNTO 0) <= Y; PROCESS(I) BEGIN CASE I IS WHEN " " => OUTPUT <= " ";--0 WHEN " " => OUTPUT <= " ";--1 WHEN " " => OUTPUT <= " ";--2 WHEN " " => OUTPUT <= " ";--3 WHEN " " => OUTPUT <= " ";--4 WHEN " " => OUTPUT <= " ";--5 WHEN " " => OUTPUT <= " ";--6 WHEN " " => OUTPUT <= " ";--7 WHEN " " => OUTPUT <= " ";--8 WHEN " " => OUTPUT <= " ";--9 WHEN " " => OUTPUT <= " ";--10 WHEN " " => OUTPUT <= " ";--11 WHEN " " => OUTPUT <= " ";--12 WHEN " " => OUTPUT <= " ";--13 WHEN " " => OUTPUT <= " ";--14 WHEN " " => OUTPUT <= " ";

10 利用 VHDL 設計乘法器 WHEN " " => OUTPUT <= " ";--16 WHEN " " => OUTPUT <= " ";--18 WHEN " " => OUTPUT <= " ";--20 WHEN " " => OUTPUT <= " ";--21 WHEN " " => OUTPUT <= " ";--22 WHEN " " => OUTPUT <= " ";--24 WHEN " " => OUTPUT <= " ";--25 WHEN " " => OUTPUT <= " ";--26 WHEN " " => OUTPUT <= " ";--27 WHEN " " => OUTPUT <= " ";--28 WHEN " " => OUTPUT <= " ";--30 WHEN " " => OUTPUT <= " ";--32 WHEN " " => OUTPUT <= " ";--33 WHEN " " => OUTPUT <= " ";--35 WHEN " " => OUTPUT <= " ";--36 WHEN " " => OUTPUT <= " ";--39 WHEN " " => OUTPUT <= " ";--40 WHEN " " => OUTPUT <= " ";--42 WHEN " " => OUTPUT <= " ";--44 WHEN " " => OUTPUT <= " ";--45 WHEN " " => OUTPUT <= " ";--48 WHEN " " => OUTPUT <= " ";--49 WHEN " " => OUTPUT <= " ";--50 WHEN " " => OUTPUT <= " ";--52 WHEN " " => OUTPUT <= " ";--54 WHEN " " => OUTPUT <= " ";--55 WHEN " " => OUTPUT <= " ";--56 WHEN " " => OUTPUT <= " ";--60 WHEN " " => OUTPUT <= " ";--63 WHEN " " => OUTPUT <= " ";--64 WHEN " " => OUTPUT <= " ";--65 WHEN " " => OUTPUT <= " ";--66 WHEN " " => OUTPUT <= " ";--70 WHEN " " => OUTPUT <= " ";

11 WHEN " " => OUTPUT <= " ";--75 WHEN " " => OUTPUT <= " ";--77 WHEN " " => OUTPUT <= " ";--78 WHEN " " => OUTPUT <= " ";--80 WHEN " " => OUTPUT <= " ";--81 WHEN " " => OUTPUT <= " ";--84 WHEN " " => OUTPUT <= " ";--88 WHEN " " => OUTPUT <= " ";--90 WHEN " " => OUTPUT <= " ";--96 WHEN " " => OUTPUT <= " ";--98 WHEN " " => OUTPUT <= " ";--99 WHEN " " => OUTPUT <= " ";--100 WHEN " " => OUTPUT <= " ";--105 WHEN " " => OUTPUT <= " ";--104 WHEN " " => OUTPUT <= " ";--108 WHEN " " => OUTPUT <= " ";--110 WHEN " " => OUTPUT <= " ";--112 WHEN " " => OUTPUT <= " ";--117 WHEN " " => OUTPUT <= " ";--120 WHEN " " => OUTPUT <= " ";--121 WHEN " " => OUTPUT <= " ";--126 WHEN " " => OUTPUT <= " ";--130 WHEN " " => OUTPUT <= " ";--132 WHEN " " => OUTPUT <= " ";--135 WHEN " " => OUTPUT <= " ";--140 WHEN " " => OUTPUT <= " ";--143 WHEN " " => OUTPUT <= " ";--150 WHEN " " => OUTPUT <= " ";--154 WHEN " " => OUTPUT <= " ";--156 WHEN " " => OUTPUT <= " ";--165 WHEN " " => OUTPUT <= " ";--168 WHEN " " => OUTPUT <= " ";--180 WHEN " " => OUTPUT <= " ";--182 WHEN " " => OUTPUT <= " ";

12 利用 VHDL 設計乘法器 WHEN " " => OUTPUT <= " ";--196 WHEN " " => OUTPUT <= " ";--210 WHEN " " => OUTPUT <= " ";--225 WHEN OTHERS => NULL;--NO_WORK END CASE; END PROCESS; a <= OUTPUT(20); b <= OUTPUT(19); c <= OUTPUT(18); d <= OUTPUT(17); e <= OUTPUT(16); f <= OUTPUT(15); g <= OUTPUT(14); a1 <= OUTPUT(13); b1 <= OUTPUT(12); c1 <= OUTPUT(11); d1 <= OUTPUT(10); e1 <= OUTPUT(9); f1 <= OUTPUT(8); g1 <= OUTPUT(7); a2 <= OUTPUT(6); b2 <= OUTPUT(5); c2 <= OUTPUT(4); d2 <= OUTPUT(3); e2 <= OUTPUT(2); f2 <= OUTPUT(1); g2 <= OUTPUT(0); END A; 圖 7. 七段顯示器程式架構 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY B4MUL_1 IS

13 PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); l,m,n,o,p,q,r,l1,m1,n1,o1,p1,q1,r1,l2,m2,n2,o2,p2,q2,r2:out STD_LOGIC ); END B4MUL_1; ARCHITECTURE A OF B4MUL_1 IS COMPONENT T3 PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Y :OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT SVN_DISP PORT(Y:IN STD_LOGIC_VECTOR(7 DOWNTO 0); a,b,c,d,e,f,g,a1,b1,c1,d1,e1,f1,g1,a2,b2,c2,d2,e2,f2,g2:out STD_LOGIC ); END COMPONENT; SIGNAL I :STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN U1 : T3 PORT MAP(A,B,I); U2 : SVN_DISP PORT MAP(I,l,m,n,o,p,q,r,l1,m1,n1,o1,p1,q1,r1,l2,m2,n2,o2,p2,q2,r2); END A; 圖 8. 4 X 4 乘法器且以七段顯示器顯示之程式架構 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY T2 IS PORT ( a,b : IN STD_LOGIC_VECTOR(15 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );END T2; ARCHITECTURE arch OF T2 IS BEGIN

14 利用 VHDL 設計乘法器 y(31 DOWNTO 0) <= a(15 DOWNTO 0)*B(15 DOWNTO 0); END ARCH; 圖 9. 簡便 16 X 16 乘法器程式架構 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY T1 IS PORT ( a,b : IN STD_LOGIC_VECTOR(4 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) );END T1; ARCHITECTURE arch OF T1 IS BEGIN y(7 DOWNTO 0) <= a(3 DOWNTO 0)*b(3 DOWNTO 0); y(8) <= a(4) XOR b(4); END arch; 圖 10. 帶符號之簡便 4 X 4 乘法器程式架構伍. 模擬計算接下來我們使用 Altera 來模擬計算, 圖 11. 為圖 5 中 16 X 16 乘法器之模擬圖 ; 圖 12. 為圖 4 中 4 X 4 乘法器模擬圖 ; 圖 13. 為圖 6 中簡便 4 X 4 乘法器模擬圖 ; 圖 14. 為圖 9 中簡便 16 X 16 乘法器模擬圖 ; 圖 15. 為圖 10 中帶符號之簡便 4 X 4 乘法器模擬圖 ; 圖 16. 為圖 8 中 4 X 4 乘法器且以七段顯示器顯示模擬圖由以上的這些圖可知其結果是正確的

15 圖 11. 圖 5 中 16 X 16 乘法器之模擬圖圖 12. 圖 4 中 4 X 4 乘法器模擬圖圖 13. 圖 6 中簡便 4 X 4 乘法器模擬圖

16 利用 VHDL 設計乘法器圖 14. 圖 9 中簡便 16 X 16 乘法器模擬圖圖 15. 圖 10 中帶符號之簡便 4 X 4 乘法器模擬圖圖 16. 圖 8 中 4 X 4 乘法器且以七段顯示器顯示模擬圖

17 陸. 結論 VHDL 對於電路的設計可以從很高階的方式寫起, 也可從低階的方式, 像是電路圖 ( 即 schematics), 也可以完成我們所需的工作, 但電路太複雜時就不適宜在位元數少之兩運算元相乘的乘法器, 先寫出其布林方程式, 其次利用 VHDL 程式寫法使用基本邏輯運算子將布林方程式描述出來 ; 也可用類似徒手相乘之乘法器結構利用 VHDL 程式寫法如圖 4 及圖 5 但位元數增加時兩運算元相乘的乘法器即顯得更複雜, 可用載入 STD_LOGIC_ARITH 與 STD_LOGIC_UNSIGNED 元件盒之後, 直接進行乘法運算如圖 6 及圖 9, 所得答案是一樣的由此可看出其為既清爽又容易擴充參考文獻 1. V.C. Hamacher, Z.G. Vranesic and S.G. Zaky, Computer Organization, 4 th ed. (McGraw-Hill: New York, 1966.) 2. D.A. Patterson and J.L. Hennessy, Computer Organization and Design-The Hardware/Software Interface, 2 nd ed. (Morgan Kaufmann: San Farncisco, CA, 1998). 3. S. Brown, Z.Vranesic, Fundamentals of Digital Logic with VHDL Design, ( McGraw-Hill: New York,2000.) 4. 黃孝祖, 鄭光欽, CPLD 與 VHDL 設計實務, 全威圖書股份有限公司, 胡振華, VHDL 與 FPGA 設計, 全華科技圖書股份有限公司, 盧毅, 賴杰, VHDL 與數位電路設計, 文魁資訊股份有限公司, 蕭如宣, VHDL 數位電路設計, 儒林圖書股份有限公司, 王國權, 賴清羽, VHDL 晶片設計, 宏友圖書開發股份有限公司,

a b c d e f g C2 C1 2

a b c d e f g C2 C1 2 IN1 IN2 0 2 to 1 Mux 1 IN1 IN2 0 2 to 1 Mux 1 Sel= 0 M0 High C2 C1 Sel= 1 M0 Low C2 C1 1 to 2 decoder M1 Low 1 to 2 decoder M1 High 3 BCD 1Hz clk 64Hz BCD 4 4 0 1 2 to 1 Mux sel 4