行 精 類 行 年 年 行 立 林 參 理 理 年
|
|
|
- 墨 荣
- 4 years ago
- Views:
Transcription
1 行 精 類 行 年 年 行 立 林 參 理 理 年
2 USB OTG USB The Design and Implementation of a USB OTG Chip and USB Speaker System NSC 222 E ( ) 96
3 USB OTG 997 PC USB (Universal Serial Bus) USB PC USB OTG (On-the-Go) USB USB 2. USB PC USB OTG USB (Dual-role Device) HNP (Host Negotiation Protocol) SRP (Session Request Protocol) USB (Host) (Peripheral) USB. OTG IP USB. I 2 C bus (Inter IC-bus) UTMI+ ( UTMI extension supporting On-The-Go) OTG IP FPGA Apex 2K4EBC-X TSMC.35um 2P4M USB. USB2. OTG UTMI+ IIC Abstract PCs have been equipped with USB (Universal Serial Bus) since 997. Recently, USB has become a plug-and-play interface between added-on devices and computers. USB OTG (On-The-Go) is a new supplement to the USB 2. specification that augments capability of existing mobile devices and USB peripherals by adding host functionality from connecting to USB peripherals. In addition, USB OTG improves the original USB architecture to perform the point-to-point transportation and adds the device of dual-role with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol) to be able dynamically to switch between host and peripheral. In this project, we plan to design and implement a USB USB. OTG IP and chip, which equips USB. controller, OTG controller, I 2 C bus (Inter IC-bus) and UTMI+ (UTMI extension supporting On-The-Go). The result IP will be verified by FPGA (Apex 2K4EBC-X) and then synthesized by using TSMC.35um 2P4M cell library for manufacturing a prototyping chip. Keyword USB., USB2., OTG, UTMI+, I 2 C, (Verilog HDL). 2
4 98 IBM USB (Universal Serial Bus) Intel 2 Mbps 995 USB-IF (USB Implementers forum) USB USB. 2 Mbps USB USB Mbps 4 USB 2. USB. USB2. USB. USB USB (Master/slave system) (PC) USB-IF 2 2 USB 2. On-The-Go (OTG) (Dual-role Device) HNP (Host Negotiation Protocol) SRP (Session Request Protocol) USB (Host) (Peripheral) OTG (low power consumption) (low cost) USB OTG USB USB USB. USB. SIE (Serial Interface Engine) I 2 C USB. control UTMI (USB 2. Transceiver Macrocell Interface) OTG USB. OTG USB (transaction) (packet transmission) (type of transaction) (endpoint address) USB USB (Frame) SOF (Start of Frame) USB. : (Low speed) 5 Mbps (Full speed) 2 Mbps USB. USB USB Mbps USB 2. USB. USB 2. (Micro Frame) USB OTG (mimi) USB ID ID A-device B-device USB OTG Transceiver Philips ISP3 ISP3 I 2 C I 2 C (I 2 C Master) ISP3 USB OTG USB OTG USB OTG SRP USB OTG V BUS (Session) USB OTG HNP V BUS USB OTG USB SRP HNP USB 3
5 (Host) (Device) OTG USB OTG (Verilog HDL) USB OTG USB. USB OTG USB OTG IP i2c interface USB OTG USB Cable D+/D- i2c protocol ISP 3 PHY I2c Master Control Source & Status Register (OTG relative) Control Register A or B OTG FSM Bus Interface MCU Serial data Tx/Rx PHY Interface USB Protocol TX/RX FIFO. USB OTG 2 (parallel to serial) NRZI SYNC EOP (output enable logic) SYNC NRZI (serial to parallel) (clock generator) 48 MHz USB / 4
6 Physical Layer RX Input Synchronizer K/J/SE Change Detect Clock Generator SYNC Pattern Finder NRZI Decoder Bit Stuff Detect S2P Converter EOP TX NRZI Encoder P2S Converter Output Enable Logic EOP Append Logic SYNC Pattern Append FSM Bit Stuffer 2. USB USB Protocol USB 3 PA PD PE IDMA PD CRC PE PE IDMA FIFO FIFO PA PA CRC PD PE PA IDMA 3. 4 ASM chart 5
7 tx_first <= 'b tx_valid <= 'b tx_data = {~SOF, SOF} crc5_din <= frame_no; SOF_ tx_first <= 'b tx_valid <= 'b tx_data <= frame_no[7:] tx_ready SOF_ tx_valid <= 'b tx_last <= 'b; tx_data <= {CRC5[:4],frame_no[:8]} tx_ready tx_last <= 'b sof_active_reset <= 'b tx_first <= 'b tx_valid <= 'b tx_last <= 'b sof_active active tx_valid <= 'b tx_last <= 'b; tx_data <= {crc5[:4], endpoint[2:]} TOKEN_2 OUT/SETUP IDLE toggle_err <= active_reset <= 'b sof_active_reset <= 'b TOKEN tx_first <= 'b tx_valid <= 'b tx_data <= {endpoint[3], USBAddr} TOKEN_ tx_ready tx_ready TOKEN_3 crc6_clr <= 'b bus_idle pid IN tx_first <= 'b tx_valid <= 'b tx_data = {~pid, pid} crc5_din <= {USBAddr, endpoint} tx_last <= 'b bus_idle RETURN active_reset <= 'b sof_active_reset <= 'b tx_first <= 'b tx_last <= 'b crc6_clr <= 'b active_reset <= 'b pid SETUP IN_ data_toggle <= tx_data <= {~DATA, DATA} OUT data_toggle OUT_ tx_first <= 'b tx_valid <= 'b crc6_din = buffer_out[:7] data_toggle <= tx_data <= {~DATA, DATA} rx_active & rx_valid buffer_empty data_toggle tx_ready buffer_re = 'b crc6_update = 'b tx_data <= buffer_out OUT_ buffer_re = 'b crc6_update = 'b crc6_din = buffer_out[:7] crc6_update = 'b tx_data <= ~crc6[:7] CRC_ CRC_ tx_ready tx_valid <= 'b tx_last <= 'b tx_data <= ~crc6[8:5] toggle_err <= 'b Pid_DATA buffer_wr = 'b crc6_update = 'b buffer_wr = 'b crc6_update = 'b data_toggle <= ~data_toggle IN_ crc6_din = rx_data[:7] rx_active rx_valid Pid_DATA buffer_wr = 'b tx_first <= 'b tx_last <= 'b toggle _err CRC6_err toggle_err <= 'b tx_data <= ACK tx_data <= NACK tx_last <= 'b tx_ready Pid=OUT & iso ACK_O tx_first <= 'b ACK_I ACK_valid 4. 6
8 5 USB OTG FIFO TX RX 52 8 FIFO FIFO Bus Interface (Endpoint) (Host) FIFO TX control FIFO TX control FIFO 2 TX control FIFO 3 TX control SRAM for TX FIFO RX control FIFO RX control FIFO 2 RX control FIFO 3 RX control SRAM for RX 5. FIFO I 2 C Master ISP3 ISP3 6 I 2 C Master I 2 C Master reg_address reg_data ISP3 write read I 2 C sda (Serial Data Line) scl (Serial Data Line) PHY i2c_data_rdy 7 I 2 C IDLE Start_wr ACK OTG I 2 C Master address 5b ISP3 reg_addr i2c_data OTG reg_data I 2 C sda scl ISP3 Stop clk rst_n sda_i write read reg_addr[7:] reg_data[7:] I2C_ Master_ CTRL sda_oen scl_oen i2c_data[7:] i2c_data_rdy clk_k 6. I 2 C 7
9 Ssubaddr >=9'h58 rst= IDLE I2c_stop/ Stop wr_end Ssubaddr < 9'h58 slave_ack/ Start_ wr wr_end & slave_ack / sta_end slave_ack/ wr_end & slave_ac k RegData _rd DevAdr _rd wr_end& slave_ack/ RegData _rd slave_ack DevAdr _ wr wr_end & slave_ack sta_end Start_ rd RegAdr _wr wr_end&slave_ack 7. I 2 C USB OTG OTG OTG OTG USB OTG ID USB 8 USB OTG USB OTG A B OTG I 2 C A a_bus_req a_set_b_hnp_en SRP HNP 9 A a_bus_req A_wait USB b_conn B A Host Suspend A a_hnp B b_conn Peripheral A loc_conn A B A_Idle B b_bus_req b_hnp_en SRP HNP 9 B b_bus_req B B_wait SRP b_sess_vld B Peripheral B HNP b_hnp A b_conn A a_conn B A Host B B_Idle USB OTG USB OTG OTG I 2 C ISP3 USB OTG USB OTG ISP3 USB SIE SOF USB. 8
10 8. USB OTG a_wait_fall drv_vbus/ id a_bus_drop a_aidl_bdis_tmout id a_bus_req (b_conn/ & a_sess_vld/) id a_bus_drop a_peripheral drv_vbus loc_conn b_conn/ & a_set_b_hnp_en/ a_suspend drv_vbus id a_bus_drop a_vbus_vld/ a_vbus_vld/ a_idle drv_vbus / chrg_vbus/ id a_bus_drop a_wait_bcon_tmout b_bus_suspend a_vbus_err drv_vbus/ b_conn/ & a_set_b_hnp_en/ a_bus_req b_bus_resume a_bus_req/ a_suspend_req a_bus_drop/ & (a_bus_req a_srp_det ) a_vbus_vld/ a_vbus_vld/ a_wait_vrise drv_vbus a_host drv_vbus loc_sof id a_bus_drop a_vbus_vld a_wait_vrise_tmout a_wait_bcon drv_vbus id b_conn/ a_bus_drop b_conn b_host drv_vbus/ loc_sof id/ b_sess_vld/ b_conn/ & a_set_b_hnp_en id/ b_sess_vld/ b_wait_bcon drv_vbus/ 9. OTG b_idle drv_vbus/ chrg_vbus/ b_bus_req/ a_conn/ b_bus_req & b_sess_end & b_se_srp id/ b_srp_done b_sess_vld id/ b_sess_vld/ a_bus_resume b_ase_brst_tmout b_bus_req & b_hnp_en & a_bus_suspend b_idle pulse chrg_vbus pulse loc_conn ASIC (CIC) cell based IC design b_peripheral CIC TSMC.8 µm P6M cell library Synopsys Design Compiler scan chain Scan chain Synopsys DFT compiler scan chain TetraMAX patterns USB OTG RAM BIST Syntest BIST (layout) Cadence SOC Encounter DRC/ERC LVS Calibra Verilog-XL I2C USB OTG I2C ISP3 OTG USB SETUP IN IN packets 2 OTG I2C ISP3 9 drv_vbus/ loc_conn
11 . I 2 C. USB 2. OTG
12 Technology.8um P6M Package LCC 68 Max. frequency MHz Power dissipation 5. mw Total 68 Input 28 Pin count Output 24 IO Power 8 Core Power 8 Die size (with DFT; without I/O pad) mm 2 Chip size (with DFT and I/O pad) mm 2 2 [] ISP3; USB OTG Transceiver, Rev.. [Online]. Available: semiconductors.philips.com/ [2] Low Pin Count Supplement to the UTMI+ Spec., Rev..6. [Online]. Available: [3] On-The-Go Supplement to the USB 2. Spec., Rev..a. [Online]. Available: [4] USB Spec., Rev. 2.. [Online]. Available: [5] USB 2. Transceiver Macrocell Interface Spec., Rev..5 [Online]. Available: [6] UTMI+ Spec., Rev..9. [Online]. Available: [7] The I2C-Bus Spec., Rev 2.. [Online]. Available: philips.com [8] USB 26 [9] USB2. Cypress Corporation, Kosta Koeman, Stuart Allman 22 [] USB 998 CIC CAD TSMC.8 µm P6M cell library
13 USB OTG USB. I 2 C bus (Inter IC-bus) UTMI+ ( UTMI extension supporting On-The-Go) OTG TSMC.8um 2P8M USB transceiver USB. USB OTG. USB 2. IP USB 2. USB transceiver 2. USB OTG 2
14 96 2 USB OTG USB NSC E--49 USB OTG USB. OTG IP USB. I 2 C bus (Inter IC-bus) UTMI+ ( UTMI extension supporting On-The-Go) OTG MP3 In this project, a USB. OTG IP is designed and verified. The IP includes a USB.controller, an I 2 C bus (Inter IC-bus) controller, a UTMI+ (UTMI extension supporting On-The-Go) module, and an OTG controller. It is targeted for MP3player applications. MP3 USB. OTG USB OTG MP3 3
FPGA GJVZsIPb3 IPb3pg(lwE & by2eh;[d)y IP ROM
FPGA IPb3pg(lwE & by2eh;[d)y IP ROM NVMe SSD FPGA!! NVMe-IP 32G bps Gen3 x 4Lane IP CPUNVMe PCIe SSD 4GB/sec, PCIe Gen3 2ch RAID CPU FAT32 SMART, Shutdown, FLUSH!! Linux Gen3 PCIe SSD 2ch RAID 2ch RAID
Xilinx Alliance Program Certified GJVZsIPb3 IPb3pg(lwE & by2eh;[d)y IP ROM
Xilinx Alliance Program Certified IPb3pg(lwE & by2eh;[d)y IP ROM NVMe SSD FPGA!! NVMe-IP 32G bps Gen3 x 4Lane IP CPUNVMe PCIe SSD 4GB/sec, PCIe Gen3 2ch RAID CPU FAT32 PLDAPCIe Soft IP!! Linux Gen3 PCIe
Huawei Technologies Co
Testbench Preliminary itator 1 TESTBENCH... 3 2 TESTBENCH... 3 2.1 Testbench... 3 2.2... 4 2.2.1 HDL... 4 2.2.2... 5 2.2.3 PLI... 5 2.3... 6 2.4... 6 2.4.1... 6 2.4.2... 7 3 TESTBENCH... 9 3.1 2-4... 9
USB - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - DES Module FSM CONTROLLER 8 6 8 Key ROM 8 8 Data_in RAM Data_out RAM 8 USB Board - 8 - - 9 - - 10 - - 11 - - 12 - USB device INF Windows INF Device Function
附件1：
2013 年 增 列 硕 士 专 业 学 位 授 权 点 申 请 表 硕 士 专 业 学 位 类 别 ( 工 程 领 域 ): 工 程 ( 集 成 电 路 工 程 ) 申 报 单 位 名 称 : 南 开 大 学 国 务 院 学 位 委 员 会 办 公 室 制 表 2013 年 12 月 18 日 填 一 申 请 增 列 硕 士 专 业 学 位 授 权 点 论 证 报 告 集 成 电 路 产 业 是
MICROCHIP EVM Board : APP APP001 PICmicro Microchip APP001 40pin PDIP PICmicro Design Tips Character LCM Temperature Sensor Application I/O Pi
MICROCHIP EVM Board : APP001 1-1. APP001 PICmicro Microchip APP001 40pin PDIP PICmicro Design Tips Character LCM Temperature Sensor Application I/O Pin 16 I/O Extension Interface 1-2. APP001 Block_A Block_B
7-1
USB 說 列 流 USB PXA250 PXA210 理 數 類 Megacell / FIFO USB 識 率 列 流 UDC USB host USB 說 參 Universal Serial Bus Specification, revision 1.1 http://www.usb.org 列 流 Universal Serial Bus USB 流 12Mbps 率 USB 連 連 127
USB解决方案.ppt
USB USB? RS232 USB USB HID U modem ADSL cable modem IrDA Silabs USB CP210x USB UART USB RS-232 USB MCU 15 USB 12 FLASH MCU 3 USB MCU USB MCU C8051F32x 10 ADC 1.5%, Vref CPU 25MIPS 8051 16KB Flash -AMUX
Microsoft Word - A200911-255.doc
硅 片 调 谐 器 (TUNER) 在 PC-TV 上 的 应 用 高 云 北 京 歌 华 有 线 电 视 网 络 股 份 有 限 公 司, 北 京 (100007) E-mail:gaoyun@bgctv.com.cn 摘 要 : 本 文 介 绍 一 款 USB 接 口 的 A+D 电 视 接 收 盒 的 设 计, 该 设 计 采 用 小 尺 寸 的 硅 片 TUNER 与 EM2880 芯 片
混訊設計流程_04.PDF
CIC Referenced Flow for Mixed-signal IC Design Version 1.0 (Date) (Description) (Version) V. 1.0 2010/11/ Abstract CIC IC (Mixed-signal Design Flow) IC (Front End) (Back End) Function Timing Power DRC
Embargoed until May 4, 2004 EXPRESS 40 NI HQ 3000 1000 5000 ~ 500 10% / 500 85% NI LabVIEW 7 Express Express EXPRESS : #1 GPS Navigation PC/WWW/Email CD+RW Mobile Phone PDA DVD+RW Satellite Car Alarm/Radio
1 1
1 1 2 Idea Architecture Design IC Fabrication Wafer (hundreds of dies) Sawing & Packaging Block diagram Final chips Circuit & Layout Design Testing Layout Bad chips Good chips customers 3 2 4 IC Fabless
ATMEL AT90S8515 AVR CPU AVR AVR AVR ATMEL RISC 32 8 r0 r X Y Z R0 R1 R2 R13 R14 R15 R16 R17 R26 R27 R28 R29 R30 R31 0x00 0x
115 AVR W.V. Awdrey ATMEL AVR PIC AVR PIC AVR RISC AVR PIC AVR AVR AVR AVR AVR ATtiny15 AVR AVR AVR RAM ROM 121 116 122 ATMEL AT90S8515 AVR CPU AVR AVR AVR ATMEL RISC 32 8 r0 r31 3 16 X Y Z 6-1 118 7 0
enews174_2
103 CMOS Seal-Ring 104 e-learning 104 104 / http://www.cic.org.tw/login/login.jsp CIC Introduction to Conversational French - Syllabus Summer 2004 1 4 21 CMOS MorSensor MorFPGA DUO 2 MorSensor 3 103 (
OSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Prot
OSI OSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Protocol OSI OSI OSI OSI OSI O S I 2-1 Application
PTS7_Manual.PDF
User Manual Soliton Technologies CO., LTD www.soliton.com.tw - PCI V2.2. - PCI 32-bit / 33MHz * 2 - Zero Skew CLK Signal Generator. - (each Slot). -. - PCI. - Hot-Swap - DOS, Windows 98/2000/XP, Linux
Bus Hound 5
Bus Hound 5.0 ( 1.0) 21IC 2007 7 BusHound perisoft PC hound Bus Hound 6.0 5.0 5.0 Bus Hound, IDE SCSI USB 1394 DVD Windows9X,WindowsMe,NT4.0,2000,2003,XP XP IRP Html ZIP SCSI sense USB Bus Hound 1 Bus
9 什 么 是 竞 争 与 冒 险 现 象? 怎 样 判 断? 如 何 消 除?( 汉 王 笔 试 ) 在 组 合 逻 辑 中, 由 于 门 的 输 入 信 号 通 路 中 经 过 了 不 同 的 延 时, 导 致 到 达 该 门 的 时 间 不 一 致 叫 竞 争 产 生 毛 刺 叫 冒 险 如
FPGA 工 程 师 面 试 试 题 一 1 同 步 电 路 和 异 步 电 路 的 区 别 是 什 么?( 仕 兰 微 电 子 ) 2 什 么 是 同 步 逻 辑 和 异 步 逻 辑?( 汉 王 笔 试 ) 同 步 逻 辑 是 时 钟 之 间 有 固 定 的 因 果 关 系 异 步 逻 辑 是 各 时 钟 之 间 没 有 固 定 的 因 果 关 系 3 什 么 是 " 线 与 " 逻 辑, 要 实
Tel:010-62981668-2930 1
Access 93C46 with SPI function V1.0.0 Jan. 31, 2005 http://www.sunplusmcu.com Tel:010-62981668-2930 http://www.sunplusmcu.com E-mail:mcu@sunplus.com.cn 1 0 0...2 1...3 2...4 2.1...4 2.2...5 3...6 3.1 AT93C46...6
逢 甲 大 學
益 老 年 不 易更 例 不 異 列 - I - 錄 錄 流 錄 六 來 錄 - II - 錄 錄 錄 錄 錄 錄 參 料 錄 - III - 料 讀 讀 錄 讀 數 錄 錄 錄 錄 錄 - IV - 錄 錄 行 錄 錄 錄 錄 讀 錄 錄 錄 讀 錄 錄 - V - 了 說 力 兩 了 - 1 - 列 邏 路 列 不 不 FLEX 10K Devices at a Glance Feature
P4i45GL_GV-R50-CN.p65
1 Main Advanced Security Power Boot Exit System Date System Time Floppy Drives IDE Devices BIOS Version Processor Type Processor Speed Cache Size Microcode Update Total Memory DDR1 DDR2 Dec 18 2003 Thu
audiogram3 Owners Manual
USB AUDIO INTERFACE ZH 2 AUDIOGRAM 3 ( ) * Yamaha USB Yamaha USB ( ) ( ) USB Yamaha (5)-10 1/2 AUDIOGRAM 3 3 MIC / INST (XLR ) (IEC60268 ): 1 2 (+) 3 (-) 2 1 3 Yamaha USB Yamaha Yamaha Steinberg Media
热设计网
例 例 Agenda Popular Simulation software in PC industry * CFD software -- Flotherm * Advantage of Flotherm Flotherm apply to Cooler design * How to build up the model * Optimal parameter in cooler design
12 Differential Low-Power 6x6 12 bit multiply 1
12 Differential Low-Power 6x6 12 bit multiply 1 2 07 1.1 07 1.2 07 1.2.1 (Sequential Structure Multiplier )07 1.2.2 (Array Structure Multiplier) 09 1.2.3 (Parallel Multiplier) 10 1.2.3.1 10 1.2.3.2 10
100Mbps 100Mbps 1000Mbps 100Mbps 1000Mbps 100Mbps 100Mbps PD LXT Mbps 100Mbps 100Mbps 1
1 3 6 6 7 100BASE-FX 10 100Mbps 13 13 21143-PD 14 LXT970 20 Serial ROM 24 Boot ROM 24 Agilent 25 100Mbps 27 27 37 100Mbps 45 50 54 55 100Mbps 100Mbps 1000Mbps 100Mbps 1000Mbps 100Mbps 100Mbps 21143-PD
工程师培训
.1 TCP/IP TCP/IP 1 .2.2.1 Host 1960 S 1970 S Host Low Speed Lines 1970 S 1980 S pc Server Local Interneting 1980 S 1990 S Branch. pc Branch. WAN Branch. pc pc IBM SNA IBM X.25 2 .2.2 OSI OSI Application
Microsoft Word - 32
* 基 于 Nios II 处 理 器 的 USB 接 口 设 计 * 项 目 基 金 : 获 中 韩 合 作 项 目 Development of Embedded Software and System for Automobile Electronics 的 资 助 ; 重 庆 市 科 技 攻 关 计 划 项 目 面 向 汽 车 ABS 嵌 入 式 系 统 的 专 用 开 发 平 台 及 其
VioCard-300 user manual
VioGate VioCard-300 ( 2.0.0) 2005 2005 2 15 2 3 VioGate 绍... 6 1.1 产 简... 6 1.2 产... 6 1.3... 7 1.4 内... 7 1.5 导览... 8 VioGate... 10 2.1 VioGate 络 认...10 2.2 VioGate...11 软... 16 3.1 VioCard-300 盘...16
P4V88+_BIOS_CN.p65
1 Main H/W Monitor Boot Security Exit System Overview System Time System Date [ 17:00:09] [Wed 12/22/2004] BIOS Version : P4V88+ BIOS P1.00 Processor Type : Intel (R) Pentium (R) 4 CPU 2.40 GHz Processor
邏輯分析儀的概念與原理-展示版
PC Base Standalone LA-100 Q&A - - - - - - - SCOPE - - LA - - ( Embedded ) ( Skew ) - Data In External CLK Internal CLK Display Buffer ASIC CPU Memory Trigger Level - - Clock BUS Timing State - ( Timing
Microsoft Word - 封面.doc
USB 系 统 体 系 中 国 电 力 出 版 社 致 谢 感 谢 各 位 参 与 MindShare 的 USB 入 门 课 程 的 工 程 师 他 们 的 意 见 和 见 解 非 常 有 价 值 感 谢 Don Coston 的 投 稿 特 别 感 谢 Tom 和 Nancy Shanley 的 关 心 和 支 持 关 于 本 书 MindShare 体 系 系 列 MindShare 体 系
IP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I
2004 5 IP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I Abstract The techniques of digital video processing, transferring
untitled
2006-4-25 2006-4-26 2 2006-4-26 3 20 50 6 2006-4-26 4 µ 2006-4-26 5 CERN LEP/LHC 2006-4-26 6 L3 Detector 2006-4-26 7 2006-4-26 8 ATLAS Detector (A Toroidal LHC ApparatuS) 2006-4-26 9 CMS Detector 2006-4-26
iml88-0v C / 8W T Tube EVM - pplication Notes. IC Description The iml88 is a Three Terminal Current Controller (TTCC) for regulating the current flowi
iml88-0v C / 8W T Tube EVM - pplication Notes iml88 0V C 8W T Tube EVM pplication Notes Table of Content. IC Description.... Features.... Package and Pin Diagrams.... pplication Circuit.... PCB Layout
P4VM800_BIOS_CN.p65
1 Main H/W Monitor Boot Security Exit System Overview System Time System Date [ 17:00:09] [Fri 02/25/2005] BIOS Version : P4VM800 BIOS P1.00 Processor Type : Intel (R) Pentium (R) 4 CPU 2.40 GHz Processor
Microsoft PowerPoint - Aqua-Sim.pptx
Peng Xie, Zhong Zhou, Zheng Peng, Hai Yan, Tiansi Hu, Jun-Hong Cui, Zhijie Shi, Yunsi Fei, Shengli Zhou Underwater Sensor Network Lab 1 Outline Motivations System Overview Aqua-Sim Components Experimental
1 CPU
2000 Tel 82316285 82317634 Mail liuxd@buaa.edu.cn 1 CPU 2 CPU 7 72 A B 85 15 3 1/2 M301 2~17 : 3/4 1/2 323 IBM PC 1. 2. 3. 1. 2. 3. 1.1 Hardware Software 1.2 M3 M2 M1 1.2 M3 M1 M2 M2 M1 M1 M1 1.2 M3 M1
Ch03_嵌入式作業系統建置_01
Chapter 3 CPU Motorola DragonBall ( Palm PDA) MIPS ( CPU) Hitachi SH (Sega DreamCast CPU) ARM StrongARM CPU CPU RISC (reduced instruction set computer ) CISC (complex instruction set computer ) DSP(digital
行业
PCL-818HD/HG/L PCL-818HD/HG/L 1.1...2 1.1.1 /...2 1.1.2 ID...2 1.2...3 1.3...3 2.1...3 2.2...3 2.2.1...4 2.2.2...4 2.2.3 DMA...5 2.2.4...5 2.2.5 D/A...5 2.2.6...6 2.2.7 EXE.trigger GATE0...6 2.2.8 FIFO
ARM Cortex-M3 (STM32F) STMicroelectronics ( ST) STM32F103 Core: ARM 32-bit Cortex -M3 CPU 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz Single-cycle multiplica
CP Chip Power ARM Cortex-M3 (STM32F) ARM Cortex-M3 (STM32F) STMicroelectronics ( ST) STM32F103 Core: ARM 32-bit Cortex -M3 CPU 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz Single-cycle multiplication and hardware
行业
PCI-1710 1.1...2 1.1.1...2 1.1.2...2 1.1.3 FIFO( )...2 1.1.4...2 1.1.5...2 1.1.6 16 16...3 1.1.7...3 1.2...3 1.3...3 2.1...3 2.2...4 2.2.1...4 2.2.2...5 2.3...9 2.3.1...10 2.3.2... 11 2.3.3...12 2.3.4...12
a b c d e f g C2 C1 2
a b c d e f g C2 C1 2 IN1 IN2 0 2 to 1 Mux 1 IN1 IN2 0 2 to 1 Mux 1 Sel= 0 M0 High C2 C1 Sel= 1 M0 Low C2 C1 1 to 2 decoder M1 Low 1 to 2 decoder M1 High 3 BCD 1Hz clk 64Hz BCD 4 4 0 1 2 to 1 Mux sel 4
工业和信息化部人才交流中心
乐 麦 夫 教 育 电 子 信 息 - 集 成 电 路 紧 缺 人 才 培 养 计 划 集 成 电 路 设 计 系 列 培 训 课 程 超 大 规 模 集 成 电 路 可 测 性 设 计 (DFT) 技 术 与 实 践 培 训 课 程 VLSI DFT Technology and Practice 第 一 期 中 国. 上 海 2016 年 4月 22 日 4 月 23日 各 有 关 单 位 :
KL DSC DEMO 使用说明
:0755-82556825 83239613 : (0755)83239613 : http://www.kingbirdnet.com EMAIL Good989@163.com 1 1 KB3000 DTU... 3 1.1... 3 1.2... 3 1.3... 3 1.4... 3 2... 4 2.1 GSM/GPRS... 4 2.2... 4 2.3... 5 2.4... 6 2.5...
使用手冊
使 用 手 冊 彩 色 液 晶 顯 示 器 重 要 請 仔 細 閱 讀 使 用 手 冊, 掌 握 安 全 及 正 確 的 使 用 方 法 最 新 的 使 用 手 冊 可 從 我 們 的 網 站 下 載 http://www.eizo.com.tw 安 全 性 須 知 關 於 顯 示 器 的 事 項 目 錄 第 1 章 特 色 與 介 紹 1-1 特 色 1-2 控 制 和 功 能 1-3 色 彩 調
MCU DSP MSO MCU DSP MSO MSO MSO MCU/DSP I/O MSO 16 Microchip IC18 turn-on MSO chirp MCU I/O I 2 C
MSO MCU DSP MSO MCU DSP MSO MSO MSO MCU/DSP I/O MSO 16 Microchip IC18 turn-on MSO chirp MCU I/O I 2 C 03 Keysight MSO MSO MSO DSO holdoff infinite-persistence / de-skew MSO 1 MSO MSO MSO MSO MCU DSP 1
投影片 1
2 理 1 2-1 CPU 2-2 CPU 理 2-3 CPU 類 2 什 CPU CPU Central Processing Unit ( 理 ), 理 (Processor), CPU 料 ( 例 ) 邏 ( 例 ),, 若 了 CPU, 3 什 CPU CPU 了, 行, 利 CPU 力 來 行 4 什 CPU 5 2-2-1 CPU CPU 了 (CU, Control Unit) / 邏
行业
PCI-1711/1711L 1.1...2 1.1.1...2 1.1.2...2 1.1.3 FIFO...2 1.1.4...2 1.1.5 16 16...3 1.2...3 2.1...3 2.2...3 2.2.1... 2.2.2...8 2.3...10 2.3.1...10 2.3.2... 11 2.3.3...12 2.3.4...13 2.4.5...14 3.1...16
行业
PCI-1716/1716L 1.1...2 1.1.1...2 1.1.2 / /SD*/BU*...2 1.1.3 FIFO( )...2 1.1.4...2 1.1.5 16 16...3 1.1.6...3 1.1.7 ID...3 1.2...3 2.1...3 2.2...4 2.2.1...4 2.2.2...6 2.3... 11 2.3.1... 11 2.3.2...12 2.3.3...13
untitled
XZL024 http://item.taobao.com/item.htm?id=6321822194 1 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.3 3 USBee Suite 3.1 3.2 3.3 3.4 4 RS232 RS485 RS422 CAN http://item.taobao.com/item.htm?id=6321822194 2 1 XZL024 PC
untitled
niosii H:\DB2005\project\niosDK\Example\NiosSmall QuartusII4.2 File -> New Project Wizard Diectory,Name,Top-Level Entity Add Files EDA Tools Setting Finish, OK H:\DB2005\project\niosDK\Example\NiosSmall
RS-232C [11-13] 1 1 (PLC) (HMI) Visual Basic (PLC) 402
![RS-232C [11-13] 1 1 (PLC) (HMI) Visual Basic (PLC) 402](/thumbs/52/30256726.jpg "RS-232C [11-13] 1 1 (PLC) (HMI) Visual Basic (PLC) 402")
年 路 年 1 [1-3][4] [5-7] [15] Visual Basic [10] 401 RS-232C [11-13] 1 1 (PLC) (HMI) Visual Basic (PLC) 402 1 1 X0 X1 X2 X3 SENSOR Y0 SENSOR VB X3 Y0 Y1 Y2 Y3 Y4 Y5 Y1~Y5 Y6 VB Y7 VB Y11 Y12 Y13 Y14 Y15 Y11~Y15
AN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING
AN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING 前言 - Andrew Payne 目录 1 2 Firefly Basics 3 COMPONENT TOOLBOX 目录 4 RESOURCES 致谢
UDC 厦门大学博硕士论文摘要库
10384 9924012 UDC 2002 5 2002 2002 2002 5 1 Study on High Speed Switch System and Their ASIC Frontend Design Thesis for MS By Shuicheng Cai Supervisor: Prof. Donghui Guo Department of Physics Xiamen Unviersity
SAPIDO GR-1733 無線寬頻分享器
1 版 權 聲 明... 4 產 品 保 固 說 明... 4 保 固 期 限... 4 維 修 辦 法... 5 服 務 條 款... 5 注 意 事 項... 6 低 功 率 電 波 輻 射 性 電 機 管 理 辦 法... 6 CE 標 誌 聲 明... 6 無 線 功 能 注 意 事 項... 6 1 產 品 特 點 介 紹... 7 1.1 LED 指 示 燈 功 能 說 明... 8 1.2
r_09hr_practical_guide_kor.pdf
PRACTICAL GUIDE TO THE EDIROL R-09HR 3 4 PRACTICAL GUIDE TO THE EDIROL R-09HR 5 Situation 1 6 1 2 3 PRACTICAL GUIDE TO THE EDIROL R-09HR WAV MP3 WAV 24 bit/96 khz WAV 16 bit/44.1 khz MP3 128 kbps/44.1
iml v C / 4W Down-Light EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the cur
iml8683-220v C / 4W Down-Light EVM - pplication Notes iml8683 220V C 4W Down Light EVM pplication Notes Table of Content. IC Description... 2 2. Features... 2 3. Package and Pin Diagrams... 2 4. pplication
68369 (ppp quickstart guide)
Printed in USA 04/02 P/N 68369 rev. B PresencePLUS Pro PC PresencePLUS Pro PresencePLUS Pro CD Pass/Fails page 2 1 1. C-PPCAM 2. PPC.. PPCAMPPCTL 3. DB9D.. STPX.. STP.. 01 Trigger Ready Power 02 03 TRIGGER
SPHE8202R Design Guide Important Notice SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provi
SPHE8202R Design Guide V2.0 JUN, 2007 19, Innovation First Road Science Park Hsin-Chu Taiwan 300 R.O.C. Tel: 886-3-578-6005 Fax: 886-3-578-4418 Web: www.sunplus.com SPHE8202R Design Guide Important Notice
untitled
( ) 2005 2 27 1 70 :SSI(Small Scale Integration), 1 10,MSI (Medium Scale Integration),,, 80 LSI(Large Scale Integration),, 16,Motoral M68000(7 ),Intel 80286 (12.5 ),80386 (27.5 ) 90 : VLSI(Very Large Scale
目 录
1 Quick51...1 1.1 SmartSOPC Quick51...1 1.2 Quick51...1 1.3 Quick51...2 2 Keil C51 Quick51...4 2.1 Keil C51...4 2.2 Keil C51...4 2.3 1 Keil C51...4 2.4 Flash Magic...9 2.5 ISP...9 2.6...10 2.7 Keil C51...12
iml v C / 0W EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the current flowin
iml8683-220v C / 0W EVM - pplication Notes iml8683 220V C 0W EVM pplication Notes Table of Content. IC Description... 2 2. Features... 2 3. Package and Pin Diagrams... 2 4. pplication Circuit... 3 5. PCB
+01-10_M5A_C1955.p65
Notebook PC User s Manual C1955 1.01 2005 4 2 50 70 3 (0 30 ) (50 122 ) 4 pre-load Fn+F7 5 ...2...3...6 1-1...12...12...13...14...15...16...17 1-2...18 1-3...20...20...21...21...21...21...22...22...22...22...23...23
中文手册
PCC-3428 PC/104 1. PCC-3428 1.1 PCC-3428 90mm 96mm ST CPU STPC Atlas Atlas CPU 486 DX/DX2 CPU DX2 133MHz Atlas 2D LCD/CRT 100MHz SDRAM 64MBytes PCC-3428 10/100Mbps DOC EIDE USB PC/104 ST STPC Atlas STPC
GA-8IG P4 533 Pentium Rev MC-8IG-1201
GA-8IG P4 533 Pentium Rev. 20 2MC-8IG-20 ... 3... 3... 4... 4 GA-8IG Layout... 6... 7 (CPU... 8 -... 8-2... 9 2... 0 3... 2 4:... 3 4- I/O... 3 4-2... 5 4-3... 2 GA-8IG - 2 - GA-8IG GA-8IG x / x x. 2.
384 : FPGA O-QPSK O-QPSK Fig.1 ProcessofO-QPSK modulationanddemodulation 3 O-QPSK FPGA d Iout d Q Indarrange clk d arrange 20 nsclr
42 3 Vol.42No.3 20126 Microelectronics Jun.2012 FPGA O-QPSK ( 161006) : Quartus IModelSim EP2C35 FPGA Verilog- HDL O-QPSK IP : ; ; :TN91 :A :1004-3365(2012)03-0383-05 DesignofO-QPSK Modem BasedonFPGA TAOBairuiMIAOFengjuanZHANGJinglinZHANG
STK2139 Datasheet
太欣半導體股份有限公司 SYNTEK SEMICONDUCTOR CO., LTD. USB 2.0 Video Class PC Camera Controller STK2139 Datasheet Released Version: V1.4 Content STK2139 1 PRODUCT OVERVIEW... 4 2 FUNCTIONAL BLOCK DIAGRAM... 5 3 PRODUCT
PS PS GMM SM.zte.com.
WBUB-010-1 ZXWN PS V0411.zte.com. PS PS GMM SM.zte.com. PS TMSI Packet-Temporary mobile subscriber identification number P-TMSI) GPRS MS P- TMSI 4 BCD 3G TS 23.003 MSC SGSN SGSN P-TMSI 11 MSC TMSI 00 01
Cube20S small, speedy, safe Eextremely modular Up to 64 modules per bus node Quick reaction time: up to 20 µs Cube20S A new Member of the Cube Family
small, speedy, safe Eextremely modular Up to 64 modules per bus de Quick reaction time: up to 20 µs A new Member of the Cube Family Murrelektronik s modular I/O system expands the field-tested Cube family
Microsoft Word - USB2 0信號分析技巧.doc
USB2.0 信 号 分 析 技 巧 前 言 USB 是 很 常 见 的 串 行 协 议 USB 有 热 插 拔 的 特 性, 当 USB 装 置 插 入 主 机 时, 主 机 会 侦 测 到, 并 且 软 件 会 对 其 作 规 划, 即 插 即 用 USB 的 连 接 线 供 应 装 置 电 源, 可 提 供 DC +5V 的 电 压, 电 流 供 应 约 100mA~500mA USB 的 连
P4Dual-915GL_BIOS_CN.p65
1 Main H/W Monitor Boot Security Exit System Overview System Time System Date Total Memory DIMM 1 DIMM 2 [ 14:00:09] [Wed 01/05/2005] BIOS Version : P4Dual-915GL BIOS P1.00 Processor Type : Intel (R) Pentium
<4D6963726F736F667420576F7264202D2031303130315FB971BEF7BB50B971A46CB8735FB773A55FA5ABA5DFB7E7AADAB0AAAFC5A475B77EC2BEB77EBEC7AED55FA97EAE61C0F4B9D2B4BCBC7AB1B1A8EEA874B2CE2E646F63>
全 國 高 職 學 生 102 年 度 專 題 製 作 競 賽 報 告 書 居 家 環 境 智 慧 控 制 系 統 群 別 : 電 機 與 電 子 群 參 賽 作 品 名 稱 : 居 家 環 境 智 慧 控 制 系 統 關 鍵 詞 : 環 境 監 控 ZigBee 感 測 元 件 目 錄 壹 摘 要... 2 貳 研 究 動 機...2 參 研 究 方 法...3 一 研 究 器 材...3 二 研
ICD ICD ICD ICD ICD
MPLAB ICD2 MPLAB ICD2 PIC MPLAB-IDE V6.0 ICD2 usb PC RS232 MPLAB IDE PC PC 2.0 5.5V LED EEDATA MPLAB ICD2 Microchip MPLAB-IDE v6.0 Windows 95/98 Windows NT Windows 2000 www.elc-mcu.com 1 ICD2...4 1.1 ICD2...4
User ID 150 Password - User ID 150 Password Mon- Cam-- Invalid Terminal Mode No User Terminal Mode No User Mon- Cam-- 2
Terminal Mode No User User ID 150 Password - User ID 150 Password Mon- Cam-- Invalid Terminal Mode No User Terminal Mode No User Mon- Cam-- 2 Mon1 Cam-- Mon- Cam-- Prohibited M04 Mon1 Cam03 Mon1 Cam03
2/80 2
2/80 2 3/80 3 DSP2400 is a high performance Digital Signal Processor (DSP) designed and developed by author s laboratory. It is designed for multimedia and wireless application. To develop application
Outline USB Application Requirements Variable Definition Communications Code for VB Code for Keil C Practice
路 ESW 聯 USB Chapter 9 Applications For Windows Outline USB Application Requirements Variable Definition Communications Code for VB Code for Keil C Practice USB I/O USB / USB 3 料 2 1 3 路 USB / 列 料 料 料 LED
. I/O Third Generation Input Output 3GIO PCI Express 3D 10GHz CPU 1Gb Gbps QoS PCI. PCI Express PCI 10 AGP PCI-X HyperTransport PCI 133MB Mu
No.19 DCE Devices July 1, 2004 2004 6 15 PCI Express Developers Conference 2004 Intel 915P 915G 925X LGA775 P4 -- PCI Express Chipset HubLink Ultra V-Link, PCI Express Desktop.Mobile, Enterprise HyperTransport,
Application Note Format
USB 說 2 - AD PWM Office: 6F, No. 12, Innovation 1st. RD., Science-Based Industrial Park, Hsin-Chu City, Taiwan, R.O.C Tel: +886-3-6661766 ext.1672 Fax: +886-3-6661765 Etoms Electronics Corp. Publication
IP505SM_manual_cn.doc
IP505SM 1 Introduction 1...4...4...4...5 LAN...5...5...6...6...7 LED...7...7 2...9...9...9 3...11...11...12...12...12...14...18 LAN...19 DHCP...20...21 4 PC...22...22 Windows...22 TCP/IP -...22 TCP/IP
图 片 展 示 : 资 源 简 介 : FPGA Altera CycloneII EP2C5T144C8 (4608 个 LE) 2 路 有 源 晶 振 (50M,25M) AS & JTAG 标 准 接 口 VGA 接 口 UART 接 口 蜂 鸣 器 8bit 并 行 DAC 8 路 按 键
官 方 淘 宝 地 址 :http://metech.taobao.com/ MeTech verilog 典 型 例 程 讲 解 V1.0 笔 者 :MeTech 小 芯 技 术 支 持 QQ : 417765928 1026690567 技 术 支 持 QQ 群 :207186911 China AET 讨 论 组 http://group.chinaaet.com/293 笔 者 博 客 :http://blog.csdn.net/ywhfdl
untitled
XILINX Platform Cbale USB www.hseda.com ...... Platform Cable USB Compatible.................. impact.........1 platform Cable USB Compatible.........1...1...1...1...1...1 Platform Cable USB Compatible
MAN- Metropolitan Area Network Resilient Packet Ring a : 5GHz 54Mbps b : 2.4GHz 11Mbps c : MAC Bridge 802.1D 80
IEEE 802.11a s0323516@ncnu.edu.tw 1 (WLAN) [1] 1963 IEEE Institute Of Electrical and Electronics Engineers LAN MAN-Metropolitan Area Network IEEE 802 IEEE 802 Working Group 802.11 IEEE 802 802.1 LAN MAN
RAID RAID 0 RAID 1 RAID 5 RAID * ( -1)* ( /2)* No Yes Yes Yes A. B. BIOS SATA C. RAID BIOS RAID ( ) D. SATA RAID/AHCI ( ) SATA M.2 SSD ( )
RAID RAID 0 RAID 1 RAID 5 RAID 10 2 2 3 4 * (-1)* (/2)* No Yes Yes Yes A. B. BIOS SATA C. RAID BIOS RAID ( ) D. SATA RAID/AHCI ( ) SATA M.2 SSD ( ) ( ) ( ) Windows USB 1 SATA A. SATASATAIntel SATA (SATA3
9 Internet 10 Internet
1 2 3 4 5 6 Internet 7 8 9 Internet 10 Internet 11 12 1 1.1 1.2 1.3 1.4 1.5 1.6 1.1 1.1.1 20 50 20 60 ARPANET ARPANET Internet 20 70 ISO International Organization for Standardization TCP/IP 20 90 Internet
775i65PE_BIOS_CN.p65
1 Main H/W Monitor Boot Security Exit System Overview System Time System Date [ 14:00:09] [Wed 10/20/2004] BIOS Version : 775i65PE BIOS P1.00 Processor Type : Intel (R) CPU 3.20 GHz Processor Speed : 3200
Abstract arm linux tool-chain root NET-Start! 2
Lab III - Embedding Linux 1 Abstract arm linux tool-chain root NET-Start! 2 Part 1.4 Step1. tool-chain 4 Step2. PATH 4 Part 2 kernel 5 Step1. 5 Step2... 6 Step3...8 Part 3 root. 8 Step1. 8 Step2. 8 Part
行业
PCL-1800 PCL-1800 1.1...2 1.1.1 1K FIFO...2 1.1.2...2 1.1.3 16...3 1.1.4...3 1.1.5...3 1.1.6...3 1.2...3 1.3...4 1.4...5 2.1...5 2.2...6 2.2.1...6 2.2.2...6 2.2.3 D/A...7 2.2.4...7 2.2.5 TRIG0 GATE0...8
Value Chain ~ (E-Business RD / Pre-Sales / Consultant) APS, Advanc
Key @ Value Chain fanchihmin@yahoo.com.tw 1 Key@ValueChain 1994.6 1996.6 2000.6 2000.10 ~ 2004.10 (E- RD / Pre-Sales / Consultant) APS, Advanced Planning & Scheduling CDP, Collaborative Demand Planning
AMP NETCONNECT
Quantum AMP NETCONNECT 1 2 ATM TSB 95 TIA/EIA 568-A-5 TIA/EIA 568-B Cat 5e / Cat 6 50 / 125m m 3 TSB95 100Ω Cat5 TIA/EIA 568A-5 100Ω Cat5e TIA/EIA 568B 100 Ω Cat6 ISO/IEC 11801 PDAM-3 PDAM-3 Class D (Cat
Microsoft Word - LD5515_5V1.5A-DB-01 Demo Board Manual
Subject LD5515 Demo Board Model Name (5V/1.5A) Key Features Built-In Pump Express TM Operation Flyback topology with PSR Control Constant Voltage Constant Current High Efficiency with QR Operation (Meet
untitled
EDM12864-GR 1 24 1. ----------------------------------------------------3 2. ----------------------------------------------------3 3. ----------------------------------------------------3 4. -------------------------------------------------------6
画像処理に新しい価値を提供するUSB3.0カメラ(国際画像機器展2014)
December 3, 2014 Toshiaki Iwata Copyright 2014 TOSHIBA TELI CORPORATION, All rights reserved. USB3.0 / USB3 Vision Copyright 2014 TOSHIBA TELI CORPORATION, All rights reserved. 2 Copyright 2014 TOSHIBA
Microsoft Word - 正文.doc
1 2 1 2 3 4 5 6 7 8 9 10 3 1 150 2 150 1 1 1.1 1.1.1 1.2 1.2.1 1.2.2 1.2.3 1.3 1.3.1 1.3.2 1.4 1.4.1 CPU 1.4.2 I/O 1.4.3 I/O 1.5 1.5.1 CISC RISC 1.5.2 1.5.3 1.6 1.6.1 1.6.2 N 1.6.3 2 2.1 2.1.1 2.1.2 2.1.3
untitled
FBC0409 V1.0 1.0 05.06.22 SIA 2005 SIA SIA SIA SIA SIA 114 86-24-23970133 HTTP://WWW.SIA.CN YANG@SIA.CN 2 ...5...5...6 PIN...6...7 1 CPU...8 2...8 4...8 5 DMA...9 7....9 8...9 9...10 A...10 B...10...11.
GW EDA VHDL VHDL VHDL VHDL ADC009 0 FPGA PC GW EDA a GW EDA beda README.TXT c d 0 e J MZH +V GND -V D/A +V GND S JA J D D D D D D D D C K J J VGA VGA B EDA JB B J HC B RS- CON CON HC PS/ CPLD/FPGA J RS-
R3105+ ADSL
... 1 1 1... 1 1 2... 1... 3 2 1... 3 2 2... 3 2 3... 5 2 4... 5 2 4 1... 5... 7 3 1... 7 3 2... 8 3 2 1... 8 3 2 2... 9 3 3... 12 3 3 1... 13 3 3 2 WAN... 16 3 3 3 LAN... 21 3 3 4 NAT... 22 3 3 5... 24
SL2511 SR Plus 操作手冊_單面.doc
IEEE 802.11b SL-2511 SR Plus SENAO INTERNATIONAL CO., LTD www.senao.com - 1 - - 2 - .5 1-1...5 1-2...6 1-3...6 1-4...7.9 2-1...9 2-2 IE...11 SL-2511 SR Plus....13 3-1...13 3-2...14 3-3...15 3-4...16-3
行业
PCL-727 PCL-727 1.1...2 1.2...2 1.3...2 1.4...3 2.1...3 2.2...3 2.2.1...3 2.2.2...4 2.2.3...5 2.3...6 2.4...7 2.4.1...7 2.4.2...9 2.5...15 2.5.1...16 2.5.2...17 2.5.3...18 3.1...19 3.1.1...19 3.1.2 4~20mA...20
99年度提案審查
1/21 2 97 98 99 00 01 02 03 04 05 06 07 3 年度 年 類 例 年 行 量 年 行 量 4 Source NCC 5 行 WAP, GPRS, PHS, 3G (Source: NCC) 6 Source: Allot Mobile Trends 7 ARPU from $48 to $24 by 2011 HSPA Modules from $70 to $35