Microsoft PowerPoint ren-build-CPU [兼容模式]

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1 嵌入式系统设计与应用如何设计一个处理器? 从 0 到 1 西安交通大学电信学院任鹏举

2 如何设计一个处理器? 从 0 到 1 如何设计一个处理器? 如何扩展一个处理器的指令集? 是否可以从处理器的指令集反向设计出相应的处理器?From ISA to Micro-Architecture?

3 如何设计一个处理器? 从 0 到 1 Application Software programs 单时钟处理器多时钟处理器流水线结构及其它 Operating Systems Architecture Microarchitecture Logic Digital Circuits Analog Circuits Devices device drivers instructions registers datapaths controllers adders memories AND gates NOT gates amplifiers filters transistors diodes Physics electrons

4 如何设计一个处理器? 从 0 到 1 程序的执行时间 = (#instructions)*(cycles/instruction) (seconds/cycle) 处理器设计的挑战是满足如下约束 : 耗费 ( 资源 ) 能耗性能 ( 吞吐率 \ 延迟.etc) 以典型的逻辑运算 \ 数学运算 :Add,And 存储器操作 : LOAD, STORE 条件转移指令 :Branch

5 如何设计一个单时钟处理器? 32bits 哈佛结构处理器的基本构成单元

6 如何设计一个单时钟处理器? STEP1: 指令存储器中取指令操作

7 如何设计一个单时钟处理器? STEP2: 从寄存器文件中取源操作数

8 如何设计一个单时钟处理器? STEP3. 拓展带符号的立即数

9 如何设计一个单时钟处理器? LAD r1 {r0 #5} STEP4. 计算存储器地址

10 如何设计一个单时钟处理器? LAD r1 {r0 #5} STEP5. 从存储器中读取数据并写回寄存器文件

11 如何设计一个单时钟处理器? LAD r1 {r0 #5} STEP5. 从存储器中读取数据并写回寄存器文件

12 如何设计一个单时钟处理器? STEP6. 确定下一条指令的地址

13 如何设计一个单时钟处理器? STR r1 ADDR

14 如何设计一个单时钟处理器? 将计算结果回写到寄存器

15 如何设计一个单时钟处理器? Branch 跳转指令

16 如何设计一个单时钟处理器?

17 如何设计一个单时钟处理器?

18 回顾 ALU A N ALU Y N B N 3 F F 2:0 Function 000 A & B 001 A B 010 A + B 011 not used 100 A & ~B 101 A ~B 110 A - B 111 SLT C out Zero Extend N 3 A N 1 + [N-1] S N 2 N B N 0 N N 1 N 0 2 F 2 F 1:0 Y N

19 控制单元设计 Instruction Op 5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp 1:0 load store X X 00 beq X X 01

20 如何设计一个单时钟处理器? SignImm CLK A RD Instruction Memory + 4 A1 A3 WD3 RD2 RD1 WE3 A2 CLK Sign Extend Register File A RD Data Memory WD WE 0 1 PC 0 1 PC' Instr 25:21 20:16 15:0 5:0 SrcB 20:16 15:11 <<2 + ALUResult ReadData WriteData SrcA PCPlus4 PCBranch WriteReg 4:0 Result 31:26 RegDst Branch MemWrite MemtoReg ALUSrc RegWrite Op Funct Control Unit Zero PCSrc CLK ALUControl 2:0 ALU

21 如何设计一个单时钟处理器?

22 控制单元设计 - 增加指令 Jump Instruction Op 5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp 1:0 Jump load store X X 00 0 beq X X 01 0 j X X X 0 X XX 1

23 如何设计一个单时钟处理器?

24 如何设计一个单时钟处理器? 程序的执行时间 = (#instructions)(cycles/instruction)(seconds/cycle) Program Execution Time = (#instructions)(cycles/instruction)(seconds/cycle) = # instructions x CPI x T C T C limited by critical path T C 取决于处理器中执行时间最长的指令路径的延迟 ( 单指令系统 )

25 如何设计一个单时钟处理器?

26 如何设计一个单时钟处理器? 处理器工作的最高频率?

27 如何设计一个单时钟处理器? Program with 100 billion instructions: Execution Time = # instructions x CPI x T C = ( )(1)( s) = 92.5 seconds

28 单时钟处理器 v.s 多时钟处理器 Single-cycle: + simple - cycle time limited by longest instruction - 2 adders/alus & 2 memories Multicycle: + higher clock speed + simpler instructions run faster + reuse expensive hardware on multiple cycles - sequencing overhead paid many times Same design steps: datapath & control

29 如何设计一个多时钟处理器? 哈佛结构处理器的基本构成单元 ( 单指令 ) 冯诺伊曼结构处理器的基本构成单元 ( 多指令 )

30 如何设计一个多时钟处理器? Step1 :Fetch instruction from memory

31 如何设计一个多时钟处理器? Step2: Read source operand from register file

32 如何设计一个多时钟处理器? Step2b: 扩展符号的立即数

33 如何设计一个多时钟处理器? Step3: 计算存储器地址

34 如何设计一个多时钟处理器? Step4: 从存储器中读取数据

35 如何设计一个多时钟处理器? Step5: 将数据写回到寄存器文件

36 如何设计一个多时钟处理器? Step 6: 增加 PC

37 单时钟处理器的 PC

38 如何设计一个多时钟处理器?

39 如何设计一个多时钟处理器?

40 如何设计一个多时钟处理器?

41 如何设计一个多时钟处理器?

42 如何设计一个多时钟处理器? Control Unit Opcode 5:0 Main Controller (FSM) MemtoReg RegDst IorD PCSrc ALUSrcB 1:0 ALUSrcA IRWrite MemWrite PCWrite Branch RegWrite Multiplexer Selects Register Enables ALUOp 1:0 Funct 5:0 ALU Decoder ALUControl 2:0

43 S0: Fetch Reset

46 如何设计一个多时钟处理器? Memory read

47 如何设计一个多时钟处理器? Memory Write

48 如何设计一个多时钟处理器? 执行另外一种操作

49 如何设计一个多时钟处理器? 增加 Branch 操作

50 如何设计一个多时钟处理器?

51 如何设计一个多时钟处理器? S2: MemAdr S0: Fetch IorD = 0 Reset AluSrcA = 0 ALUSrcB = 01 ALUOp = 00 PCSrc = 00 IRWrite PCWrite ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Op = LW or Op = SW S1: Decode ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Op = R-type S6: Execute ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 Op = BEQ Op = J Op = ADDI S8: Branch ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCSrc = 01 Branch S11: Jump ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Op = LW S3: MemRead Op = SW S5: MemWrite S7: ALU Writeback S9: ADDI Execute S10: ADDI Writeback IorD = 1 IorD = 1 MemWrite RegDst = 1 MemtoReg = 0 RegWrite RegDst = 0 MemtoReg = 0 RegWrite S4: Mem Writeback RegDst = 0 MemtoReg = 1 RegWrite

52 如何设计一个多时钟处理器?

53 如何设计一个多时钟处理器? PCEn IorD MemWrite IRWrite RegDst MemtoReg RegWrite ALUSrcA ALUSrcB 1:0 ALUControl 2:0 BranchPCWrite PCSrc 1:0 PC' CLK PC 0 EN 1 Adr CLK A RD Instr / Data Memory WD WE CLK EN CLK Instr Data 25:21 20:16 20:16 15: CLK A1 A2 WE3 RD1 RD2 A3 Register File WD3 CLK A B 31: << SrcA SrcB ALU Zero ALUResult CLK PCJump <<2 27:0 ALUOut :0 Sign Extend SignImm 25:0 (jump)

54 如何设计一个多时钟处理器? Instructions take different number of cycles: 3 cycles: beq, j 4 cycles: store, addi 5 cycles: load CPI is weighted average ( 时钟周期 / 每条指令 ) SPECINT2000 benchmark: 25% loads 10% stores 11% branches 2% jumps 52% R-type Average CPI = ( )(3) + ( )(4) + (0.25)(5) = 4.12

55 如何设计一个多时钟处理器? Tc=? Element Parameter Delay (ps) Register clock-to-q t pcq_pc 30 Register setup t setup 20 Multiplexer t mux 25 ALU t ALU 200 Memory read t mem 250 Register file read t RFread 150 Register file setup t RFsetup 20

56 如何设计一个多时钟处理器? Element Parameter Delay (ps) Register clock-to-q t pcq_pc 30 Register setup t setup 20 Multiplexer t mux 25 ALU t ALU 200 Memory read t mem 250 Register file read t RFread 150 Register file setup t RFsetup 20 多时钟处理器执行时间单时钟处理器执行时间

57 如何设计一个多时钟处理器? Program with 100 billion instructions: Execution Time = # instructions x CPI x T C = ( )(4.12)( s) = seconds This is slower than the single-cycle processor (92.5 seconds). Why?

58 回顾 : 单指令处理器 31:26 5:0 MemtoReg Control MemWrite Unit Branch ALUControl 2:0 Op ALUSrc Funct RegDst RegWrite PCSrc PC' CLK PC A RD Instruction Memory Instr 25:21 20:16 CLK A1 A2 WE3 RD1 RD2 A3 Register WD3 File 0 1 SrcA SrcB ALU Zero ALUResult WriteData CLK A RD Data Memory WD WE ReadData 0 1 Result PCJump 4 + PCPlus4 20:16 15:11 15:0 Jump WriteReg 4:0 Sign Extend 0 1 SignImm <<2 + PCBranch 27:0 31:28 25:0 <<2

59 回顾 : 多指令处理器 PC' CLK PC 0 EN 1 Adr CLK A RD Instr / Data Memory WD WE CLK EN CLK Instr Data 25:21 20:16 20:16 15: CLK A1 A2 WE3 RD1 RD2 A3 Register File WD3 CLK A B 31: << SrcA SrcB ALU IorD MemWrite IRWrite 31:26 5:0 CLK Control Unit Op Funct PCWrite Branch PCSrc ALUControl 2:0 ALUSrcB 1:0 ALUSrcA RegWrite PCEn MemtoReg RegDst Zero ALUResult <<2 CLK PCJump 27:0 ALUOut :0 Sign Extend ImmExt 25:0 (Addr)

60 流水线的概念 (1) 以洗衣服为例假设有 Ann, Brian, Cathy, Dave 四个人, 每个人都需要洗衣烘干和叠衣服三个步骤洗衣需要 30 分钟烘干需要 40 分钟叠衣服需要 20 分钟 A B C D

61 流水线的概念 (2) 6 PM Midnight Time T a s k O r d e r A B C D 人的衣量, 如果顺序洗衣服, 共需要 6 个小时如果她们学过流水线需要多少时间?

62 流水线的概念 (3) 6 PM Midnight Time T a s k O r d e r A B C D 4 人的衣量, 如果用流水线的方式洗衣服, 只需要 3.5 小时

63 流水线的概念 (4) T a s k O r d e r A B C D 6 PM Time 流水线无法减少每个任务的延迟, 但可以提高整个工作的吞吐率流水线的速率受限于速度最慢的一级多个任务同时执行最大提速比 = 流水线级数进 / 出流水线的时间降低了提速比

64 处理器的流水线通常, 最大的处理速度取决于计算逻辑的传输延迟如上图, 每隔 T1+T2 时间周期可以处理一个输入数据寄存器如上图的结构, 每隔 max{t1,t2} 时间周期可以处理一个输入数据, 但是每个输入处理时间仍需要 T1+T2

65 单时钟处理器单时钟处理器的数据通路图

66 单时钟处理器 & 流水线设计多时钟处理器的数据通路图

67 流水线处理器的控制

68 流水线处理器 Temporal parallelism ( 时域并行 ) Divide single-cycle processor into 5 stages: 将单时钟处理器分为 5 级流水 Fetch ( 取指令 ) Decode ( 指令解码 ) Execute ( 执行运算 ) Memory ( 存储器控制 ) Writeback ( 写回操作 ) Add pipeline registers between stages 在每级流水线间增加寄存器

69 Instr 1 2 流水线处理器 Fetch Instruction Decode Read Reg Execute ALU Memory Read / Write Single-Cycle Write Reg Fetch Instruction Decode Read Reg Execute ALU Memory Read / Write Time (ps) Write Reg Pipelined Instr 1 Fetch Instruction Decode Read Reg Execute ALU Memory Read/Write Write Reg 2 Fetch Instruction Decode Read Reg Execute ALU Memory Read/Write Write Reg 3 Fetch Instruction Decode Read Reg Execute ALU Memory Read/Write Write Reg

70 流水线处理器的控制 - 危险? When an instruction depends on result from instruction that hasn t completed 当前指令依赖于前序指令未完成的结果 Types: Data hazard: register value not yet written back to register file 数据冲突 : 寄存器的值还未写回寄存器文件 Control hazard: next instruction not decided yet (caused by branches) 控制冲突 : 由于跳转指令导致的下一条指令未明确

71 流水线处理器的控制 - 数据冲突

72 数据冲突消除 - 增加空指令 Insert enough nops for result to be ready Or move independent useful instructions forward Time (cycles) add $s2 add $s0, $s2, $s3 IM RF $s3 + DM $s0 RF nop IM nop RF DM RF nop IM nop RF DM RF and $t0, $s0, $s1 IM and $s0 RF $s1 & DM $t0 RF 9 10 or $t1, $s4, $s0 IM or $s4 RF $s0 DM $t1 RF sub $t2, $s0, $s5 IM sub $s0 RF $s5 - DM $t2 RF

73 数据冲突消除 - 数据前向转移

74 数据冲突消除 - 数据前向转移

75 数据冲突消除 - 数据前向转移

76 流水线处理器的控制 - 控制冲突

77 流水线处理器的控制 - 控制冲突

78 控制冲突消除

79 控制冲突消除

80 控制冲突消除 - 预测 Branch Guess whether branch will be taken( 猜想 ) Backward branches are usually taken (loops) loops 循环经常发生如 :for 循环 Consider history to improve guess 利用实施数据来提高预测准确性 Good prediction reduces fraction of branches requiring a flush 好的预测可以降低需要冲刷的 Branch 比例

81 多时钟处理器流水线结构的性能 SPECINT2000 benchmark: 25% loads 10% stores 11% branches 2% jumps 52% R-type Suppose: 40% of loads used by next instruction (40% 2 cycles, 60% 1 cycles) 25% of branches mispredicted (75% 1cycle; 25% 2 cycles) All jumps flush next instruction (2 cycles) What is the average CPI? Load/Branch CPI = 1 when no stalling, 2 when stalling CPI lw = 1(0.6) + 2(0.4) = 1.4 CPI beq = 1(0.75) + 2(0.25) = 1.25 Average CPI = (0.25)(1.4) + (0.1)(1) + (0.11)(1.25) + (0.02)(2) + (0.52)(1) = 1.15

82 流水线处理器性能 Program with 100 billion instructions: Execution Time = # instructions x CPI x T C = ( )(4.12)( s) = seconds 多指令处理器性能 Execution Time = (# instructions) CPI T c = ( )(1.15)( ) = 63 seconds 流水线处理器性能

83 流水线处理器增加冲突控制

84 流水线处理器 - 异常处理 Unscheduled function call to exception handler Caused by: Hardware, also called an interrupt, e.g. keyboard 硬件引起的, 也称为中断, 如键盘 Software, also called traps, e.g. undefined instruction 软件引起的, 也称为陷阱, 如未定义的指令 When exception occurs, the processor: Records cause of exception (Cause register) 记录导致异常的原因 Jumps to exception handler (0x ) 跳转到异常处理部分 Returns to program (EPC register) 返回程序 ( 异常 PC 寄存器 )

85 流水线处理器 - 异常处理 ( 举例 )

86 流水线处理器 - 异常处理 Exception Hardware Interrupt Cause 0x System Call Breakpoint / Divide by 0 Undefined Instruction Arithmetic Overflow 0x x x x

87 流水线处理器 - 异常处理

88 流水线处理器 - 异常处理 S12: Undefined PCSrc = 11 PCWrite IntCause = 1 CauseWrite EPCWrite S14: MFC0 RegDst = 0 Memtoreg = 10 RegWrite Op = others S2: MemAdr S0: Fetch IorD = 0 Reset AluSrcA = 0 ALUSrcB = 01 ALUOp = 00 PCSrc = 00 IRWrite PCWrite ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Op = LW or Op = SW S1: Decode ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Op = R-type S6: Execute ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 Op = BEQ Op = J Op = ADDI S8: Branch ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCSrc = 01 Branch S11: Jump S9: ADDI Execute PCSrc = 10 PCWrite ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Op = LW S3: MemRead IorD = 1 Op = SW S5: MemWrite IorD = 1 MemWrite Op = mfc0 S7: ALU Overflow Overflow Writeback S13: Overflow PCSrc = 11 RegDst = 1 MemtoReg = 00 RegWrite PCWrite IntCause = 0 CauseWrite EPCWrite S10: ADDI Writeback RegDst = 0 MemtoReg = 00 RegWrite S4: Mem Writeback RegDst = 0 MemtoReg = 01 RegWrite

89 高级处理器采用的技术 Deep Pipelining ( 深度流水线 ) Branch Prediction ( 跳转预测 ) Superscalar Processors ( 超标量处理器 ) Out of Order Processors ( 乱序执行处理器 ) Register Renaming ( 寄存器重命名 ) SIMD ( 单指令多数据 ) Multithreading ( 多线程 ) Multiprocessors ( 多处理器 )

90 高级处理器采用的技术 Deep Pipelining ( 深度流水线 ) stages typical Number of stages limited by: Pipeline hazards Sequencing overhead Power Cost

91 高级处理器采用的技术 Branch Prediction( 跳转预测 ) Ideal pipelined processor: CPI = 1 Branch misprediction increases CPI Static branch prediction( 静态预测 ): Check direction of branch (forward or backward) If backward, predict taken Else, predict not taken Dynamic branch prediction( 动态预测 ): Keep history of last (several hundred) branches in branch target buffer, record: Branch destination Whether branch was taken

92 高级处理器采用的技术 Deep Pipelining ( 深度流水线 ) Branch Prediction ( 跳转预测 ) Superscalar Processors ( 超标量处理器 ) Out of Order Processors ( 乱序执行处理器 ) Register Renaming ( 寄存器重命名 ) SIMD ( 单指令多数据 ) Multithreading ( 多线程 ) Multiprocessors ( 多处理器 )

93 超标量处理器 (Superscalar)

94 超标量处理器 (Superscalar)

95 超标量处理器 (Superscalar)

96 高级处理器采用的技术 Deep Pipelining ( 深度流水线 ) Branch Prediction ( 跳转预测 ) Superscalar Processors ( 超标量处理器 ) Out of Order Processors ( 乱序执行处理器 ) Register Renaming ( 寄存器重命名 ) SIMD ( 单指令多数据 ) Multithreading ( 多线程 ) Multiprocessors ( 多处理器 )

97 高级处理器采用的技术 - 乱序 Out of Order Looks ahead across multiple instructions Issues as many instructions as possible at once Issues instructions out of order (as long as no dependencies) Dependencies: RAW (read after write): one instruction writes, later instruction reads a register WAR (write after read): one instruction reads, later instruction writes a register WAW (write after write): one instruction writes, later instruction writes a register

98 高级处理器采用的技术 - 乱序 Out of Order Instruction level parallelism (ILP): number of instruction that can be issued simultaneously (average < 3) Scoreboard: table that keeps track of: Instructions waiting to issue Available functional units Dependencies

99 乱序执行 (Out-of-Order)

100 高级处理器采用的技术 Deep Pipelining ( 深度流水线 ) Branch Prediction ( 跳转预测 ) Superscalar Processors ( 超标量处理器 ) Out of Order Processors ( 乱序执行处理器 ) Register Renaming ( 寄存器重命名 ) SIMD ( 单指令多数据 ) Multithreading ( 多线程 ) Multiprocessors ( 多处理器 )

101 寄存器重命名 (Register Renaming) Time (cycles) lw $t0, 40($s0) sub $r0, $s2, $s3 IM lw sub RF $s0 40 $s2 $s3 + - DM $t0 $r0 RF 2-cycle RAW RAW and $t2, $s4, $r0 or $t3, $s5, $s6 IM and or RF $s4 $r0 $s5 $s6 & DM $t2 $t3 RF RAW add $t1, $t0, $s1 sw $s7, 80($t3) IM add sw RF $t0 $s1 $t DM $s7 $t1 RF

102 高级处理器采用的技术 Deep Pipelining ( 深度流水线 ) Branch Prediction ( 跳转预测 ) Superscalar Processors ( 超标量处理器 ) Out of Order Processors ( 乱序执行处理器 ) Register Renaming ( 寄存器重命名 ) SIMD ( 单指令多数据 ) Multithreading ( 多线程 ) Multiprocessors ( 多处理器 )

103 高级处理器采用的技术 -SIMD SIMD (Single Instruction Multiple Data) Single instruction acts on multiple pieces of data at once 同样的指令同时作用于多个数据 Common application: graphics 常用在图形学应用 Perform short arithmetic operations (also called packed arithmetic) 常常是较短的数值运算 For example, add four 8-bit elements padd8 $s2, $s0, $s Bit position a 3 a 2 a 1 a 0 $s0 + b 3 b 2 b 1 b 0 $s1 a 3 + b 3 a 2 + b 2 a 1 + b 1 a 0 + b 0 $s2

104 高级处理器采用的技术 Deep Pipelining ( 深度流水线 ) Branch Prediction ( 跳转预测 ) Superscalar Processors ( 超标量处理器 ) Out of Order Processors ( 乱序执行处理器 ) Register Renaming ( 寄存器重命名 ) SIMD ( 单指令多数据 ) Multithreading ( 多线程 ) Multiprocessors ( 多处理器 )

105 高级处理器采用的技术 Multithreading - Wordprocessor: thread for typing, spell checking, printing 如文字处理时, 键入, 拼写检查, 打印 Multiprocessors - Multiple processors (cores) on a single chip 单颗芯片上有多个处理器 ( 处理核 )

106 进程 v.s 线程 Process: program running on a computer Multiple processes can run at once: e.g., surfing Web, playing music, writing a paper 多个进程可以同时工作 : 浏览网站播放音乐写论文 Thread: part of a program Each process has multiple threads: e.g., a word process may have threads for typing, spell checking, printing 每个进程含有多个线程 : 如同样的文字处理包含键入拼写检查打印等线程 ( 可能共享数据, 或共同完成任务 )

107 传统处理器中的线程 One thread runs at once When one thread stalls (for example, waiting for memory): Architectural state of that thread stored 当线程等待时, 状态需要存储 Architectural state of waiting thread loaded into processor and it runs 当线程的状态读入处理器时, 线程继续执行 Called context switching Appears to user like all threads running simultaneously 从用户的角度看多个线程是在同时执行

108 多线程处理器中的线程 Multiple copies of architectural state Multiple threads active at once: When one thread stalls, another runs immediately If one thread can t keep all execution units busy, another thread can use them Does not increase instruction-level parallelism (ILP) of single thread, but increases throughput Simultaneously multithreading Intel calls this hyperthreading

109 多核处理器 Multiple processors (cores) with a method of communication between them Types: Homogeneous: multiple cores with shared memory Heterogeneous: separate cores for different tasks (for example, DSP and CPU in cell phone) Clusters: each core has own memory system

110 多核多线程处理器举例 Intel Xeon processor with 6 cores/12 Threads and 6 L3 cache units IBM BG/Q Compute Chip with 18 cores (PU) and 16 L2 Cache units (L2) Nvdia Kepler GPGPU

111 Source from Kirk (Vice President, Intel Crop) 高性能计算已经成为科学研究和重大工程设计中具有战略意义的研究手段

112 Pen gju R en@ IA=I 并行性性能提升 RX JTU 片上核心的数目每18个月翻倍代替时钟频率x2! 处理器是未来的晶体管

显式的存储层次化结构 ( 提供计算局域性 ) 高效的通讯系统 ( 提高系统协同效率 ), 多种方法协同的容错机制 ( 系统可靠性 ) 1Gb 2GHz Embedded DRAM

113 能耗是传统方法不再适用的核心问题 64 bit DP 20pJ 256-bit access 8kB SRAM 256-bit Buses 26pJ 256pJ 20 mm 50pJ 效率 = 局域性 500pJ 16nJ DRAM Rd/Wr Off-chip Access 1nJ 28 nm 计算系统需要大量的处理单元 ( 提供潜在的并行性 ), 显式的存储层次化结构 ( 提供计算局域性 ) 高效的通讯系统 ( 提高系统协同效率 ), 多种方法协同的容错机制 ( 系统可靠性 ) 1Gb 2GHz Embedded DRAM in 22nm Tri-Gate (Intel 2014 ISSCC) Source from Professor Bill Dally (Chief scientist of Nvidia)

114 片上互连网络的发展路线图 Bus (core<=8) Ring (cores<10) Crossbar (cores<16) 2D Mesh (cores<=100 ) Optical Network (cores >100) 3D Topology (cores >100) IBM Cell (8-core) Sun SPAC T1 (8-core) Intel TeraFlop80 (80-core) Intel SCC48 (48-core) Tilera (64/100cores) Sun SPAC T5 (16-core) ATAC (1024 core)

State-of-the-art 的研究成果 The chip, called TrueNorth, consists of 1 million programmable neurons and 256 million programmable synapses across 4096

IBM is now a big step closer to building a brain on a chip. P. A. Merolla, J. V. Arthur, R. Alvarez-Icaza, A. S. Cassidy, J. Sawada, F. Akopyan, B. L.

115 State-of-the-art 的研究成果 The chip, called TrueNorth, consists of 1 million programmable neurons and 256 million programmable synapses across 4096 individual neurosynaptic cores. Built on Samsung s 28nm process and with a monstrous transistor count of 5.4 billion. IBM is now a big step closer to building a brain on a chip. P. A. Merolla, J. V. Arthur, R. Alvarez-Icaza, A. S. Cassidy, J. Sawada, F. Akopyan, B. L. Jackson, N. Imam, C. Guo, Y. Nakamura et al., A million spiking-neuron integrated circuit with a scalable communication network and interface, Science, vol. 345, no. 6197, pp , 2014.

116 State-of-the-art 的研究成果

117 片上互联网络通讯范式 (0,3) (1,3) (2,3) (3,3) (0,2) (1,2) (2,2) (3,2) (0,1) (1,1) (2,1) (3,1) (0,0) (1,0) (2,0) (3,0) Processor Element Router 片上互联网络当前的发展水平 e.g. Intel Tera80 (2007), Single-cloud computing 48 (2009), Tilera 64/100 (2011) 16x16 Network-on-chip in 22nm 340mV-0.9V 20.2Tb/s (Intel 2014) A 22nm 15-Core Enterprise Xeon Processor (Intel 2014)

片上互连网络的研究内容 Module description & Organization

Partition & Scheduling Design Constrains & Goals

118 片上互连网络的研究内容 Module description & Organization Communication profile Module Grouping Task Mapping & Partition & Scheduling Design Constrains & Goals Optimization Communication Routing, Infrastructure Flow control Analysis etc. Simulation Prototyping Test & Verification Physical synthesis & Floorplan &Tapeout 从计算机体系结构操作系统嵌入式系统 VLSI 系统设计和计算机辅助设计等

119 HPC

120 其他参考学习资料 Patterson & Hennessy s: Computer Architecture: A Quantitative Approach 计算机体系结构的圣经 Conferences: ( 国际顶级会议 ) ISCA (International Symposium on Computer Architecture) HPCA (International Symposium on High Performance Computer Architecture)

121 嵌入式课程第一次实验安排在第五周请各班班长去实验中心与刘美兰老师联系实验时间

Microsoft PowerPoint - CA_02 Chapter5 Part-I_Single _V2.ppt

Microsoft PowerPoint - CA_02 Chapter5 Part-I_Single _V2.ppt Chapter5- The Processor: Datapath and Control (Single-cycle implementation) 臺大電機系吳安宇教授 V. 3/27/27 V2. 3/29/27 For 27 DSD Course 臺大電機吳安宇教授 - 計算機結構 Outline 5. Introduction 5.2 Logic Design Conventions 5.3