单周期数据通路

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1 计算机组织与系统结构设计单周期数据通路的处理器 Designing a Single Cycle Datapath Microprocessor 第四讲程旭 27..2

2 2 Processor Processor Control Enable? Read/Write Memory Datapath PC Registers Arithmetic & Logic Unit (ALU) Address Write Data Read Data Program Bytes Data Processor-Memory Interface

3 处理器性能 CPI 计算机的性能决定于 : 指令总数时钟周期时间每条指令的时钟周期数目处理器设计 ( 数据通路和控制 ) 将决定 : 时钟周期时间每条指令的时钟周期数目单周期处理器 : 优点 : 每条指令一个时钟周期缺点 : 时钟周期时间太长指令总数周期时间

4 如何设计处理器 : 循序渐进. 分析指令系统 => 数据通路需求通过寄存器传输描述每条指令的意图针对 ISA 寄存器, 数据通路必须具备必要的存储元件可能需要多个数据通路必须支持每种寄存器传输 2. 选择一组数据通路部件, 建立时钟同步方法 3. 根据需求, 组装数据通路 4. 分析每条指令的实现, 以确定如何设置影响寄存器传输的控制点 5. 装配控制逻辑

5 RISCV32I 指令格式 Not in this Lecture

6 6 State Required by RV32I ISA Each instruction reads and updates this state during execution: Registers (x..x3) Register file (or regfile) Reg holds 32 registers x 32 bits/register: Reg[].. Reg[3] First register read specified by rs field in instruction Second register read specified by rs2 field in instruction Write register (destination) specified by rd field in instruction x is always (writes to Reg[]are ignored) Program Counter (PC) Holds address of current instruction Memory (MEM) Holds both instructions & data, in one 32-bit byte-addressed memory space We ll use separate memories for instructions (IMEM) and data (DMEM) Later we ll replace these with instruction and data caches Instructions are read (fetched) from instruction memory Load/store instructions access data memory

7 One-Instruction-Per-Cycle RISC-V Machine pc clock IMEM Reg[] DMEM Combinationa l Logic On every tick of the clock, the computer executes one instruction Current state outputs drive the inputs to

7 7 One-Instruction-Per-Cycle RISC-V Machine pc clock IMEM Reg[] DMEM Combinationa l Logic On every tick of the clock, the computer executes one instruction Current state outputs drive the inputs to the combinational logic, whose outputs settles at the values of the state before the next clock edge At the rising clock edge, all the state elements are updated with the combinational logic outputs, and execution moves to the next clock cycle

8 mux PC IMEM Reg[] DMEM 8 Basic Phases of Instruction Execution rd rs rs2 ALU +4 imm Clock. Instruction Fetch time 2. Decode/ Register Read 5. Register 3. Execute 4. Memory Write

9 9 Implementing the add instruction add rd, rs, rs2 Instruction makes two changes to machine s state: Reg[rd] = Reg[rs] + Reg[rs2] PC = PC + 4

10 Datapath for add pc+4 pc +4 IMEM inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2 ] + alu inst[3:] RegWriteEnable (RegWEn) Control Logic

11 Timing Diagram for add clock pc+4 pc +4 IMEM inst[3:] Reg[] DataD inst[:7] AddrD inst[9:5] AddrADataA inst[24:2] AddrBDataB RegWEn Reg[rs ] Reg[rs2 ] time + alu Clock PC PC inst[3:] Reg[rs] Reg[rs2] add x,x2,x3 Reg[2] Reg[3] add x6,x7,x9 Reg[7] Reg[9] alu Reg[2]+Reg[3] Reg[7]+Reg[9] Reg[]??? Reg[2]+Reg[3]

12 Implementing the sub instruction sub rd, rs, rs2 Almost the same as add, except now have to subtract operands instead of adding them inst[3] selects between add and subtract

13 Datapath for add/sub pc+4 pc +4 IMEM inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2 ] ALU alu inst[3:] RegWEn (=write, =no write) Control Logic ALUSel (Add=/Sub=)

14 Implementing other R-Format instructions All implemented by decoding funct3 and funct7 fields and selecting appropriate ALU function

15 5 Implementing the addi instruction RISC-V Assembly Instruction: addi x5,x,-5 imm=-5 rs= ADD rd=5 OP-Imm

16 Datapath for add/sub pc+4 pc +4 IMEM inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2 ] ALU alu inst[3:] RegWEn (=write, =no write) Control Logic ALUSel (Add=/Sub=)

17 Adding addi to datapath +4 Reg[] pc+4 pc IMEM inst[:7] inst[9:5] inst[24:2] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2 ] ALU alu inst[3:2] Imm. Gen imm[3:] inst[3:] ImmSel=IRegWEn= BSel= ALUSel=Add Control Logic

18 I-Format immediates inst[3:] inst[3]-(sign-extension) inst[3:2] inst[3:2] Imm. Gen ImmSel=I imm[3:] imm[3:] High 2 bits of instruction (inst[3:2]) copied to low 2 bits of immediate (imm[:]) Immediate is sign-extended by copying value of inst[3] to fill the upper 2 bits of the immediate value (imm[3:2])

19 Adding addi to datapath +4 Reg[] pc+4 pc IMEM inst[:7] inst[9:5] AddrADataA inst[24:2] AddrBDataB inst[3:2] DataD AddrD Imm. Gen Reg[rs] Reg[rs2 ] imm[3:] ALU alu Also works for all other I- format arithmetic instruction (slti,sltiu,andi,ori, xori,slli,srli,srai) just by changing ALUSel inst[3:] ImmSel=IRegWEn= BSel= ALUSel=Add Control Logic

20 Implementing Load Word instruction RISC-V Assembly Instruction: lw x4, 8(x2) imm=+8 rs=2 LW rd=4 LOAD /6/27

21 Adding addi to datapath +4 Reg[] pc+4 pc IMEM inst[:7] inst[9:5] inst[24:2] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2 ] ALU alu inst[3:2] Imm. Gen imm[3:] inst[3:] ImmSel=IRegWEn= BSel= ALUSel=Add Control Logic

22 Adding lw to datapath pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2] ALU Addr alu DMEM DataR mem wb inst[3:2] Imm. Gen imm[3:] inst[3:] ImmSel RegWEn BSel ALUSel MemRW WBSel

23 Adding lw to datapath pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2] ALU Addr alu DMEM DataR mem wb inst[3:2] Imm. Gen imm[3:] inst[3:] ImmSel=IRegWEn= Bsel= ALUSel=Add MemRW=Read WBSel=

24 All RV32 Load Instructions funct3 field encodes size and signedness of load data Supporting the narrower loads requires additional circuits to extract the correct byte/halfword from the value loaded from memory, and sign- or zero-extend the result to 32 bits before writing back to register file.

25 5 Implementing Store Word instruction RISC-V Assembly Instruction: sw x4, 8(x2) offset[:5] = rs2=4 rs=2 SW offset[4:] =8 STORE combined 2-bit offset = 8

26 Adding lw to datapath pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2] ALU Addr alu DMEM DataR mem wb inst[3:2] Imm. Gen imm[3:] inst[3:] ImmSel RegWEn BSel ALUSel MemRW WBSel

27 Adding sw to datapath pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2] ALU DMEM alu Addr DataR DataW mem wb inst[3:7] Imm. Gen imm[3:] inst[3:] ImmSel RegWEn Bsel ALUSel MemRW WBSel=

28 Adding sw to datapath pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2] ALU DMEM alu Addr DataR DataW mem wb inst[3:7] Imm. Gen imm[3:] inst[3:] ImmSel=S RegWEn= Bsel= ALUSel=Add MemRW=Write WBSel=* *= Don t Care

29 I-Format immediates inst[3:] inst[3]-(sign-extension) inst[3:2] inst[3:2] Imm. Gen ImmSel=I imm[3:] imm[3:] High 2 bits of instruction (inst[3:2]) copied to low 2 bits of immediate (imm[:]) Immediate is sign-extended by copying value of inst[3] to fill the upper 2 bits of the immediate value (imm[3:2])

30 I & S Immediate Generator inst[3:] imm[:] rs funct3 rd I-opcode imm[:5] rs2 rs funct3 imm[4:] S-opcode I S 3 inst[3](sign-extension) inst[3:25] Just need a 5-bit mux to select between two positions where low five bits of immediate can reside in instruction Other bits in immediate are wired to fixed positions in instruction inst[24:2] inst[3](sign-extension) inst[3:25] inst[:7] 5 4 imm[3:] I S

31 Implementing Branches B-format is mostly same as S-Format, with two register sources (rs/rs2) and a 2-bit immediate But now immediate represents values -496 to +494 in 2-byte increments The 2 immediate bits encode even 3-bit signed byte offsets (lowest bit of offset is always zero, so no need to store it)

32 Adding sw to datapath pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Reg[rs] Reg[rs2] ALU DMEM alu Addr DataR DataW mem wb inst[3:7] Imm. Gen imm[3:] inst[3:] ImmSel RegWEn Bsel ALUSel MemRW WBSel=

33 Adding branches to datapath alu pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Branch Comp. pc Reg[rs] Reg[rs2] ALU DMEM alu Addr DataR DataW mem wb inst[3:7] Imm. Gen imm[3:] PCSel inst[3:] ImmSel RegWEn BrUnBrEqBrLT BSel ASel ALUSel MemRW WBSel

34 Adding branches to datapath IMEM ALU Imm. Gen +4 DMEM Branch Comp. Reg[] AddrA AddrB DataA AddrD DataB DataD Addr DataW DataR pc inst[:7] inst[9:5] inst[24:2] inst[3:7] alu mem wb alu pc+4 Reg[rs] pc imm[3:] Reg[rs2] inst[3:] ImmSel=BRegWEn=BrUnBrEqBrLT ASel= Bsel= ALUSel=Add MemRW=Read WBSel=* PCSel=taken/not-taken wb

35 Branch Comparator A B Branch Comp. BrEq =, if A=B BrLT =, if A < B BrUn = selects unsigned comparison for BrLT, =signed BGE branch: A >= B, if!(a<b) BrUnBrEqBrLT

36 Multiply Branch Immediates by Shift? 2-bit immediate encodes PC-relative offset of -496 to +494 bytes in multiples of 2 bytes Standard approach: treat immediate as in range , then shift left by bit to multiply by 2 for branches s imm[:5] rs2 rs funct3 imm[4:] B-opcode sign-extension sign-extension s imm[:5] imm[4:] s imm[:5] imm[4:] S-Immediate B-Immediate (shift left by ) Each instruction immediate bit can appear in one of two places in output immediate value so need one 2-way mux per bit

37 RISC-V Branch Immediates 2-bit immediate encodes PC-relative offset of -496 to +494 bytes in multiples of 2 bytes RISC-V approach: keep immediate bits in fixed position in output value, and rotate LSB of S-format to be bit 2 of B-format sign=imm[] imm[:5] imm[4:] S-Immediate sign=imm[2] imm[:5] imm[4:] B-Immediate (shift left by ) imm[] Only one bit changes position between S and B, so only need a single-bit 2-way mux

38 RISC-V Immediate Encoding Instruction Encodings, inst[3:] 32-bit immediates produced, imm[3:] Upper bits sign-extended from inst[3] always Only bit 7 of instruction changes role in immediate between S and B

39 Implementing JALR Instruction (I-Format) JALR rd, rs, immediate Writes PC+4 to Reg[rd] (return address) Sets PC = Reg[rs] + immediate Uses same immediates as arithmetic and loads no multiplication by 2 bytes

40 Adding branches to datapath alu pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Branch Comp. pc Reg[rs] Reg[rs2] ALU DMEM alu Addr DataR DataW mem wb inst[3:7] Imm. Gen imm[3:] PCSel inst[3:] ImmSel RegWEn BrUnBrEqBrLT BSel ASel ALUSel MemRW WBSel

41 Adding jalr to datapath alu pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Branch Comp. pc Reg[rs] Reg[rs2] ALU DMEM alu Addr DataR DataW mem pc+4 2 wb inst[3:7] Imm. Gen imm[3:] PCSel inst[3:] ImmSel RegWEn BrUnBrEqBrLT BSel ASel ALUSel MemRW WBSel

42 Adding jalr to datapath IMEM ALU Imm. Gen +4 DMEM Branch Comp. Reg[] AddrA AddrB DataA AddrD DataB DataD Addr DataW DataR 2 pc inst[:7] inst[9:5] inst[24:2] inst[3:7] pc+4 alu mem wb alu pc+4 Reg[rs] pc imm[3:] Reg[rs2] inst[3:] ImmSel=B RegWEn= BrUn=* BrEq=*BrLT=* Asel= Bsel= ALUSel=Add MemRW=Read WBSel=2 PCSel wb

43 Implementing jal Instruction JAL saves PC+4 in Reg[rd] (the return address) Set PC = PC + offset (PC-relative jump) Target somewhere within ±2 9 locations, 2 bytes apart ± bit instructions Immediate encoding optimized similarly to branch instruction to reduce hardware cost

44 Adding jal to datapath alu pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Branch Comp. pc Reg[rs] Reg[rs2] ALU DMEM alu Addr DataR DataW mem pc+4 2 wb inst[3:7] Imm. Gen imm[3:] PCSel inst[3:] ImmSel RegWEn BrUnBrEqBrLT BSel ASel ALUSel MemRW WBSel

45 Adding jal to datapath IMEM ALU Imm. Gen +4 DMEM Branch Comp. Reg[] AddrA AddrB DataA AddrD DataB DataD Addr DataW DataR 2 pc inst[:7] inst[9:5] inst[24:2] inst[3:7] pc+4 alu mem wb alu pc+4 Reg[rs] pc imm[3:] Reg[rs2] inst[3:] ImmSel=J RegWEn= BrUn=* BrEq=*BrLT=* Asel= Bsel= ALUSel=Add MemRW=Read WBSel=2 PCSel wb

46 Upper Immediate instructions Has 2-bit immediate in upper 2 bits of 32-bit instruction word One destination register, rd Used for two instructions LUI Load Upper Immediate (add to zero) AUIPC Add Upper Immediate to PC

47 Implementing lui IMEM ALU Imm. Gen +4 DMEM Branch Comp. Reg[] AddrA AddrB DataA AddrD DataB DataD Addr DataW DataR 2 inst[:7] inst[9:5] inst[24:2] inst[3:7] pc+4 alu mem wb alu pc+4 Reg[rs] pc imm[3:] Reg[rs2] inst[3:] ImmSel=URegWEn= BrUn=* BrE=*BrLT=* Asel=* Bsel= ALUSel=BMemRW=Read WBSel= PCSel=pc+4 wb pc

48 Implementing auipc IMEM ALU Imm. Gen +4 DMEM Branch Comp. Reg[] AddrA AddrB DataA AddrD DataB DataD Addr DataW DataR 2 inst[:7] inst[9:5] inst[24:2] inst[3:7] pc+4 alu mem wb alu pc+4 Reg[rs] pc imm[3:] Reg[rs2] inst[3:] ImmSel=URegWEn= BrUn=* BrE=*BrLT=* Asel= Bsel= ALUSel=AddMemRW= WBSel= PCSel=pc+4 wb pc

49 Single-Cycle RISC-V RV32I Datapath alu pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Branch Comp. pc Reg[rs] Reg[rs2] ALU DMEM alu Addr DataR DataW mem pc+4 2 wb inst[3:7] Imm. Gen imm[3:] PCSel inst[3:] ImmSel RegWEn BrUnBrEq BrLT BSel ASel ALUSel MemRW WBSel RV32I has 47 instructions total 37 instructions were covered!

50 5 Processor Processor Control Enable? Read/Write Memory Datapath PC Registers Arithmetic & Logic Unit (ALU) Address Write Data Read Data Program Bytes Data Processor-Memory Interface

51 Single-Cycle RISC-V RV32I Datapath alu pc+4 pc +4 IMEM wb inst[:7] inst[9:5] inst[24:2] Reg[] DataD AddrD AddrADataA AddrBDataB Branch Comp. pc Reg[rs] Reg[rs2] ALU DMEM alu Addr DataR DataW mem pc+4 2 wb inst[3:7] Imm. Gen imm[3:] PCSel inst[3:] ImmSel RegWEn BrUnBrEqBrLT BSel ASel ALUSel MemRW WBSel Control Logic

52 5 2 Control Logic Truth Table (incomplete) Inst[3:] BrEq BrLT PCSel ImmSel BrUn ASel BSel ALUSel MemRW RegWEn WBSel add * * +4 * * Reg Reg Add Read ALU sub * * +4 * * Reg Reg Sub Read ALU (R-R Op) * * +4 * * Reg Reg (Op) Read ALU addi * * +4 I * Reg Imm Add Read ALU lw * * +4 I * Reg Imm Add Read Mem sw * * +4 S * Reg Imm Add Write * beq * +4 B * PC Imm Add Read * beq * ALU B * PC Imm Add Read * bne * ALU B * PC Imm Add Read * bne * +4 B * PC Imm Add Read * blt * ALU B PC Imm Add Read * bltu * ALU B PC Imm Add Read * jalr * * ALU I * Reg Imm Add Read PC+4 jal * * ALU J * PC Imm Add Read PC+4 auipc * * +4 U * PC Imm Add Read ALU

53 5 3 Control Realization Options ROM Read-Only Memory Regular structure Can be easily reprogrammed fix errors add instructions Popular when designing control logic manually Combinatorial Logic Today, chip designers use logic synthesis tools to convert truth tables to networks of gates

54 RV32I, a nine-bit ISA! inst[3] inst[4:2] inst[6:2] Not in this Lecture Instruction type encoded using only 9 bits inst[3],inst[4:2], inst[6:2]

55 第五步 : 每个控制信号的逻辑 (mini-mips 示例 ) Branch <= if (OP == BEQ) then else Jump <= if (OP == JUMP) then else ALUsrc ALUctr ExtOp MemWr <= if (OP == R-type) then RegB else Immed <= if (OP == R-type) then funct elseif (OP == ORi) then OR elseif (OP == BEQ) then Sub? else Add <= if (OP == ORi) then Zero else Sign <= (OP == Store) MemtoReg <= (OP == Load) RegWr: <= if ((OP == Store) (OP == BEQ)) then else RegDst: <= if ((OP == Load) (OP == ORi)) then else

beq jump x 3 ALUop (Symbolic) R-type Or Add Add Subtract xxx ALUop <2>

56 主控制器 ( 主控 ) 的真值表 (mini-mips 示例 ) op 6 RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp 主控 RegDst ALUSrc : ALUop R-type ori lw sw beq jump x 3 ALUop (Symbolic) R-type Or Add Add Subtract xxx ALUop <2> x func op ALUop <> x ALUop <> x 6 x x ALU 控制 ( 局部 ) x x x ALUctr x x x x 3

57 RegWrite 的真值表 (mini-mips 示例 ) op R-type ori lw sw beq jump RegWrite x x x RegWrite = R-type + ori + lw =!op<5> &!op<4> &!op<3> &!op<2> &!op<> &!op<> (Rtype) +!op<5> &!op<4> & op<3> & op<2> &!op<> & op<> (ori) + op<5> &!op<4> &!op<3> &!op<2> & op<> & op<> (lw) op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> <> op<5>.. op<> R-type ori lw sw beq jump RegWrite

58 主控的 PLA 实现 ((mini-mips 示例 )) op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> <> op<5>.. op<> R-type ori lw sw beq jump RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<> ALUop<>

59 5 9 ROM-based Control -bit address (inputs) Inst[3,4:2,6:2] BrEq BrLT 9 ROM PCSel ImmSel[2:] BrUn ASel BSel ALUSel[3:] MemRW RegWEn WBSel[:] 5 data bits (outputs)

60 Address Decoder 6 ROM Controller Implementation add sub or Control Word for add Control Word for sub Control Word for or Inst[] BrEQ BrLT jal Controller output (PCSel, ImmSel, )

61 6 Instruction Timing IF ID EX MEM WB Total I-MEM Reg Read ALU D-MEM Reg W 2 ps ps 2 ps 2 ps ps 8 ps

62 Instruction Timing Instr IF = 2ps ID = ps ALU = 2ps MEM=2ps WB = ps Total add X X X X 6ps beq X X X 5ps jal X X X 5ps lw X X X X X 8ps sw X X X X 7ps Maximum clock frequency f max = /8ps =.25 GHz Most blocks idle most of the time E.g. f max,alu = /2ps = 5 GHz! How can we keep ALU busy all the time? 5 billion adds/sec, rather than just.25 billion? Idea: Factories use three employee shifts - equipment is always busy!

63 6 3 Performance Measures Our RISC-V executes instructions at.25 GHz instruction every 8 ps Can we improve its performance? What do we mean with this statement? Not so obvious: Quicker response time, so one job finishes faster? More jobs per unit time (e.g. web server returning pages)? Longer battery life?

64 6 4 Transportation Analogy Sports Car Bus Passenger Capacity 2 5 Travel Speed 2 mph 5 mph Gas Mileage 5 mpg 2 mpg 5 Mile trip: Sports Car Bus Travel Time 5 min 6 min Time for passengers 75 min 2 min Gallons per passenger 5 gallons.5 gallons

65 Computer Analogy Transportation Computer Trip Time Time for passengers Program execution time: e.g. time to update display Throughput: e.g. number of server requests handled per hour Gallons per passenger Energy per task*: e.g. how many movies you can watch per battery charge or energy bill for datacenter * Note: power is not a good measure, since low-power CPU might run for a long time to complete one task consuming more energy than faster computer running at higher power for a shorter time

66 Iron Law of Processor Performance Time = Instructions Cycles Time Program Program * Instruction * Cycle

67 6 7 Instructions per Program Determined by Task Algorithm, e.g. O(N 2 ) vs O(N) Programming language Compiler Instruction Set Architecture (ISA)

68 6 8 (Average) Clock cycles per Instruction Determined by ISA Processor implementation (or microarchitecture) E.g. for our single-cycle RISC-V design, CPI = Complex instructions (e.g. strcpy), CPI >> Superscalar processors, CPI < (next lecture)

69 6 9 Time per Cycle (/Frequency) Determined by Processor microarchitecture (determines critical path through logic gates) Technology (e.g. 4nm versus 28nm) Power budget (lower voltages reduce transistor speed)

70 Speed Tradeoff Example For some task (e.g. image compression) Processor A Processor B # Instructions Million.5 Million Average CPI 2.5 Clock rate f 2.5 GHz 2 GHz Execution time ms.75 ms Processor B is faster for this task, despite executing more instructions and having a lower clock rate!

71 Energy per Task Energy = Instructions Energy Program Program * Instruction Energy α Instructions * C V 2 Program Program Capacitance depends on technology, processor features e.g. # of cores Supply voltage, e.g. V Want to reduce capacitance and voltage to reduce energy/task

72 72 Energy Tradeoff Example Next-generation processor C (Moore s Law): -5 % Supply voltage, V sup : -5 % Energy consumption: - (-.85) 3 = -39 % Significantly improved energy efficiency thanks to Moore s Law AND Reduced supply voltage

73 Energy Iron Law Performance = Power * Energy Efficiency (Tasks/Second) (Joules/Second) (Tasks/Joule) Energy efficiency (e.g., instructions/joule) is key metric in all computing devices For power-constrained systems (e.g., 2MW datacenter), need better energy efficiency to get more performance at same power For energy-constrained systems (e.g., W phone), need better energy efficiency to prolong battery life

74 7 4 End of Scaling In recent years, industry has not been able to reduce supply voltage much, as reducing it further would mean increasing leakage power where transistor switches don t fully turn off (more like dimmer switch than onoff switch) Also, size of transistors and hence capacitance, not shrinking as much as before between transistor generations Power becomes a growing concern the power wall Cost-effective air-cooled chip limit around ~5W

75 Processor Trends Transistors (Thousands) Frequency (MHz) Power (W) Cores [Olukotun, Hammond,Sutter,Smith,Batten]

76 7 6 Pipelining A familiar example: Getting a university degree Year Year 2 Year 3 Year 4 Shortage of Computer scientists (your startup is growing): How long does it take to educate 6,?

77 7 7 Computer Scientist Education Option : serial 4 enter 4 graduate 4 graduate 4 graduate 4 4 years Option 2: pipelining year 6, in 6 years, average throughput is /year 7 years 4 years 4 years 4 years 6, in 7 years Steady state throughput is 4/year 4 graduate Resources used efficiently 4 graduate 4-fold improvement over serial education 4 graduate 4 graduate

78 7 8 Latency versus Throughput Latency Time from entering college to graduation Serial 4 years Pipelining 4 years Throughput Average number of students graduating each year Serial Pipelining 4 Pipelining Increases throughput (4x in this example) But does nothing to latency sometimes worse (additional overhead e.g. for shift transition)

79 7 9 Simultaneous versus Sequential What happens sequentially? What happens simultaneously? 4 years 4 graduate 4 graduate 4 graduate 4 graduate 4 graduate 4 graduate 4 graduate 4 graduate 4 graduate 4 graduate

80 8 Pipelining with RISC-V Phase Pictogram t step Serial Instruction Fetch 2 ps Reg Read ps ALU 2 ps Memory 2 ps Register Write ps t instruction t instruction 8 ps t cycle Pipelined 2 ps 2 ps 2 ps 2 ps 2 ps ps instruction sequence add t, t, t2 or t3, t4, t5 sll t6, t, t3 t cycle

81 Pipelining with RISC-V instruction sequence add t, t, t2 or t3, t4, t5 sll t6, t, t3 t instruction t cycle Single Cycle Pipelining Timing t step = 2 ps t cycle = 2 ps Register access only ps All cycles same length Instruction time, t instruction = t cycle = 8 ps ps Clock rate, f s /8 ps =.25 GHz /2 ps = 5 GHz Relative speed x 4 x

82 Sequential vs Simultaneous What happens sequentially, what happens simultaneously? t instruction = ps add t, t, t2 or t3, t4, t5 instruction sequence sll t6, t, t3 sw t, 4(t3) lw t, 8(t3) addi t2, t2, t cycle = 2 ps

Microsoft PowerPoint - CA_02 Chapter5 Part-I_Single _V2.ppt

Microsoft PowerPoint - CA_02 Chapter5 Part-I_Single _V2.ppt Chapter5- The Processor: Datapath and Control (Single-cycle implementation) 臺大電機系吳安宇教授 V. 3/27/27 V2. 3/29/27 For 27 DSD Course 臺大電機吳安宇教授 - 計算機結構 Outline 5. Introduction 5.2 Logic Design Conventions 5.3