[Group 9] Give an example of structural hazard ans 1. 假設下列指令是在只有單一記憶體的 datapath 中執行 lw $5, 100($2) add $2, $7, $4 add $4, $2, $5 sw $5, 100($2)

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1 Computer Architecture Fall, 2017 Week [Group 11] 1. 請詳述為何在 MIPS 中不會發生 WAR 與 WAW 這兩種 Hazards ANS: Use simple, fixed designs WAR: 因為 Write 是第五個 Stage,Read 是第二個 Stage, 因此 Write 永遠在 Read 後面, 故不會發生 WAR WAW: 因為 Write 是第五個 Stage, 故後面的 instruction 一定會在後面才會 Write, 故不會發生 WAW [Group 1] 2. To increase the speed of memory access in pipelining, we make use of a) Special memory locations b) Special purpose registers c) Cache d) Buffers ans:(c) Simplest scheme to handle branches is to a) Flush pipeline b) Freezing pipeline c)depth of pipeline d)both a and b ans:(d)

2 [Group 9] Give an example of structural hazard ans 1. 假設下列指令是在只有單一記憶體的 datapath 中執行 lw $5, 100($2) add $2, $7, $4 add $4, $2, $5 sw $5, 100($2) 在第 4 個 CLK 時 lw 跟 sw 同時對同一個記憶體進行存取, 此時發生 structural hazard [Group 2] 4. Q2: 在什麼情況下要用 stalling 來解決 hazard 而不能用 forwarding? A: 當一個 instruction 進入到 EX stage 準備進行 ALU 計算, 但 register 還沒辦法讀到正確的值, 也就是前一個 instruction 尚未進行 write back 的程序, 這時要使用 stalling 的方式, 在在 IF/ID stage 中 insert NOP [Group 3] Forwarding 是其中一種解決 data hazard 的方式, 請試著描述 Forwarding 這個方式判斷 data hazard 的條件 Ans: 1. Rs 或 rt 的 register number 和前兩個 instruction 的 destination 相同 EX/MEM.RegisterRd=ID/EX.RegisterRs EX/MEM.RegisterRd=ID/EX.RegisterRt MEM/WB.RegisterRd=ID/EX.RegisterRs MEM/WB.RegisterRd=ID/EX.RegisterRt 2. Two optimization

A: 在第三個 cycle 就已經有運算的結果了, 會產生 data hazard 是因為我們直到第五個 cycle 才把結果寫回 register Forwarding 這個方法直接將運算出來的結果, 當作下一次運算的輸入, 這樣就不需要等待了 [Group 4] 7.

3 write instruction 才要 forward check if RegWrite is asserted Destination register 不為 $0 $0 永遠 =0 [Group 6] 6. Q: 在上周的課程中, 當遇到 data hazard 時, 我們插入 nop, 等待正確的資料為何在 R-type 的 data hazard 時, 利用 forwarding, 可以不用等待 ( 不用插入 nop)? A: 在第三個 cycle 就已經有運算的結果了, 會產生 data hazard 是因為我們直到第五個 cycle 才把結果寫回 register Forwarding 這個方法直接將運算出來的結果, 當作下一次運算的輸入, 這樣就不需要等待了 [Group 4] 7. The following sequence of MIPS instructions include a data dependency. Can the hazard be resolved by forwarding? Why? lw $t0, 0($t1) add $t2, $t0, $t1 Ans. It cannot be resolved by forwarding. The value lw writes to its destination register is not available for

4 forwarding until the lw instruction reaches the end of the MEM stage. By then, the add instruction has reached the end of the EX stage, and so forwarding is no longer possible. [Group 4] 8. The following are some statements about hazards, indicate if they are True or False. Justify your answer if they are False. a. The most efficient way to solve hazards is stalling the pipeline. b. A compiler can solve all hazards without needing to insert NOPs. c. Performance is hurt a lot if hazards are solved by stalling the pipeline. d. All hazards can be solved forwarding data between stages. Ans. a. F. Stalling the pipeline is a bad solution, since it hurts performance a lot. b. F. A compiler cannot solve all hazards by inserting NOPs, since sometimes it cannot find enough independent instructions to put between dependent ones. c. T. d. Not all hazards can be solved by forwarding data. If the value hasn t been computed yet forwarding is not an option. [Group 13] 9. Consider a 5-stage pipeline like MIPS. The finish time of branch instructions can be moved early from MEM to ID. What are the costs behind that? Is it possible, to move earlier to the IF stage? Ans: 需要增加額外硬體 (XOR array) 於 ID stage 來比較兩個暫存器是否相等不可能將 branch 完成時間移至 IF stage 因為此時尚無法擷取出暫存器內

5 容來進行比較 [Group 5] 10. Q2: Ans) Which instruction pairs will cause the data hazard? sub $2,$1,$3 add $12,$2,$5 or $13,$6,$2 and $14,$2,$2 sw $15,100($2) Sub instruction & add instruction Sub instruction & or instruction. [Group 7] 參考附圖, 寫出 forwarding 時 mux 所需的值 A: B: Ans: A:10 B:00 A: 10, B:01

[Group 9] 12. 2. Identify all of the data dependencies in the following code. Show which dependencies are data hazards?

6 [Group 9] Identify all of the data dependencies in the following code. Show which dependencies are data hazards? add $2, $5, $4 add $4, $2, $5 sw $5, 100($2) add $3, $2, $4 ans 2. data dependency data hazard $2 (1,2) (1,3) (1,4) (1,2) (1,3) $4 (2,4) (2,4) [Group 14]

7 13. Q 以下 instruction 是否發生 hazards, 請解釋如何發生並說明用何種方式處理此 hazards Str1 : lw $8 2($1) Str2 : and $4 $8 $2 Str3 : or $2 $2 $8 A load-use hazard 由於 str1 $8 要到 memory access stage 才能得到 $8, 而 str2 $8 會於 instruction decode stage read $8 所以會發在 data hazard (RAW) Waiting : Inserting Bubbles (NOP) [Group 12] 14. Which conditions below are data hazard (and we need forwarding)? (a)ex/mem.regwrite and (EX/MEM.RegRd=$0) and (EX/MEM.RegRd=ID/EX.RegRs) (b)mem/wb.regwrite and (MEM/WB.RegRd $0) and (MEM/WB.RegRt=ID/EX.RegRs) (c)ex/mem.regwrite and (EX/MEM.RegRd $0) and (EX/MEM.RegRd=ID/EX.RegRs) (d)mem/wb.regwrite and (MEM/WB.RegRd $0) and (MEM/WB.RegRd=ID/EX.RegRs) Ans: (c) (d)

Microsoft PowerPoint - CA_04 Chapter6 v ppt

Microsoft PowerPoint - CA_04 Chapter6 v ppt Chap. 6 Enhancing Performance with Pipelining 臺大電機系吳安宇教授 V1. 2007/04/20 臺大電機吳安宇教授 - 計算機結構 1 Outline 6.1 An Overview of Pipelining 6.2 A Pipelined Datapath 6.3 Pipelined Control 6.4 Data Hazards and Forwarding